commit b3b114c28f6e7c11b327fce84d93141498d5f665
author Martin Roth <martinroth@google.com> Sat Jun 24 14:00:01 2017 -0600
committer Martin Roth <martinroth@google.com> Wed Jun 28 17:48:57 2017 +0000
tree 4ca1b11a12b72dded9f8bf96ec39691621239400
parent ebade5dec9e05291f64b0687130d6fbce52270f0

src/device: add IS_ENABLED() around Kconfig symbol references

Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/device/pci_device.c

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index e423151..75e9a79 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -664,7 +664,7 @@
 			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
-#if CONFIG_VGA_ROM_RUN
+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
 static int should_run_oprom(struct device *dev)
 {
 	static int should_run = -1;
@@ -677,7 +677,7 @@
 	 */
 	should_run = display_init_required();
 
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
 	if (!should_run)
 		should_run = vboot_wants_oprom();
 #endif
@@ -706,7 +706,7 @@
 /** Default handler: only runs the relevant PCI BIOS. */
 void pci_dev_init(struct device *dev)
 {
-#if CONFIG_VGA_ROM_RUN
+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
 	struct rom_header *rom, *ram;
 
 	/* Only execute VGA ROMs. */
@@ -783,7 +783,7 @@
  */
 static struct device_operations *get_pci_bridge_ops(device_t dev)
 {
-#if CONFIG_PCIX_PLUGIN_SUPPORT
+#if IS_ENABLED(CONFIG_PCIX_PLUGIN_SUPPORT)
 	unsigned int pcixpos;
 	pcixpos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 	if (pcixpos) {
@@ -791,7 +791,7 @@
 		return &default_pcix_ops_bus;
 	}
 #endif
-#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
+#if IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)
 	unsigned int htpos = 0;
 	while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) {
 		u16 flags;
@@ -804,7 +804,7 @@
 		}
 	}
 #endif
-#if CONFIG_PCIEXP_PLUGIN_SUPPORT
+#if IS_ENABLED(CONFIG_PCIEXP_PLUGIN_SUPPORT)
 	unsigned int pciexpos;
 	pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 	if (pciexpos) {
@@ -894,7 +894,7 @@
 			goto bad;
 		dev->ops = get_pci_bridge_ops(dev);
 		break;
-#if CONFIG_CARDBUS_PLUGIN_SUPPORT
+#if IS_ENABLED(CONFIG_CARDBUS_PLUGIN_SUPPORT)
 	case PCI_HEADER_TYPE_CARDBUS:
 		dev->ops = &default_cardbus_ops_bus;
 		break;
@@ -1445,7 +1445,7 @@
 	return target_pin;
 }
 
-#if CONFIG_PC80_SYSTEM
+#if IS_ENABLED(CONFIG_PC80_SYSTEM)
 /**
  * Assign IRQ numbers.
  *
@@ -1494,7 +1494,7 @@
 		printk(BIOS_DEBUG, "  Readback = %d\n", irq);
 #endif
 
-#if CONFIG_PC80_SYSTEM
+#if IS_ENABLED(CONFIG_PC80_SYSTEM)
 		/* Change to level triggered. */
 		i8259_configure_irq_trigger(pIntAtoD[line - 1],
 					    IRQ_LEVEL_TRIGGERED);