| commit | b36100faf49c5a01e062e93b9a2fe542709fb6bd | [log] [tgz] |
|---|---|---|
| author | Angel Pons <th3fanbus@gmail.com> | Mon Sep 07 13:18:10 2020 +0200 |
| committer | Patrick Georgi <pgeorgi@google.com> | Wed Sep 09 10:34:32 2020 +0000 |
| tree | ad70742077d0185b38d72ce2ff264a3c7f81ecea | |
| parent | ee735945754180544c8bd060d6fc0b9b2c507360 [diff] [blame] |
soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbol For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`. Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 1b75cdb..1e50622 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl
@@ -21,7 +21,7 @@ /* Root Hub */ Name (_ADR, Zero) -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #include "xhci_glk_ports.asl" #else #include "xhci_apl_ports.asl"