##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Arastra, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License version 2 as
## published by the Free Software Foundation.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb

##
## Set all of the defaults for an x86 architecture
##

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end

##
## Romcc output
##
makerule ./failover.E
        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end

makerule ./failover.inc
        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end

makerule ./auto.E
        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
        action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
        action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end

##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds

##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/reset16.inc
        ldscript /cpu/x86/16bit/reset16.lds
else
        mainboardinit cpu/x86/32bit/reset32.inc
        ldscript /cpu/x86/32bit/reset32.lds
end

### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc

##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds
        mainboardinit ./failover.inc
end

###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc

##
## Include the secondary Configuration files
##
dir /pc80
config chip.h

chip northbridge/intel/i3100
        device pci_domain 0 on
                device pci 00.0 on end # IMCH
                device pci 00.1 on end # IMCH error status
                device pci 01.0 on end # IMCH EDMA engine
                device pci 02.0 on end # PCIe port A/A0
                device pci 03.0 on end # PCIe port A1
                chip southbridge/intel/i3100
                        # PIRQ line -> legacy IRQ mappings
                        register "pirq_a_d" = "0x0b070a05"
                        register "pirq_e_h" = "0x0a808080"

                        device pci 1c.0 on end # PCIe port B0
                        device pci 1c.1 on end # PCIe port B1
                        device pci 1c.2 on end # PCIe port B2
                        device pci 1c.3 on end # PCIe port B3
                        device pci 1d.0 on end # USB (UHCI) 1
                        device pci 1d.1 on end # USB (UHCI) 2
                        device pci 1d.7 on end # USB (EHCI)
                        device pci 1e.0 on end # PCI bridge
                        device pci 1e.2 on end # audio
                        device pci 1e.3 on end # modem
                        device pci 1f.0 on     # LPC bridge
                                chip superio/intel/i3100
                                        device pnp 4e.4 on # Com1
                                                 io 0x60 = 0x3f8
                                                irq 0x70 = 4
                                        end
                                        device pnp 4e.5 on # Com2
                                                 io 0x60 = 0x2f8
                                                irq 0x70 = 3
                                        end
                                end
                        end
                        device pci 1f.2 on end # SATA
                        device pci 1f.3 on end # SMBus
                end
        end
        device apic_cluster 0 on
                chip cpu/intel/socket_mPGA479M
                        device apic 0 on end
                end
        end
end