| commit | b1e4bd0d28bb65474c0a954374124f21cac05972 | [log] [tgz] |
|---|---|---|
| author | Kenji Chen <kenji.chen@intel.com> | Mon Nov 16 17:08:32 2015 +0800 |
| committer | Martin Roth <martinroth@google.com> | Thu Jan 28 20:41:14 2016 +0100 |
| tree | dbc1dcb92637367a72a7ee47b0247457d1cea1b6 | |
| parent | c4153c1b15fa88796ce3bcccb49e3537c9e65ff3 [diff] [blame] |
Braswell: Separate L1 Sub State init procedure for boards. Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: https://review.coreboot.org/12750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index f23a86c..6587d5a 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig
@@ -13,6 +13,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_BRASWELL + select PCIEXP_L1_SUB_STATE config CHROMEOS select LID_SWITCH