soc/amd/*: Hook up GPP bridges ops to devicetree

This removes the need for a PCI driver.

Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb
index 260452d..6397ce9 100644
--- a/src/soc/amd/mendocino/chipset_rembrandt.cb
+++ b/src/soc/amd/mendocino/chipset_rembrandt.cb
@@ -10,15 +10,16 @@
 		device pci 01.0 on end # Dummy Host Bridge
 
 		device pci 02.0 on end # Dummy Host Bridge, do not disable
-		device pci 02.1 alias gpp_bridge_0 off end
-		device pci 02.2 alias gpp_bridge_1 off end
-		device pci 02.3 alias gpp_bridge_2 off end
-		device pci 02.4 alias gpp_bridge_3 off end
-		device pci 02.5 alias gpp_bridge_4 off end
-		device pci 02.6 alias gpp_bridge_5 off end
+		device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end
+		device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end
+		device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end
+		device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end
+		device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end
+		device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
 
 		device pci 08.0 on end # Dummy Host Bridge, do not disable
 		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias gfx off end # Internal GPU (GFX)
 			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
 			device pci 0.2 alias crypto off end # Crypto Coprocessor
@@ -64,8 +65,9 @@
 			device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
 			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
 		end
-		device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B
+		device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B
 		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID
 		end