commit b1197af7f5aa18b17160f0c5fba9869482891cd2
author Felix Held <felix-coreboot@felixheld.de> Wed Mar 02 23:02:31 2022 +0100
committer Felix Held <felix-coreboot@felixheld.de> Thu Mar 03 22:45:28 2022 +0000
tree 21db49d4df0d514bf3ea77e298689b397841330e
parent 56b037b857e17691dfb528f969772a8acb28b2c4

soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource index

In the northbridge's and root complex' read_resources function, the
GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index
which might be misleading. Instead use idx++ as a unique index for this
resource.

TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:

Before:  PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed)
After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed)


Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8061364879d772469882fc060f92676de6f600a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/cezanne/root_complex.c

diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index e29b4e0..dabfa78 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -168,7 +168,7 @@
 	}
 
 	/* GNB IOAPIC resource */
-	gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR);
+	gnb_apic = new_resource(dev, idx++);
 	gnb_apic->base = GNB_IO_APIC_ADDR;
 	gnb_apic->size = 0x00001000;
 	gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

src/soc/amd/picasso/root_complex.c

diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c
index 076588e..a3a3d4b 100644
--- a/src/soc/amd/picasso/root_complex.c
+++ b/src/soc/amd/picasso/root_complex.c
@@ -166,7 +166,7 @@
 	}
 
 	/* GNB IOAPIC resource */
-	gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR);
+	gnb_apic = new_resource(dev, idx++);
 	gnb_apic->base = GNB_IO_APIC_ADDR;
 	gnb_apic->size = 0x00001000;
 	gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

src/soc/amd/sabrina/root_complex.c

diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c
index fc49f4f..2a3ed6f 100644
--- a/src/soc/amd/sabrina/root_complex.c
+++ b/src/soc/amd/sabrina/root_complex.c
@@ -170,7 +170,7 @@
 	}
 
 	/* GNB IOAPIC resource */
-	gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR);
+	gnb_apic = new_resource(dev, idx++);
 	gnb_apic->base = GNB_IO_APIC_ADDR;
 	gnb_apic->size = 0x00001000;
 	gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

src/soc/amd/stoneyridge/northbridge.c

diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 0a80648..0384e00 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -68,7 +68,7 @@
 	mmconf_resource(dev, idx++);
 
 	/* NB IOAPIC2 resource */
-	res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */
+	res = new_resource(dev, idx++); /* IOAPIC2 */
 	res->base = IO_APIC2_ADDR;
 	res->size = 0x00001000;
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;