tree ecb7de5786c7c9a69e7e0721bff7c6e0abbb405f
parent 1ac0dc164d81f28602668cdb559b44f18dd4227d
author Tim Wawrzynczak <twawrzynczak@chromium.org> 1638487169 -0700
committer Felix Held <felix-coreboot@felixheld.de> 1639403750 +0000

soc/intel/alderlake: Define soc_get_pcie_rp_type

In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Alder Lake. While we're
here, add PCIe RP group definitions for PCH-M chipsets.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>