commit b0d3a019413d179d624690ff4065c84cdd759584
author Tim Wawrzynczak <twawrzynczak@chromium.org> Thu Dec 02 16:19:29 2021 -0700
committer Felix Held <felix-coreboot@felixheld.de> Mon Dec 13 13:55:50 2021 +0000
tree ecb7de5786c7c9a69e7e0721bff7c6e0abbb405f
parent 1ac0dc164d81f28602668cdb559b44f18dd4227d

soc/intel/alderlake: Define soc_get_pcie_rp_type

In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Alder Lake. While we're
here, add PCIe RP group definitions for PCH-M chipsets.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/soc/intel/alderlake/Makefile.inc

diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index 3ab4d9d..6962ab2 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -22,6 +22,7 @@
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
 romstage-y += reset.c
+romstage-y += cpu.c
 
 ramstage-y += acpi.c
 ramstage-y += chip.c

src/soc/intel/alderlake/cpu.c

diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index be11527..41b69ef 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -34,7 +34,7 @@
 {
 	msr_t msr;
 
-	config_t *conf = config_of_soc();
+	const config_t *conf = config_of_soc();
 
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */

src/soc/intel/alderlake/pcie_rp.c

diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c
index 4ec24c2..dd0cfbc 100644
--- a/src/soc/intel/alderlake/pcie_rp.c
+++ b/src/soc/intel/alderlake/pcie_rp.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <device/device.h>
 #include <intelblocks/pcie_rp.h>
+#include <soc/cpu.h>
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>
 
@@ -10,9 +12,18 @@
 	{ 0 }
 };
 
+static const struct pcie_rp_group pch_m_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 2 },
+	{ 0 }
+};
+
 const struct pcie_rp_group *get_pch_pcie_rp_table(void)
 {
-	return pch_lp_rp_groups;
+	if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
+		return pch_m_rp_groups;
+
+	return pch_lp_rp_groups; /* Valid for PCH-P and PCH-N */
 }
 
 /*
@@ -28,7 +39,55 @@
 	{ 0 }
 };
 
+static const struct pcie_rp_group cpu_m_rp_groups[] = {
+	{ .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 },
+	{ 0 }
+};
+
+static const struct pcie_rp_group cpu_n_rp_groups[] = {
+	{ 0 }
+};
+
 const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
 {
+	if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
+		return cpu_m_rp_groups;
+
+	if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N))
+		return cpu_n_rp_groups;
+
 	return cpu_rp_groups;
 }
+
+static bool is_part_of_group(const struct device *dev,
+			     const struct pcie_rp_group *groups)
+{
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return false;
+
+	const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn);
+	const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn);
+	const struct pcie_rp_group *group;
+	unsigned int i;
+	unsigned int fn;
+
+	for (group = groups; group->count; ++group) {
+		for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) {
+			if (slot_to_find == group->slot && fn_to_find == fn)
+				return true;
+		}
+	}
+
+	return false;
+}
+
+enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
+{
+	if (is_part_of_group(dev, pch_lp_rp_groups))
+		return PCIE_RP_PCH;
+
+	if (CONFIG_MAX_CPU_ROOT_PORTS && is_part_of_group(dev, cpu_rp_groups))
+		return PCIE_RP_CPU;
+
+	return PCIE_RP_UNKNOWN;
+}