commit b01097e0fe03b7dc81eadd898ff380b57f291852
author Zheng Bao <fishbaozi@gmail.com> Fri Dec 14 15:58:15 2012 +0800
committer Marc Jones <marcj303@gmail.com> Fri Dec 28 21:16:42 2012 +0100
tree 333c446ea37ebb98f73b01cd2bced56119530e46
parent ceb82da99f9b9bc0629b6e3689dd19c988f4cd0b

USBDEBUG: Enable the EHCI in AMD Southbridge

Since SB800, USB2.0 debug port is dev 0x12, func 2.

Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1880
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>

src/southbridge/amd/cimx/sb800/Makefile.inc

diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 064cbc7..de9b979 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -32,6 +32,9 @@
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
 
+romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+
 ramstage-y   += smbus.c
 ramstage-y   += lpc.c