commit afb143dadbe3d516e7795e6eeb97367aeb7d4c41
author Maulik V Vaghela <maulik.v.vaghela@intel.com> Fri Jan 29 22:42:08 2021 +0530
committer Patrick Georgi <pgeorgi@google.com> Tue Apr 06 07:51:05 2021 +0000
tree 1b398597628fc8077ce5f52943a46a206bba153f
parent ac91fca8a0277686cf03650f13ff9d39a5882f7c

soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M

Added new LPC and IGD device IDs for Alderlake M.
Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c

TEST=Check if platform information print is coming properly in coreboot

Change-Id: If33c43da8cbd786261b00742e342f0f01622c607
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/graphics/graphics.c

diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index ca96f35..0920a05 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -296,6 +296,7 @@
 	PCI_DEVICE_ID_INTEL_ADL_GT1_9,
 	PCI_DEVICE_ID_INTEL_ADL_P_GT2,
 	PCI_DEVICE_ID_INTEL_ADL_S_GT1,
+	PCI_DEVICE_ID_INTEL_ADL_M_GT1,
 	0,
 };