mb/google/brox: Fix pulls as necessary
Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes in this CL include fixing the pulls for
GPIOs as necessary, making sure that it matches what is in the HW
team's spreadsheet.
BUG=b:300690448
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: Ie50cb3c6fc85f1633c1afd1330c0e040e04b0ec1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79704
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 217390a..baff251 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -118,9 +118,9 @@
/* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> NOTE_BOOK_MODE (NC initially) */
PAD_NC(GPP_B17, NONE),
/* GPP_B18 : GPP_B18 ==> GPP_B18_STRAP */
- PAD_NC(GPP_B18, DN_20K),
+ PAD_NC(GPP_B18, NONE),
/* GPP_B23 : SML1ALERT_L/PCHHOT_L ==> PCHHOT_ODL_STRAP */
- PAD_CFG_GPI(GPP_B23, DN_20K, DEEP),
+ PAD_CFG_GPI(GPP_B23, NONE, DEEP),
/* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SOC_GPP_C0 (NC) */
PAD_NC(GPP_C0, NONE),
@@ -164,7 +164,7 @@
/* GPP_D11 : [] ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_D11, 1, DEEP),
/* GPP_D12 : [NF1: ISH_SPI_MOSI NF2: DDP4_CTRLDATA NF4: TBT_LSX3_RXD NF5: BSSB_LS3_TX NF6: USB_C_GPP_D12 NF7: GSPI2_MOSI] ==> SOC_GPP_D12 (NC) */
- PAD_NC(GPP_D12, DN_20K),
+ PAD_NC(GPP_D12, NONE),
/* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* GPP_D14 : [NF1: ISH_UART0_TXD NF3: I2C6_SCL NF6: USB_C_GPP_D14] ==> UART0_ISH_TX_DBG_RX */
@@ -223,16 +223,16 @@
/* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX NF6: USB_C_GPP_E20] ==> SOC_GPP_E20 (NC) */
PAD_NC(GPP_E20, NONE),
/* GPP_E21 : DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX ==> USB_C1_LSX_RX_STRAP */
- PAD_NC(GPP_E21, DN_20K),
+ PAD_NC(GPP_E21, NONE),
/* GPP_E22 : DDPA_CTRLCLK/DNX_FORCE_RELOAD ==> USB_C0_AUX_DC_STRAP_P */
- PAD_NC(GPP_E22, DN_20K),
+ PAD_NC(GPP_E22, NONE),
/* GPP_E23 : [NF1: DDPA_CTRLDATA] ==> USB_C0_AUX_DC_N */
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
/* GPP_F0 : [NF1: CNV_BRI_DT NF2: UART2_RTS# NF6: USB_C_GPP_F0] ==> CNV_BRI_DT_STRAP */
- PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F0, UP_20K, DEEP, NF1),
/* GPP_F1 : [NF1: CNV_BRI_RSP NF2: UART2_RXD NF6: USB_C_GPP_F1] ==> CNV_BRI_RSP */
- PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
/* GPP_F2 : [NF1: CNV_RGI_DT NF2: UART2_TXD NF6: USB_C_GPP_F2] ==> CNV_RGI_DT_STRAP */
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
/* GPP_F3 : [NF1: CNV_RGI_RSP NF2: UART2_CTS# NF6: USB_C_GPP_F3] ==> CNV_RGI_RSP */
@@ -248,7 +248,7 @@
/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_F9, 1, PLTRST),
/* GPP_F10 : GPP_F10 ==> GPP_F10_STRAP (NC) */
- PAD_NC(GPP_F10, DN_20K),
+ PAD_NC(GPP_F10, NONE),
/* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> SOC_GPP_F11 (NC) */
PAD_NC(GPP_F11, NONE),
/* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL NF6: USB_C_GPP_F12] ==> SOC_GPP_F12 (NC) */