resolve conflict
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index b7ff4c0..36d59c3 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -7,7 +7,27 @@
#define GLCP_DELAY_CONTROLS 0x4c00000f
#define GLCP_SYS_RSTPLL 0x4c000014
#define GLCP_DOTPLL 0x4c000015
-#define GLCP_CHIP_REVID 0x4c000017
+#define GLCP_CHIP_REVID 0x4c000017
+
+/* GLCP_SYS_RSTPLL, Upper 32 bits */
+#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
+#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
+#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
+
+/* GLCP_SYS_RSTPLL, Lower 32 bits */
+#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
+#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
+
+#define GLCP_SYS_RSTPLL_LOCKWAIT 24
+#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
+#define GLCP_SYS_RSTPLL_BYPASS 15
+#define GLCP_SYS_RSTPLL_PD 14
+#define GLCP_SYS_RSTPLL_RESETPLL 13
+#define GLCP_SYS_RSTPLL_DDRMODE 10
+#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
+#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
+#define GLCP_SYS_RSTPLL_CHIP_RESET 0
+
/* MSR routing as follows*/
/* MSB = 1 means not for CPU*/
/* next 3 bits 1st port*/
@@ -272,23 +292,4 @@
#define VG_GLD_MSR_CONFIG MSR_VG + 0x2001
#define VG_GLD_MSR_PM MSR_VG + 0x2004
- /* Upper 32 bits */
-#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
-#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
-#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
-
- /* Lower 32 bits */
-#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
-#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
-
-#define GLCP_SYS_RSTPLL_LOCKWAIT 24
-#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
-#define GLCP_SYS_RSTPLL_BYPASS 15
-#define GLCP_SYS_RSTPLL_PD 14
-#define GLCP_SYS_RSTPLL_RESETPLL 13
-#define GLCP_SYS_RSTPLL_DDRMODE 10
-#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
-#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
-#define GLCP_SYS_RSTPLL_CHIP_RESET 0
-
#endif /* CPU_AMD_GX2DEF_H */