sb/intel: Use `bool` for PCIe coalescing option
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 5f21e61..30773e6 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -28,7 +28,7 @@
u32 b0d28f0_32c;
u32 b0d28f4_32c;
u32 b0d28f5_32c;
- int coalesce;
+ bool coalesce;
int gbe_port;
int num_ports;
struct device *ports[MAX_NUM_ROOT_PORTS];
@@ -304,7 +304,7 @@
/* If the first root port is disabled the coalesce ports. */
if (!is_rp_enabled(1))
- rpc.coalesce = 1;
+ rpc.coalesce = true;
/* Perform clock gating configuration. */
pcie_enable_clock_gating();