sb/intel: Use `bool` for PCIe coalescing option
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index 0570cdc..ad8e50c 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -33,7 +33,7 @@
register "pcie_port_force_aspm" = "0x10"
# Enable port coalescing
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index 0a92efe..cfb4812 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -36,7 +36,7 @@
# Force enable ASPM for PCIe Port 3
register "pcie_port_force_aspm" = "0x04"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013b0000"
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index 8c54f6a..8eada25 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -44,7 +44,7 @@
register "pcie_port_force_aspm" = "0x10"
# Enable port coalescing
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 725cbd1..c79526e 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -58,7 +58,7 @@
register "gen2_dec" = "0x00040381"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index 08b2c95..e972baa 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -38,7 +38,7 @@
register "pcie_port_force_aspm" = "0x10"
# Enable port coalescing
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index fda74da..49c3476 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -56,7 +56,7 @@
register "gen2_dec" = "0x00fc0901"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index d748277..6850cf2 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -54,7 +54,7 @@
register "gen2_dec" = "0x00040069"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index ad700ce..b38adaf 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -61,7 +61,7 @@
register "gen3_dec" = "0x0001C1611"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1