commit | af4bad167d4ab07ba2d44666c878a0871d7f91cd | [log] [tgz] |
---|---|---|
author | Xi Chen <xixi.chen@mediatek.corp-partner.google.com> | Thu Aug 18 11:27:18 2022 +0800 |
committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | Wed Aug 31 16:44:46 2022 +0000 |
tree | ca8071405b2eefeb199add572cb7f24231a92763 | |
parent | df0396149aba5171d64b9fbab0856dc9f07b1c15 [diff] |
soc/mediatek/mt8188: Initialize DPM in ramstage Add initialization of DPM drvier for DRAM low power mode. DPM is an essential component on MediaTek SoC, so we initialize DPM in soc_init(). This DPM flow adds 22ms to the boot time. coreboot logs: CBFS: Found 'dpm.dm' @0x156c0 size 0xfc in mcache @0xfffdd110 mtk_init_mcu: Loaded (and reset) dpm.dm in 6 msecs (422 bytes) CBFS: Found 'dpm.pm' @0x15800 size 0x3c59 in mcache @0xfffdd140 mtk_init_mcu: Loaded (and reset) dpm.pm in 16 msecs (18910 bytes) TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I46baa7b49e90d53dd4d1d95af9c46622faf30419 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66969 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.