diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index bd0d8ef..d645a53 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -22,8 +22,8 @@
 
 cd $(dirname $0)
 
-CROSSGCC_DATE="June 17th, 2015"
-CROSSGCC_VERSION="1.31"
+CROSSGCC_DATE="July 17th, 2015"
+CROSSGCC_VERSION="1.32"
 
 # default settings
 PACKAGE=GCC
@@ -38,7 +38,7 @@
 MPFR_VERSION=3.1.2
 MPC_VERSION=1.0.3
 LIBELF_VERSION=0.8.13
-GCC_VERSION=4.9.2
+GCC_VERSION=5.2.0
 GCC_AUTOCONF_VERSION=2.69
 BINUTILS_VERSION=2.25
 GDB_VERSION=7.9.1
diff --git a/util/crossgcc/patches/binutils-2.25_riscv.patch b/util/crossgcc/patches/binutils-2.25_riscv.patch
index 66d42e4..ebe2f37 100644
--- a/util/crossgcc/patches/binutils-2.25_riscv.patch
+++ b/util/crossgcc/patches/binutils-2.25_riscv.patch
@@ -1,133 +1,6 @@
-Created from https://github.com/riscv/riscv-gnu-toolchain,
-commit ddce5d17f14831f4957e57c415aca77817c2a82c
-
-diff -urN original-binutils/bfd/archures.c binutils/bfd/archures.c
---- original-binutils/bfd/archures.c	2014-10-14 09:32:02.000000000 +0200
-+++ binutils-2.25/bfd/archures.c	2015-03-07 09:55:02.355135671 +0100
-@@ -597,6 +597,7 @@
- extern const bfd_arch_info_type bfd_plugin_arch;
- extern const bfd_arch_info_type bfd_powerpc_archs[];
- #define bfd_powerpc_arch bfd_powerpc_archs[0]
-+extern const bfd_arch_info_type bfd_riscv_arch;
- extern const bfd_arch_info_type bfd_rs6000_arch;
- extern const bfd_arch_info_type bfd_rl78_arch;
- extern const bfd_arch_info_type bfd_rx_arch;
-@@ -683,6 +684,7 @@
-     &bfd_or1k_arch,
-     &bfd_pdp11_arch,
-     &bfd_powerpc_arch,
-+    &bfd_riscv_arch,
-     &bfd_rs6000_arch,
-     &bfd_rl78_arch,
-     &bfd_rx_arch,
-diff -urN original-binutils/bfd/bfd-in2.h binutils/bfd/bfd-in2.h
---- original-binutils/bfd/bfd-in2.h	2014-11-04 10:54:41.000000000 +0100
-+++ binutils-2.25/bfd/bfd-in2.h	2015-03-07 09:55:02.359135671 +0100
-@@ -2043,6 +2043,9 @@
- #define bfd_mach_ppc_e6500     5007
- #define bfd_mach_ppc_titan     83
- #define bfd_mach_ppc_vle       84
-+  bfd_arch_riscv, /* RISC-V */
-+#define bfd_mach_riscv32 132
-+#define bfd_mach_riscv64 164
-   bfd_arch_rs6000,    /* IBM RS/6000 */
- #define bfd_mach_rs6k          6000
- #define bfd_mach_rs6k_rs1      6001
-@@ -5531,6 +5534,41 @@
- value in a word.  The relocation is relative offset from  */
-   BFD_RELOC_MICROBLAZE_32_GOTOFF,
- 
-+/* RISC-V relocations */
-+  BFD_RELOC_RISCV_HI20,
-+  BFD_RELOC_RISCV_PCREL_HI20,
-+  BFD_RELOC_RISCV_PCREL_LO12_I,
-+  BFD_RELOC_RISCV_PCREL_LO12_S,
-+  BFD_RELOC_RISCV_LO12_I,
-+  BFD_RELOC_RISCV_LO12_S,
-+  BFD_RELOC_RISCV_GPREL12_I,
-+  BFD_RELOC_RISCV_GPREL12_S,
-+  BFD_RELOC_RISCV_TPREL_HI20,
-+  BFD_RELOC_RISCV_TPREL_LO12_I,
-+  BFD_RELOC_RISCV_TPREL_LO12_S,
-+  BFD_RELOC_RISCV_TPREL_ADD,
-+  BFD_RELOC_RISCV_CALL,
-+  BFD_RELOC_RISCV_CALL_PLT,
-+  BFD_RELOC_RISCV_ADD8,
-+  BFD_RELOC_RISCV_ADD16,
-+  BFD_RELOC_RISCV_ADD32,
-+  BFD_RELOC_RISCV_ADD64,
-+  BFD_RELOC_RISCV_SUB8,
-+  BFD_RELOC_RISCV_SUB16,
-+  BFD_RELOC_RISCV_SUB32,
-+  BFD_RELOC_RISCV_SUB64,
-+  BFD_RELOC_RISCV_GOT_HI20,
-+  BFD_RELOC_RISCV_TLS_GOT_HI20,
-+  BFD_RELOC_RISCV_TLS_GD_HI20,
-+  BFD_RELOC_RISCV_JMP,
-+  BFD_RELOC_RISCV_TLS_DTPMOD32,
-+  BFD_RELOC_RISCV_TLS_DTPREL32,
-+  BFD_RELOC_RISCV_TLS_DTPMOD64,
-+  BFD_RELOC_RISCV_TLS_DTPREL64,
-+  BFD_RELOC_RISCV_TLS_TPREL32,
-+  BFD_RELOC_RISCV_TLS_TPREL64,
-+  BFD_RELOC_RISCV_ALIGN,
-+
- /* This is used to tell the dynamic linker to copy the value out of
- the dynamic object into the runtime process image.  */
-   BFD_RELOC_MICROBLAZE_COPY,
-diff -urN original-binutils/bfd/config.bfd binutils/bfd/config.bfd
---- original-binutils/bfd/config.bfd	2014-10-14 09:32:02.000000000 +0200
-+++ binutils-2.25/bfd/config.bfd	2015-03-07 09:55:02.359135671 +0100
-@@ -119,6 +119,7 @@
- pdp11*)		 targ_archs=bfd_pdp11_arch ;;
- pj*)		 targ_archs="bfd_pj_arch bfd_i386_arch";;
- powerpc*)	 targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
-+riscv*)		 targ_archs=bfd_riscv_arch ;;
- rs6000)		 targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
- s390*)		 targ_archs=bfd_s390_arch ;;
- sh*)		 targ_archs=bfd_sh_arch ;;
-@@ -1319,6 +1320,14 @@
-     targ_defvec=rl78_elf32_vec
-     ;;
- 
-+#ifdef BFD64
-+  riscv*-*-*)
-+    targ_defvec=riscv_elf64_vec
-+    targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
-+    want64=true
-+    ;;
-+#endif
-+
-   rx-*-elf)
-     targ_defvec=rx_elf32_le_vec
-     targ_selvecs="rx_elf32_be_vec rx_elf32_le_vec rx_elf32_be_ns_vec"
-diff -urN original-binutils/bfd/configure binutils/bfd/configure
---- original-binutils/bfd/configure	2014-12-23 15:22:04.000000000 +0100
-+++ binutils-2.25/bfd/configure	2015-03-07 09:55:02.367135671 +0100
-@@ -15506,6 +15506,8 @@
-     powerpc_pei_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
-     powerpc_pei_le_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
-     powerpc_xcoff_vec)		 tb="$tb coff-rs6000.lo xcofflink.lo" ;;
-+    riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
-+    riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
-     rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
-     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
-     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
-diff -urN original-binutils/bfd/configure.ac binutils/bfd/configure.ac
---- original-binutils/bfd/configure.ac	2014-10-14 09:32:02.000000000 +0200
-+++ binutils-2.25/bfd/configure.ac	2015-03-07 09:55:02.367135671 +0100
-@@ -907,6 +907,8 @@
-     powerpc_pei_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
-     powerpc_pei_le_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
-     powerpc_xcoff_vec)		 tb="$tb coff-rs6000.lo xcofflink.lo" ;;
-+    riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
-+    riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
-     rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
-     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
-     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
-diff -urN original-binutils/bfd/cpu-riscv.c binutils/bfd/cpu-riscv.c
---- original-binutils/bfd/cpu-riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/bfd/cpu-riscv.c	2015-03-07 09:51:45.655139025 +0100
+diff -urN empty/bfd/cpu-riscv.c binutils-2.25/bfd/cpu-riscv.c
+--- empty/bfd/cpu-riscv.c	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/bfd/cpu-riscv.c	2015-07-18 00:02:36.218287546 +0200
 @@ -0,0 +1,80 @@
 +/* BFD backend for RISC-V
 +   Copyright 2011-2014 Free Software Foundation, Inc.
@@ -209,21 +82,10 @@
 +
 +const bfd_arch_info_type bfd_riscv_arch =
 +N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]);
-diff -urN original-binutils/bfd/elf-bfd.h binutils/bfd/elf-bfd.h
---- original-binutils/bfd/elf-bfd.h	2014-12-23 09:47:10.000000000 +0100
-+++ binutils-2.25/bfd/elf-bfd.h	2015-03-07 09:55:02.367135671 +0100
-@@ -433,6 +433,7 @@
-   XGATE_ELF_DATA,
-   TILEGX_ELF_DATA,
-   TILEPRO_ELF_DATA,
-+  RISCV_ELF_DATA,
-   GENERIC_ELF_DATA
- };
- 
-diff -urN original-binutils/bfd/elfnn-riscv.c binutils/bfd/elfnn-riscv.c
---- original-binutils/bfd/elfnn-riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/bfd/elfnn-riscv.c	2015-03-07 09:51:45.655139025 +0100
-@@ -0,0 +1,2954 @@
+diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
+--- empty/bfd/elfnn-riscv.c	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/bfd/elfnn-riscv.c	2015-07-18 00:02:36.218287546 +0200
+@@ -0,0 +1,2995 @@
 +/* RISC-V-specific support for NN-bit ELF.
 +   Copyright 2011-2014 Free Software Foundation, Inc.
 +
@@ -803,6 +665,8 @@
 +	case R_RISCV_CALL:
 +	case R_RISCV_JAL:
 +	case R_RISCV_BRANCH:
++	case R_RISCV_RVC_BRANCH:
++	case R_RISCV_RVC_JUMP:
 +	case R_RISCV_PCREL_HI20:
 +	  /* In shared libs, these relocs are known to bind locally.  */
 +	  if (info->shared)
@@ -1042,6 +906,8 @@
 +	case R_RISCV_BRANCH:
 +	case R_RISCV_CALL:
 +	case R_RISCV_JAL:
++	case R_RISCV_RVC_BRANCH:
++	case R_RISCV_RVC_JUMP:
 +	  if (info->shared)
 +	    break;
 +	  /* Fall through.  */
@@ -1086,6 +952,7 @@
 +  /* Make sure we know what is going on here.  */
 +  BFD_ASSERT (dynobj != NULL
 +	      && (h->needs_plt
++		  || h->type == STT_GNU_IFUNC
 +		  || h->u.weakdef != NULL
 +		  || (h->def_dynamic
 +		      && h->ref_regular
@@ -1094,7 +961,7 @@
 +  /* If this is a function, put it in the procedure linkage table.  We
 +     will fill in the contents of the procedure linkage table later
 +     (although we could actually do it here).  */
-+  if (h->type == STT_FUNC || h->needs_plt)
++  if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
 +    {
 +      if (h->plt.refcount <= 0
 +	  || SYMBOL_CALLS_LOCAL (info, h)
@@ -1731,6 +1598,18 @@
 +      value = ENCODE_SBTYPE_IMM (value);
 +      break;
 +
++    case R_RISCV_RVC_BRANCH:
++      if (!VALID_RVC_B_IMM (value))
++	return bfd_reloc_overflow;
++      value = ENCODE_RVC_B_IMM (value);
++      break;
++
++    case R_RISCV_RVC_JUMP:
++      if (!VALID_RVC_J_IMM (value))
++	return bfd_reloc_overflow;
++      value = ENCODE_RVC_J_IMM (value);
++      break;
++
 +    case R_RISCV_32:
 +    case R_RISCV_64:
 +    case R_RISCV_ADD8:
@@ -2001,6 +1880,7 @@
 +	  continue;
 +
 +	case R_RISCV_BRANCH:
++	case R_RISCV_RVC_BRANCH:
 +	case R_RISCV_HI20:
 +	  /* These require no special handling beyond perform_relocation.  */
 +	  break;
@@ -2109,6 +1989,7 @@
 +	case R_RISCV_CALL_PLT:
 +	case R_RISCV_CALL:
 +	case R_RISCV_JAL:
++	case R_RISCV_RVC_JUMP:
 +	  if (info->shared && h != NULL && h->plt.offset != MINUS_ONE)
 +	    {
 +	      /* Refer to the PLT entry.  */
@@ -2890,12 +2771,12 @@
 +{
 +  bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
 +  bfd_signed_vma foff = symval - (sec_addr (sec) + rel->r_offset);
-+  bfd_boolean near_zero = !link_info->shared && symval < RISCV_IMM_REACH/2;
++  bfd_boolean near_zero = (symval + RISCV_IMM_REACH/2) < RISCV_IMM_REACH;
 +  bfd_vma auipc, jalr;
-+  int r_type;
++  int rd, r_type, len = 4, rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
 +
 +  /* See if this function call can be shortened.  */
-+  if (!VALID_UJTYPE_IMM (foff) && !near_zero)
++  if (!VALID_UJTYPE_IMM (foff) && !(!link_info->shared && near_zero))
 +    return TRUE;
 +
 +  /* Shorten the function call.  */
@@ -2903,28 +2784,37 @@
 +
 +  auipc = bfd_get_32 (abfd, contents + rel->r_offset);
 +  jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4);
++  rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
++  rvc = rvc && VALID_RVC_J_IMM (foff);
 +
-+  if (VALID_UJTYPE_IMM (foff))
++  if (rvc && (rd == 0 || rd == X_RA))
++    {
++      /* Relax to C.J[AL] rd, addr.  */
++      r_type = R_RISCV_RVC_JUMP;
++      auipc = rd == 0 ? MATCH_C_J : MATCH_C_JAL;
++      len = 2;
++    }
++  else if (VALID_UJTYPE_IMM (foff))
 +    {
 +      /* Relax to JAL rd, addr.  */
 +      r_type = R_RISCV_JAL;
-+      auipc = (jalr & (OP_MASK_RD << OP_SH_RD)) | MATCH_JAL;
++      auipc = MATCH_JAL | (rd << OP_SH_RD);
 +    }
 +  else /* near_zero */
 +    {
 +      /* Relax to JALR rd, x0, addr.  */
 +      r_type = R_RISCV_LO12_I;
-+      auipc = (jalr & (OP_MASK_RD << OP_SH_RD)) | MATCH_JALR;
++      auipc = MATCH_JALR | (rd << OP_SH_RD);
 +    }
 +
 +  /* Replace the R_RISCV_CALL reloc.  */
 +  rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), r_type);
 +  /* Replace the AUIPC.  */
-+  bfd_put_32 (abfd, auipc, contents + rel->r_offset);
++  bfd_put (8 * len, abfd, auipc, contents + rel->r_offset);
 +
 +  /* Delete unnecessary JALR.  */
 +  *again = TRUE;
-+  return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + 4, 4);
++  return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + len, 8 - len);
 +}
 +
 +/* Relax non-PIC global variable references.  */
@@ -2982,28 +2872,40 @@
 +			bfd_vma symval,
 +			bfd_boolean *again ATTRIBUTE_UNUSED)
 +{
-+  bfd_vma alignment = 1;
++  bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
++  bfd_vma alignment = 1, pos;
 +  while (alignment <= rel->r_addend)
 +    alignment *= 2;
 +
 +  symval -= rel->r_addend;
 +  bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment;
-+  bfd_vma nop_bytes_needed = aligned_addr - symval;
++  bfd_vma nop_bytes = aligned_addr - symval;
++
++  /* Once we've handled an R_RISCV_ALIGN, we can't relax anything else.  */
++  sec->sec_flg0 = TRUE;
 +
 +  /* Make sure there are enough NOPs to actually achieve the alignment.  */
-+  if (rel->r_addend < nop_bytes_needed)
++  if (rel->r_addend < nop_bytes)
 +    return FALSE;
 +
 +  /* Delete the reloc.  */
 +  rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
 +
 +  /* If the number of NOPs is already correct, there's nothing to do.  */
-+  if (nop_bytes_needed == rel->r_addend)
++  if (nop_bytes == rel->r_addend)
 +    return TRUE;
 +
-+  /* Delete the excess NOPs.  */
-+  return riscv_relax_delete_bytes (abfd, sec, rel->r_offset,
-+				   rel->r_addend - nop_bytes_needed);
++  /* Write as many RISC-V NOPs as we need.  */
++  for (pos = 0; pos < (nop_bytes & -4); pos += 4)
++    bfd_put_32 (abfd, RISCV_NOP, contents + rel->r_offset + pos);
++
++  /* Write a final RVC NOP if need be.  */
++  if (nop_bytes % 4 != 0)
++    bfd_put_16 (abfd, RVC_NOP, contents + rel->r_offset + pos);
++
++  /* Delete the excess bytes.  */
++  return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes,
++				   rel->r_addend - nop_bytes);
 +}
 +
 +/* Relax a section.  Pass 0 shortens code sequences unless disabled.
@@ -3023,6 +2925,7 @@
 +  *again = FALSE;
 +
 +  if (info->relocatable
++      || sec->sec_flg0
 +      || (sec->flags & SEC_RELOC) == 0
 +      || sec->reloc_count == 0
 +      || (info->disable_target_specific_optimizations
@@ -3039,7 +2942,7 @@
 +  /* Examine and consider relaxing each reloc.  */
 +  for (i = 0; i < sec->reloc_count; i++)
 +    {
-+      Elf_Internal_Rela *rel = data->relocs + i;
++      Elf_Internal_Rela *rel = relocs + i;
 +      typeof(&_bfd_riscv_relax_call) relax_func = NULL;
 +      int type = ELFNN_R_TYPE (rel->r_info);
 +      bfd_vma symval;
@@ -3178,10 +3081,10 @@
 +#define elf_backend_default_execstack 0
 +
 +#include "elfNN-target.h"
-diff -urN original-binutils/bfd/elfxx-riscv.c binutils/bfd/elfxx-riscv.c
---- original-binutils/bfd/elfxx-riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/bfd/elfxx-riscv.c	2015-03-07 09:51:45.659139025 +0100
-@@ -0,0 +1,730 @@
+diff -urN empty/bfd/elfxx-riscv.c binutils-2.25/bfd/elfxx-riscv.c
+--- empty/bfd/elfxx-riscv.c	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/bfd/elfxx-riscv.c	2015-07-18 00:02:36.218287546 +0200
+@@ -0,0 +1,765 @@
 +/* RISC-V-specific support for ELF.
 +   Copyright 2011-2014 Free Software Foundation, Inc.
 +
@@ -3823,6 +3726,39 @@
 +	 0,			/* src_mask */
 +	 0,			/* dst_mask */
 +	 TRUE),			/* pcrel_offset */
++
++  /* 8-bit PC-relative branch offset.  */
++  HOWTO (R_RISCV_RVC_BRANCH,	/* type */
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 TRUE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_signed, /* complain_on_overflow */
++	 bfd_elf_generic_reloc,	/* special_function */
++	 "R_RISCV_RVC_BRANCH",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 ENCODE_RVC_B_IMM(-1U),	/* dst_mask */
++	 TRUE),			/* pcrel_offset */
++
++  /* 11-bit PC-relative jump offset.  */
++  HOWTO (R_RISCV_RVC_JUMP,	/* type */
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 TRUE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++				/* This needs complex overflow
++				   detection, because the upper 36
++				   bits must match the PC + 4.  */
++	 bfd_elf_generic_reloc,	/* special_function */
++	 "R_RISCV_RVC_JUMP",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 ENCODE_RVC_J_IMM(-1U),	/* dst_mask */
++	 TRUE),		/* pcrel_offset */
 +};
 +
 +/* A mapping from BFD reloc types to RISC-V ELF reloc types.  */
@@ -3870,6 +3806,8 @@
 +  { BFD_RELOC_RISCV_TLS_GOT_HI20, R_RISCV_TLS_GOT_HI20 },
 +  { BFD_RELOC_RISCV_TLS_GD_HI20, R_RISCV_TLS_GD_HI20 },
 +  { BFD_RELOC_RISCV_ALIGN, R_RISCV_ALIGN },
++  { BFD_RELOC_RISCV_RVC_BRANCH, R_RISCV_RVC_BRANCH },
++  { BFD_RELOC_RISCV_RVC_JUMP, R_RISCV_RVC_JUMP },
 +};
 +
 +/* Given a BFD reloc type, return a howto structure.  */
@@ -3912,9 +3850,9 @@
 +    }
 +  return &howto_table[r_type];
 +}
-diff -urN original-binutils/bfd/elfxx-riscv.h binutils/bfd/elfxx-riscv.h
---- original-binutils/bfd/elfxx-riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/bfd/elfxx-riscv.h	2015-03-07 09:51:45.659139025 +0100
+diff -urN empty/bfd/elfxx-riscv.h binutils-2.25/bfd/elfxx-riscv.h
+--- empty/bfd/elfxx-riscv.h	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/bfd/elfxx-riscv.h	2015-07-18 00:02:36.218287546 +0200
 @@ -0,0 +1,34 @@
 +/* RISC-V ELF specific backend routines.
 +   Copyright 2011-2014 Free Software Foundation, Inc.
@@ -3950,158 +3888,10 @@
 +
 +extern reloc_howto_type *
 +riscv_elf_rtype_to_howto (unsigned int r_type);
-diff -urN original-binutils/bfd/Makefile.am binutils/bfd/Makefile.am
---- original-binutils/bfd/Makefile.am	2014-10-14 09:32:02.000000000 +0200
-+++ binutils-2.25/bfd/Makefile.am	2015-03-07 09:55:02.371135671 +0100
-@@ -931,6 +931,18 @@
- 	sed -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
- 	mv -f elf64-ia64.new elf64-ia64.c
- 
-+elf32-riscv.c : elfnn-riscv.c
-+	rm -f elf32-riscv.c
-+	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new
-+	sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new
-+	mv -f elf32-riscv.new elf32-riscv.c
-+
-+elf64-riscv.c : elfnn-riscv.c
-+	rm -f elf64-riscv.c
-+	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new
-+	sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new
-+	mv -f elf64-riscv.new elf64-riscv.c
-+
- peigen.c : peXXigen.c
- 	rm -f peigen.c
- 	sed -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
-diff -urN original-binutils/bfd/Makefile.in binutils/bfd/Makefile.in
---- original-binutils/bfd/Makefile.in	2014-10-14 09:32:02.000000000 +0200
-+++ binutils-2.25/bfd/Makefile.in	2015-03-07 09:55:02.371135671 +0100
-@@ -2009,6 +2009,18 @@
- 	sed -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
- 	mv -f elf64-ia64.new elf64-ia64.c
- 
-+elf32-riscv.c : elfnn-riscv.c
-+	rm -f elf32-riscv.c
-+	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new
-+	sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new
-+	mv -f elf32-riscv.new elf32-riscv.c
-+
-+elf64-riscv.c : elfnn-riscv.c
-+	rm -f elf64-riscv.c
-+	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new
-+	sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new
-+	mv -f elf64-riscv.new elf64-riscv.c
-+
- peigen.c : peXXigen.c
- 	rm -f peigen.c
- 	sed -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
-diff -urN original-binutils/bfd/targets.c binutils/bfd/targets.c
---- original-binutils/bfd/targets.c	2014-11-04 10:54:41.000000000 +0100
-+++ binutils-2.25/bfd/targets.c	2015-03-07 09:55:02.371135671 +0100
-@@ -784,6 +784,8 @@
- extern const bfd_target powerpc_pei_vec;
- extern const bfd_target powerpc_pei_le_vec;
- extern const bfd_target powerpc_xcoff_vec;
-+extern const bfd_target riscv_elf32_vec;
-+extern const bfd_target riscv_elf64_vec;
- extern const bfd_target rl78_elf32_vec;
- extern const bfd_target rs6000_xcoff64_vec;
- extern const bfd_target rs6000_xcoff64_aix_vec;
-diff -urN original-binutils/binutils/readelf.c binutils/binutils/readelf.c
---- original-binutils/binutils/readelf.c	2014-12-23 09:47:10.000000000 +0100
-+++ binutils-2.25/binutils/readelf.c	2015-03-07 09:55:02.375135671 +0100
-@@ -125,6 +125,7 @@
- #include "elf/metag.h"
- #include "elf/microblaze.h"
- #include "elf/mips.h"
-+#include "elf/riscv.h"
- #include "elf/mmix.h"
- #include "elf/mn10200.h"
- #include "elf/mn10300.h"
-@@ -720,6 +721,7 @@
-     case EM_OR1K:
-     case EM_PPC64:
-     case EM_PPC:
-+    case EM_RISCV:
-     case EM_RL78:
-     case EM_RX:
-     case EM_S390:
-@@ -1252,6 +1254,10 @@
- 	  rtype = elf_mips_reloc_type (type);
- 	  break;
- 
-+	case EM_RISCV:
-+	  rtype = elf_riscv_reloc_type (type);
-+	  break;
-+
- 	case EM_ALPHA:
- 	  rtype = elf_alpha_reloc_type (type);
- 	  break;
-@@ -2164,6 +2170,7 @@
-     case EM_CR16:
-     case EM_MICROBLAZE:
-     case EM_MICROBLAZE_OLD:	return "Xilinx MicroBlaze";
-+    case EM_RISCV:		return "RISC-V";
-     case EM_RL78:		return "Renesas RL78";
-     case EM_RX:			return "Renesas RX";
-     case EM_METAG:		return "Imagination Technologies Meta processor architecture";
-@@ -2951,6 +2958,14 @@
- 	  decode_NDS32_machine_flags (e_flags, buf, sizeof buf);
- 	  break;
- 
-+	case EM_RISCV:
-+          {
-+            unsigned int riscv_extension = EF_GET_RISCV_EXT(e_flags);
-+            strcat (buf, ", ");
-+            strcat (buf, riscv_elf_flag_to_name (riscv_extension));
-+          }
-+	  break;
-+
- 	case EM_SH:
- 	  switch ((e_flags & EF_SH_MACH_MASK))
- 	    {
-@@ -10789,6 +10804,8 @@
-       return reloc_type == 1; /* R_PPC64_ADDR32.  */
-     case EM_PPC:
-       return reloc_type == 1; /* R_PPC_ADDR32.  */
-+    case EM_RISCV:
-+      return reloc_type == 1; /* R_RISCV_32.  */
-     case EM_RL78:
-       return reloc_type == 1; /* R_RL78_DIR32.  */
-     case EM_RX:
-@@ -10924,6 +10941,8 @@
-       return reloc_type == 80; /* R_PARISC_DIR64.  */
-     case EM_PPC64:
-       return reloc_type == 38; /* R_PPC64_ADDR64.  */
-+    case EM_RISCV:
-+      return reloc_type == 2; /* R_RISCV_64.  */
-     case EM_SPARC32PLUS:
-     case EM_SPARCV9:
-     case EM_SPARC:
-@@ -11072,6 +11091,7 @@
-     case EM_ADAPTEVA_EPIPHANY:
-     case EM_PPC:     /* R_PPC_NONE.  */
-     case EM_PPC64:   /* R_PPC64_NONE.  */
-+    case EM_RISCV:   /* R_RISCV_NONE.  */
-     case EM_ARM:     /* R_ARM_NONE.  */
-     case EM_IA_64:   /* R_IA64_NONE.  */
-     case EM_SH:      /* R_SH_NONE.  */
-diff -urN original-binutils/config.sub binutils/config.sub
---- original-binutils/config.sub	2014-10-14 09:32:02.000000000 +0200
-+++ binutils-2.25/config.sub	2015-03-07 09:55:02.375135671 +0100
-@@ -335,6 +335,9 @@
- 	ms1)
- 		basic_machine=mt-unknown
- 		;;
-+	riscv)
-+		basic_machine=riscv-ucb
-+		;;
- 
- 	strongarm | thumb | xscale)
- 		basic_machine=arm-unknown
-diff -urN original-binutils/gas/config/tc-riscv.c binutils/gas/config/tc-riscv.c
---- original-binutils/gas/config/tc-riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/gas/config/tc-riscv.c	2015-03-07 09:51:45.659139025 +0100
-@@ -0,0 +1,2225 @@
+diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
+--- empty/gas/config/tc-riscv.c	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/gas/config/tc-riscv.c	2015-07-18 00:02:36.222287541 +0200
+@@ -0,0 +1,2484 @@
 +/* tc-riscv.c -- RISC-V assembler
 +   Copyright 2011-2014 Free Software Foundation, Inc.
 +
@@ -4160,9 +3950,31 @@
 +  fixS *fixp;
 +};
 +
-+bfd_boolean rv64 = TRUE; /* RV64 (true) or RV32 (false) */
-+#define LOAD_ADDRESS_INSN (rv64 ? "ld" : "lw")
-+#define ADD32_INSN (rv64 ? "addiw" : "addi")
++/* The default architecture.  */
++#ifndef DEFAULT_ARCH
++#define DEFAULT_ARCH "riscv64"
++#endif
++static const char default_arch[] = DEFAULT_ARCH;
++
++unsigned xlen = 0; /* width of an x-register */
++#define LOAD_ADDRESS_INSN (xlen == 64 ? "ld" : "lw")
++#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
++
++unsigned elf_flags = 0;
++
++/* This is the set of options which the .option pseudo-op may modify.  */
++
++struct riscv_set_options
++{
++  int pic; /* Generate position-independent code.  */
++  int rvc; /* Generate RVC code.  */
++};
++
++static struct riscv_set_options riscv_opts =
++{
++  0,	/* pic */
++  0,	/* rvc */
++};
 +
 +struct riscv_subset
 +{
@@ -4183,7 +3995,7 @@
 +
 +  if ((rv64_insn = !strncmp(feature, "64", 2)) || !strncmp(feature, "32", 2))
 +    {
-+      if (rv64 != rv64_insn)
++      if ((xlen == 64) != rv64_insn)
 +        return 0;
 +      feature += 2;
 +    }
@@ -4198,7 +4010,7 @@
 +}
 +
 +static void
-+riscv_add_subset(const char* subset)
++riscv_add_subset (const char* subset)
 +{
 +  struct riscv_subset* s = xmalloc(sizeof(struct riscv_subset));
 +  s->name = xstrdup(subset);
@@ -4209,7 +4021,7 @@
 +}
 +
 +static void
-+riscv_set_arch(const char* arg)
++riscv_set_arch (const char* arg)
 +{
 +  /* Formally, ISA subset names begin with RV, RV32, or RV64, but we allow the
 +     prefix to be omitted.  We also allow all-lowercase names if version
@@ -4217,8 +4029,10 @@
 +     is supported in this case).
 +     
 +     FIXME: Version numbers are not supported yet. */
-+  const char* subsets = "IMAFD";
++  const char* subsets = "IMAFDC";
++  const char* extension = NULL;
 +  const char* p;
++  int rvc = 0;
 +  
 +  for (p = arg; *p; p++)
 +    if (!ISLOWER(*p) || strchr(subsets, TOUPPER(*p)) == NULL)
@@ -4228,21 +4042,21 @@
 +    {
 +      /* Legal all-lowercase name. */
 +      for (p = arg; *p; p++)
-+        {
-+          char subset[2] = {TOUPPER(*p), 0};
-+          riscv_add_subset(subset);
-+        }
++	{
++	  char subset[2] = {TOUPPER(*p), 0};
++	  riscv_add_subset(subset);
++	}
 +      return;
 +    }
 +
 +  if (strncmp(arg, "RV32", 4) == 0)
 +    {
-+      rv64 = FALSE;
++      xlen = 32;
 +      arg += 4;
 +    }
 +  else if (strncmp(arg, "RV64", 4) == 0)
 +    {
-+      rv64 = TRUE;
++      xlen = 64;
 +      arg += 4;
 +    }
 +  else if (strncmp(arg, "RV", 2) == 0)
@@ -4251,49 +4065,47 @@
 +  if (*arg && *arg != 'I')
 +    as_fatal("`I' must be the first ISA subset name specified (got %c)", *arg);
 +
-+  for (p = arg; *p; p++)
++  for (p = arg; *p; )
 +    {
 +      if (*p == 'X')
-+        {
-+          const char* q = p+1;
-+          while (ISLOWER(*q))
-+            q++;
++	{
++	  char *subset = xstrdup(p), *q = subset;
 +
-+          char subset[q-p+1];
-+          memcpy(subset, p, q-p);
-+          subset[q-p] = 0;
++	  do
++	    q++;
++	  while (ISLOWER(*q));
++	  *q = 0;
 +
-+          riscv_add_subset(subset);
-+          p = q-1;
-+        }
++	  if (extension)
++	    as_bad ("only one eXtension is supported (found %s and %s)",
++		    extension, subset);
++	  extension = subset;
++	  EF_SET_RISCV_EXT (elf_flags, riscv_elf_name_to_flag (subset));
++
++	  riscv_add_subset (subset);
++	  p += strlen (subset);
++	  free (subset);
++	}
 +      else if (strchr(subsets, *p) != NULL)
-+        {
-+          char subset[2] = {*p, 0};
-+          riscv_add_subset(subset);
-+        }
++	{
++	  char subset[2] = {*p, 0};
++	  riscv_add_subset (subset);
++	  if (*p == 'C')
++	    rvc = 1;
++	  p++;
++	}
 +      else
-+        as_fatal("unsupported ISA subset %c", *p);
++	as_fatal("unsupported ISA subset %c", *p);
 +    }
++
++  if (rvc)
++    /* Override -m[no-]rvc setting if C was explicitly listed.  */
++    riscv_opts.rvc = 1;
++  else
++    /* Add RVC anyway.  -m[no-]rvc toggles its availability.  */
++    riscv_add_subset ("C");
 +}
 +
-+/* This is the set of options which may be modified by the .set
-+   pseudo-op.  We use a struct so that .set push and .set pop are more
-+   reliable.  */
-+
-+struct riscv_set_options
-+{
-+  /* Generate position-independent code.  */
-+  int pic;
-+  /* Generate RVC code.  */
-+  int rvc;
-+};
-+
-+static struct riscv_set_options riscv_opts =
-+{
-+  0,	/* pic */
-+  0,	/* rvc */
-+};
-+
 +/* handle of the OPCODE hash table */
 +static struct hash_control *op_hash = NULL;
 +
@@ -4321,21 +4133,16 @@
 +/* or    0d1.2345e12 */
 +const char FLT_CHARS[] = "rRsSfFdDxXpP";
 +
-+/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
-+   changed in read.c .  Ideally it shouldn't have to know about it at all,
-+   but nothing is ideal around here.
-+ */
-+
-+static char *insn_error;
-+
-+#define RELAX_BRANCH_ENCODE(uncond, toofar)		\
++#define RELAX_BRANCH_ENCODE(uncond, rvc, length)	\
 +  ((relax_substateT) 					\
 +   (0xc0000000						\
-+    | ((toofar) ? 1 : 0)				\
-+    | ((uncond) ? 2 : 0)))
++    | ((uncond) ? 1 : 0)				\
++    | ((rvc) ? 2 : 0)					\
++    | ((length) << 2)))
 +#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
-+#define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
-+#define RELAX_BRANCH_UNCOND(i) (((i) & 2) != 0)
++#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
++#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
++#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
 +
 +/* Is the given value a sign-extended 32-bit value?  */
 +#define IS_SEXT_32BIT_NUM(x)						\
@@ -4386,23 +4193,12 @@
 +
 +static char *expr_end;
 +
-+/* Expressions which appear in instructions.  These are set by
-+   riscv_ip.  */
-+
-+static expressionS imm_expr;
-+static expressionS offset_expr;
-+
-+/* Relocs associated with imm_expr and offset_expr.  */
-+
-+static bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
-+static bfd_reloc_code_real_type offset_reloc = BFD_RELOC_UNUSED;
-+
 +/* The default target format to use.  */
 +
 +const char *
 +riscv_target_format (void)
 +{
-+  return rv64 ? "elf64-littleriscv" : "elf32-littleriscv";
++  return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
 +}
 +
 +/* Return the length of instruction INSN.  */
@@ -4469,37 +4265,42 @@
 +      subtype, symbol, offset, NULL);
 +}
 +
-+/* Compute the length of a branch sequence, and adjust the
-+   RELAX_BRANCH_TOOFAR bit accordingly.  If FRAGP is NULL, the
-+   worst-case length is computed. */
++/* Compute the length of a branch sequence, and adjust the stored length
++   accordingly.  If FRAGP is NULL, the worst-case length is returned. */
++
 +static int
 +relaxed_branch_length (fragS *fragp, asection *sec, int update)
 +{
-+  bfd_boolean toofar = TRUE;
++  int jump, rvc, length = 8;
 +
-+  if (fragp)
++  if (!fragp)
++    return length;
++
++  jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
++  rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
++  length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
++
++  /* Assume jumps are in range; the linker will catch any that aren't.  */
++  length = jump ? 4 : 8;
++
++  if (fragp->fr_symbol != NULL
++      && S_IS_DEFINED (fragp->fr_symbol)
++      && sec == S_GET_SEGMENT (fragp->fr_symbol))
 +    {
-+      bfd_boolean uncond = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
++      offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
++      bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
++      val -= fragp->fr_address + fragp->fr_fix;
 +
-+      if (S_IS_DEFINED (fragp->fr_symbol)
-+	  && sec == S_GET_SEGMENT (fragp->fr_symbol))
-+	{
-+	  offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
-+	  bfd_vma range;
-+	  val -= fragp->fr_address + fragp->fr_fix;
-+
-+	  if (uncond)
-+	    range = RISCV_JUMP_REACH;
-+	  else
-+	    range = RISCV_BRANCH_REACH;
-+	  toofar = (bfd_vma)(val + range/2) >= range;
-+	}
-+
-+      if (update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
-+	fragp->fr_subtype = RELAX_BRANCH_ENCODE (uncond, toofar);
++      if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
++	length = 2;
++      else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
++	length = 4;
 +    }
 +
-+  return toofar ? 8 : 4;
++  if (update)
++    fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
++
++  return length;
 +}
 +
 +struct regname {
@@ -4601,18 +4402,15 @@
 +{
 +  const char *p = opc->args;
 +  char c;
-+  insn_t required_bits, used_bits = opc->mask;
++  insn_t used_bits = opc->mask;
++  insn_t required_bits = (uint64_t)-1 >> (64 - 8 * riscv_insn_length (opc->match));
 +
-+  if ((used_bits & opc->match) != opc->match)
++  if ((used_bits & opc->match) != (opc->match & required_bits))
 +    {
 +      as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
 +	      opc->name, opc->args);
 +      return 0;
 +    }
-+  required_bits = ((insn_t)1 << (8 * riscv_insn_length (opc->match))) - 1;
-+  /* Work around for undefined behavior of uint64_t << 64 */
-+  if(riscv_insn_length (opc->match) == 8)
-+    required_bits = 0xffffffffffffffff;
 +
 +#define USE_BITS(mask,shift)	(used_bits |= ((insn_t)(mask) << (shift)))
 +  while (*p)
@@ -4650,6 +4448,41 @@
 +          return 0;
 +        }
 +      break;
++      case 'C': /* RVC */
++	switch (c = *p++)
++	  {
++	  case 'd': USE_BITS (OP_MASK_CRDS, OP_SH_CRDS); break;
++	  case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
++	  case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
++	  case 'w': break; /* RS1S, constrained to equal RD */
++	  case 'x': break; /* RS1S, constrained to equal RD */
++	  case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
++	  case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
++	  case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
++	  case 'c': break; /* RS1, constrained to equal sp */
++	  case 'U': break; /* RS2, constrained to equal RD */
++	  case '<': used_bits |= ENCODE_RVC_IMM(-1U); break;
++	  case '>': used_bits |= ENCODE_RVC_IMM(-1U); break;
++	  case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
++	  case 'j': used_bits |= ENCODE_RVC_IMM(-1U); break;
++	  case 'k': used_bits |= ENCODE_RVC_LW_IMM(-1U); break;
++	  case 'l': used_bits |= ENCODE_RVC_LD_IMM(-1U); break;
++	  case 'm': used_bits |= ENCODE_RVC_LWSP_IMM(-1U); break;
++	  case 'n': used_bits |= ENCODE_RVC_LDSP_IMM(-1U); break;
++	  case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM(-1U); break;
++	  case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM(-1U); break;
++	  case 'M': used_bits |= ENCODE_RVC_SWSP_IMM(-1U); break;
++	  case 'N': used_bits |= ENCODE_RVC_SDSP_IMM(-1U); break;
++	  case 'u': used_bits |= ENCODE_RVC_IMM(-1U); break;
++	  case 'v': used_bits |= ENCODE_RVC_IMM(-1U); break;
++	  case 'a': used_bits |= ENCODE_RVC_J_IMM(-1U); break;
++	  case 'p': used_bits |= ENCODE_RVC_B_IMM(-1U); break;
++	  default:
++	    as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
++		    c, opc->name, opc->args);
++	    return 0;
++	  }
++	break;
 +      case ',': break;
 +      case '(': break;
 +      case ')': break;
@@ -4718,8 +4551,7 @@
 +    {
 +      const char *name = riscv_opcodes[i].name;
 +
-+      if (riscv_subset_supports(riscv_opcodes[i].subset))
-+        retval = hash_insert (op_hash, name, (void *) &riscv_opcodes[i]);
++      retval = hash_insert (op_hash, name, (void *) &riscv_opcodes[i]);
 +
 +      if (retval != NULL)
 +	{
@@ -4768,77 +4600,72 @@
 +  dwarf2_emit_insn (0);
 +#endif
 +
-+  gas_assert(reloc_type <= BFD_RELOC_UNUSED);
-+
-+  if (address_expr != NULL)
++  if (reloc_type != BFD_RELOC_UNUSED)
 +    {
-+      if (address_expr->X_op == O_constant)
++      reloc_howto_type *howto;
++
++      gas_assert(address_expr);
++      if (reloc_type == BFD_RELOC_12_PCREL
++	  || reloc_type == BFD_RELOC_RISCV_JMP)
++	{
++	  int j = reloc_type == BFD_RELOC_RISCV_JMP;
++	  int best_case = riscv_insn_length (ip->insn_opcode);
++	  int worst_case = relaxed_branch_length (NULL, NULL, 0);
++	  add_relaxed_insn (ip, worst_case, best_case,
++			    RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
++			    address_expr->X_add_symbol,
++			    address_expr->X_add_number);
++	  return;
++	}
++      else if (address_expr->X_op == O_constant)
 +	{
 +	  switch (reloc_type)
 +	    {
 +	    case BFD_RELOC_32:
 +	      ip->insn_opcode |= address_expr->X_add_number;
-+	      break;
++	      goto append;
 +
 +	    case BFD_RELOC_RISCV_HI20:
 +	      ip->insn_opcode |= ENCODE_UTYPE_IMM (
 +		RISCV_CONST_HIGH_PART (address_expr->X_add_number));
-+	      break;
++	      goto append;
 +
 +	    case BFD_RELOC_RISCV_LO12_S:
 +	      ip->insn_opcode |= ENCODE_STYPE_IMM (address_expr->X_add_number);
-+	      break;
++	      goto append;
 +
-+	    case BFD_RELOC_UNUSED:
 +	    case BFD_RELOC_RISCV_LO12_I:
 +	      ip->insn_opcode |= ENCODE_ITYPE_IMM (address_expr->X_add_number);
-+	      break;
++	      goto append;
 +
 +	    default:
-+	      internalError ();
++	      break;
 +	    }
-+	    reloc_type = BFD_RELOC_UNUSED;
 +	}
-+      else if (reloc_type == BFD_RELOC_12_PCREL)
-+	{
-+	  add_relaxed_insn (ip, relaxed_branch_length (NULL, NULL, 0), 4,
-+			    RELAX_BRANCH_ENCODE (0, 0),
-+			    address_expr->X_add_symbol,
-+			    address_expr->X_add_number);
-+	  return;
-+	}
-+      else if (reloc_type < BFD_RELOC_UNUSED)
-+	{
-+	  reloc_howto_type *howto;
 +
-+	  howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
-+	  if (howto == NULL)
-+	    as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
-+	 
-+	  ip->fixp = fix_new_exp (ip->frag, ip->where,
-+				  bfd_get_reloc_size (howto),
-+				  address_expr,
-+				  reloc_type == BFD_RELOC_12_PCREL ||
-+				  reloc_type == BFD_RELOC_RISCV_CALL ||
-+				  reloc_type == BFD_RELOC_RISCV_JMP,
-+				  reloc_type);
++	howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
++	if (howto == NULL)
++	  as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
 +
-+	  /* These relocations can have an addend that won't fit in
-+	     4 octets for 64bit assembly.  */
-+	  if (rv64
-+	      && ! howto->partial_inplace
-+	      && (reloc_type == BFD_RELOC_32
-+		  || reloc_type == BFD_RELOC_64
-+		  || reloc_type == BFD_RELOC_CTOR
-+		  || reloc_type == BFD_RELOC_RISCV_HI20
-+		  || reloc_type == BFD_RELOC_RISCV_LO12_I
-+		  || reloc_type == BFD_RELOC_RISCV_LO12_S))
-+	    ip->fixp->fx_no_overflow = 1;
-+	}
++	ip->fixp = fix_new_exp (ip->frag, ip->where,
++				bfd_get_reloc_size (howto),
++				address_expr, FALSE, reloc_type);
++
++	/* These relocations can have an addend that won't fit in
++	   4 octets for 64bit assembly.  */
++	if (xlen == 64
++	    && ! howto->partial_inplace
++	    && (reloc_type == BFD_RELOC_32
++		|| reloc_type == BFD_RELOC_64
++		|| reloc_type == BFD_RELOC_CTOR
++		|| reloc_type == BFD_RELOC_RISCV_HI20
++		|| reloc_type == BFD_RELOC_RISCV_LO12_I
++		|| reloc_type == BFD_RELOC_RISCV_LO12_S))
++	  ip->fixp->fx_no_overflow = 1;
 +    }
 +
++append:
 +  add_fixed_insn (ip);
-+
 +  install_insn (ip);
 +}
 +
@@ -4860,6 +4687,10 @@
 +  r = BFD_RELOC_UNUSED;
 +  mo = (struct riscv_opcode *) hash_find (op_hash, name);
 +  gas_assert (mo);
++
++  /* Find a non-RVC variant of the instruction.  */
++  while (riscv_insn_length (mo->match) < 4)
++    mo++;
 +  gas_assert (strcmp (name, mo->name) == 0);
 +
 +  create_insn (&insn, mo);
@@ -4912,7 +4743,7 @@
 +static void
 +normalize_constant_expr (expressionS *ex)
 +{
-+  if (rv64)
++  if (xlen > 32)
 +    return;
 +  if ((ex->X_op == O_constant || ex->X_op == O_symbol)
 +      && IS_ZEXT_32BIT_NUM (ex->X_add_number))
@@ -4993,7 +4824,7 @@
 +
 +  gas_assert (ep->X_op == O_constant);
 +
-+  if (rv64 && !IS_SEXT_32BIT_NUM(ep->X_add_number))
++  if (xlen > 32 && !IS_SEXT_32BIT_NUM(ep->X_add_number))
 +    {
 +      /* Reduce to a signed 32-bit constant using SLLI and ADDI, which
 +	 is not optimal but also not so bad.  */
@@ -5025,7 +4856,8 @@
 +
 +/* Expand RISC-V assembly macros into one or more instructions. */
 +static void
-+macro (struct riscv_cl_insn *ip)
++macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
++       bfd_reloc_code_real_type *imm_reloc)
 +{
 +  int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
 +  int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
@@ -5035,117 +4867,117 @@
 +  switch (mask)
 +    {
 +    case M_LI:
-+      load_const (rd, &imm_expr);
++      load_const (rd, imm_expr);
 +      break;
 +
 +    case M_LA:
 +    case M_LLA:
 +      /* Load the address of a symbol into a register. */
-+      if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
++      if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
 +	as_bad(_("offset too large"));
 +
-+      if (offset_expr.X_op == O_constant)
-+	load_const (rd, &offset_expr);
++      if (imm_expr->X_op == O_constant)
++	load_const (rd, imm_expr);
 +      else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
-+	pcrel_load (rd, rd, &offset_expr, LOAD_ADDRESS_INSN,
++	pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
 +		    BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      else /* Local PIC symbol, or any non-PIC symbol */
-+	pcrel_load (rd, rd, &offset_expr, "addi",
++	pcrel_load (rd, rd, imm_expr, "addi",
 +		    BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_LA_TLS_GD: 
-+      pcrel_load (rd, rd, &offset_expr, "addi",
++      pcrel_load (rd, rd, imm_expr, "addi",
 +		  BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_LA_TLS_IE: 
-+      pcrel_load (rd, rd, &offset_expr, LOAD_ADDRESS_INSN,
++      pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
 +		  BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_LB:
-+      pcrel_load (rd, rd, &offset_expr, "lb",
++      pcrel_load (rd, rd, imm_expr, "lb",
 +		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_LBU:
-+      pcrel_load (rd, rd, &offset_expr, "lbu",
++      pcrel_load (rd, rd, imm_expr, "lbu",
 +		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_LH:
-+      pcrel_load (rd, rd, &offset_expr, "lh",
++      pcrel_load (rd, rd, imm_expr, "lh",
 +		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_LHU:
-+      pcrel_load (rd, rd, &offset_expr, "lhu",
++      pcrel_load (rd, rd, imm_expr, "lhu",
 +		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_LW:
-+      pcrel_load (rd, rd, &offset_expr, "lw",
++      pcrel_load (rd, rd, imm_expr, "lw",
 +		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_LWU:
-+      pcrel_load (rd, rd, &offset_expr, "lwu",
++      pcrel_load (rd, rd, imm_expr, "lwu",
 +		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_LD:
-+      pcrel_load (rd, rd, &offset_expr, "ld",
++      pcrel_load (rd, rd, imm_expr, "ld",
 +		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_FLW:
-+      pcrel_load (rd, rs1, &offset_expr, "flw",
++      pcrel_load (rd, rs1, imm_expr, "flw",
 +		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_FLD:
-+      pcrel_load (rd, rs1, &offset_expr, "fld",
++      pcrel_load (rd, rs1, imm_expr, "fld",
 +		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
 +    case M_SB:
-+      pcrel_store (rs2, rs1, &offset_expr, "sb",
++      pcrel_store (rs2, rs1, imm_expr, "sb",
 +		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
 +      break;
 +
 +    case M_SH:
-+      pcrel_store (rs2, rs1, &offset_expr, "sh",
++      pcrel_store (rs2, rs1, imm_expr, "sh",
 +		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
 +      break;
 +
 +    case M_SW:
-+      pcrel_store (rs2, rs1, &offset_expr, "sw",
++      pcrel_store (rs2, rs1, imm_expr, "sw",
 +		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
 +      break;
 +
 +    case M_SD:
-+      pcrel_store (rs2, rs1, &offset_expr, "sd",
++      pcrel_store (rs2, rs1, imm_expr, "sd",
 +		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
 +      break;
 +
 +    case M_FSW:
-+      pcrel_store (rs2, rs1, &offset_expr, "fsw",
++      pcrel_store (rs2, rs1, imm_expr, "fsw",
 +		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
 +      break;
 +
 +    case M_FSD:
-+      pcrel_store (rs2, rs1, &offset_expr, "fsd",
++      pcrel_store (rs2, rs1, imm_expr, "fsd",
 +		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
 +      break;
 +
 +    case M_VF:
-+      pcrel_access (0, rs1, &offset_expr, "vf", "s,s,q",
++      pcrel_access (0, rs1, imm_expr, "vf", "s,s,q",
 +		    BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
 +      break;
 +
 +    case M_CALL:
-+      riscv_call (rd, rs1, &offset_expr, offset_reloc);
++      riscv_call (rd, rs1, imm_expr, *imm_reloc);
 +      break;
 +
 +    default:
@@ -5241,9 +5073,17 @@
 +		       char *str, const struct percent_op_match *percent_op)
 +{
 +  size_t reloc_index;
-+  int crux_depth, str_depth;
++  unsigned crux_depth, str_depth, regno;
 +  char *crux;
 +
++  /* First, check for integer registers.  */
++  if (reg_lookup (&str, RCLASS_GPR, &regno))
++    {
++      ep->X_op = O_register;
++      ep->X_add_number = regno;
++      return 0;
++    }
++
 +  /* Search for the start of the main expression.
 +     End the loop with CRUX pointing to the start
 +     of the main expression and with CRUX_DEPTH containing the number
@@ -5283,118 +5123,92 @@
 +}
 +
 +/* This routine assembles an instruction into its binary format.  As a
-+   side effect, it sets one of the global variables imm_reloc or
-+   offset_reloc to the type of relocation to do if one of the operands
-+   is an address expression.  */
++   side effect, it sets the global variable imm_reloc to the type of
++   relocation to do if one of the operands is an address expression.  */
 +
-+static void
-+riscv_ip (char *str, struct riscv_cl_insn *ip)
++static const char *
++riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
++	  bfd_reloc_code_real_type *imm_reloc)
 +{
 +  char *s;
 +  const char *args;
 +  char c = 0;
-+  struct riscv_opcode *insn;
++  struct riscv_opcode *insn, *end = &riscv_opcodes[NUMOPCODES];
 +  char *argsStart;
 +  unsigned int regno;
 +  char save_c = 0;
 +  int argnum;
 +  const struct percent_op_match *p;
++  const char *error = "unrecognized opcode";
 +
-+  insn_error = NULL;
-+
-+  /* If the instruction contains a '.', we first try to match an instruction
-+     including the '.'.  Then we try again without the '.'.  */
-+  insn = NULL;
-+  for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
-+    continue;
-+
-+  /* If we stopped on whitespace, then replace the whitespace with null for
-+     the call to hash_find.  Save the character we replaced just in case we
-+     have to re-parse the instruction.  */
-+  if (ISSPACE (*s))
-+    {
-+      save_c = *s;
-+      *s++ = '\0';
-+    }
++  /* Parse the name of the instruction.  Terminate the string if whitespace
++     is found so that hash_find only sees the name part of the string.  */
++  for (s = str; *s != '\0'; ++s)
++    if (ISSPACE (*s))
++      {
++	save_c = *s;
++	*s++ = '\0';
++	break;
++      }
 +
 +  insn = (struct riscv_opcode *) hash_find (op_hash, str);
 +
-+  /* If we didn't find the instruction in the opcode table, try again, but
-+     this time with just the instruction up to, but not including the
-+     first '.'.  */
-+  if (insn == NULL)
++  argsStart = s;
++  for ( ; insn && insn < end && strcmp (insn->name, str) == 0; insn++)
 +    {
-+      /* Restore the character we overwrite above (if any).  */
-+      if (save_c)
-+	*(--s) = save_c;
-+
-+      /* Scan up to the first '.' or whitespace.  */
-+      for (s = str;
-+	   *s != '\0' && *s != '.' && !ISSPACE (*s);
-+	   ++s)
++      if (!riscv_subset_supports (insn->subset))
 +	continue;
 +
-+      /* If we did not find a '.', then we can quit now.  */
-+      if (*s != '.')
-+	{
-+	  insn_error = "unrecognized opcode";
-+	  return;
-+	}
-+
-+      /* Lookup the instruction in the hash table.  */
-+      *s++ = '\0';
-+      if ((insn = (struct riscv_opcode *) hash_find (op_hash, str)) == NULL)
-+	{
-+	  insn_error = "unrecognized opcode";
-+	  return;
-+	}
-+    }
-+
-+  argsStart = s;
-+  for (;;)
-+    {
-+      bfd_boolean ok = TRUE;
-+      gas_assert (strcmp (insn->name, str) == 0);
-+
 +      create_insn (ip, insn);
-+      insn_error = NULL;
 +      argnum = 1;
++
++      imm_expr->X_op = O_absent;
++      *imm_reloc = BFD_RELOC_UNUSED;
++      p = percent_op_itype;
++
 +      for (args = insn->args;; ++args)
 +	{
 +	  s += strspn (s, " \t");
 +	  switch (*args)
 +	    {
 +	    case '\0':		/* end of args */
++	      if (insn->pinfo != INSN_MACRO
++		  && riscv_insn_length (insn->match) == 2
++		  && !riscv_opts.rvc)
++		break;
 +	      if (*s == '\0')
-+		return;
++		{
++		  error = NULL;
++		  goto out;
++		}
 +	      break;
 +            /* Xcustom */
 +            case '^':
 +            {
 +              unsigned long max = OP_MASK_RD;
-+              my_getExpression (&imm_expr, s);
-+              check_absolute_expr (ip, &imm_expr);
++              my_getExpression (imm_expr, s);
++              check_absolute_expr (ip, imm_expr);
 +              switch (*++args)
 +                {
 +                case 'j':
 +                  max = OP_MASK_CUSTOM_IMM;
-+                  INSERT_OPERAND (CUSTOM_IMM, *ip, imm_expr.X_add_number);
++                  INSERT_OPERAND (CUSTOM_IMM, *ip, imm_expr->X_add_number);
 +                  break;
 +                case 'd':
-+                  INSERT_OPERAND (RD, *ip, imm_expr.X_add_number);
++                  INSERT_OPERAND (RD, *ip, imm_expr->X_add_number);
 +                  break;
 +                case 's':
-+                  INSERT_OPERAND (RS1, *ip, imm_expr.X_add_number);
++                  INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
 +                  break;
 +                case 't':
-+                  INSERT_OPERAND (RS2, *ip, imm_expr.X_add_number);
++                  INSERT_OPERAND (RS2, *ip, imm_expr->X_add_number);
 +                  break;
 +                }
-+              imm_expr.X_op = O_absent;
++              imm_expr->X_op = O_absent;
 +              s = expr_end;
-+              if ((unsigned long) imm_expr.X_add_number > max)
++              if ((unsigned long) imm_expr->X_add_number > max)
 +                  as_warn ("Bad custom immediate (%lu), must be at most %lu",
-+                           (unsigned long)imm_expr.X_add_number, max);
++                           (unsigned long)imm_expr->X_add_number, max);
 +              continue;
 +            }
 +
@@ -5403,86 +5217,258 @@
 +              switch ( *++args )
 +                {
 +                case 'g':
-+                  my_getExpression( &imm_expr, s );
++                  my_getExpression( imm_expr, s );
 +                  /* check_absolute_expr( ip, &imm_expr ); */
-+                  if ((unsigned long) imm_expr.X_add_number > 32 )
++                  if ((unsigned long) imm_expr->X_add_number > 32 )
 +                    as_warn( _( "Improper ngpr amount (%lu)" ),
-+                             (unsigned long) imm_expr.X_add_number );
-+                  INSERT_OPERAND( IMMNGPR, *ip, imm_expr.X_add_number );
-+                  imm_expr.X_op = O_absent;
++                             (unsigned long) imm_expr->X_add_number );
++                  INSERT_OPERAND( IMMNGPR, *ip, imm_expr->X_add_number );
++                  imm_expr->X_op = O_absent;
 +                  s = expr_end;
 +                  continue;
 +                case 'f':
-+                  my_getExpression( &imm_expr, s );
++                  my_getExpression( imm_expr, s );
 +                  /* check_absolute_expr( ip, &imm_expr ); */
-+                  if ((unsigned long) imm_expr.X_add_number > 32 )
++                  if ((unsigned long) imm_expr->X_add_number > 32 )
 +                    as_warn( _( "Improper nfpr amount (%lu)" ),
-+                             (unsigned long) imm_expr.X_add_number );
-+                  INSERT_OPERAND( IMMNFPR, *ip, imm_expr.X_add_number );
-+                  imm_expr.X_op = O_absent;
++                             (unsigned long) imm_expr->X_add_number );
++                  INSERT_OPERAND( IMMNFPR, *ip, imm_expr->X_add_number );
++                  imm_expr->X_op = O_absent;
 +                  s = expr_end;
 +                  continue;
 +                case 'n':
-+                  my_getExpression( &imm_expr, s );
++                  my_getExpression( imm_expr, s );
 +                  /* check_absolute_expr( ip, &imm_expr ); */
-+                  if ((unsigned long) imm_expr.X_add_number > 8 )
++                  if ((unsigned long) imm_expr->X_add_number > 8 )
 +                    as_warn( _( "Improper nelm amount (%lu)" ),
-+                             (unsigned long) imm_expr.X_add_number );
-+                  INSERT_OPERAND( IMMSEGNELM, *ip, imm_expr.X_add_number - 1 );
-+                  imm_expr.X_op = O_absent;
++                             (unsigned long) imm_expr->X_add_number );
++                  INSERT_OPERAND( IMMSEGNELM, *ip, imm_expr->X_add_number - 1 );
++                  imm_expr->X_op = O_absent;
 +                  s = expr_end;
 +                  continue;
 +                case 'd':
-+                  ok = reg_lookup( &s, RCLASS_VEC_GPR, &regno );
-+                  if ( !ok )
++                  if (!reg_lookup( &s, RCLASS_VEC_GPR, &regno ))
 +                    as_bad( _( "Invalid vector register" ) );
 +                  INSERT_OPERAND( VRD, *ip, regno );
 +                  continue;
 +                case 's':
-+                  ok = reg_lookup( &s, RCLASS_VEC_GPR, &regno );
-+                  if ( !ok )
++                  if (!reg_lookup( &s, RCLASS_VEC_GPR, &regno ))
 +                    as_bad( _( "Invalid vector register" ) );
 +                  INSERT_OPERAND( VRS, *ip, regno );
 +                  continue;
 +                case 't':
-+                  ok = reg_lookup( &s, RCLASS_VEC_GPR, &regno );
-+                  if ( !ok )
++                  if (!reg_lookup( &s, RCLASS_VEC_GPR, &regno ))
 +                    as_bad( _( "Invalid vector register" ) );
 +                  INSERT_OPERAND( VRT, *ip, regno );
 +                  continue;
 +                case 'r':
-+                  ok = reg_lookup( &s, RCLASS_VEC_GPR, &regno );
-+                  if ( !ok )
++                  if (!reg_lookup( &s, RCLASS_VEC_GPR, &regno ))
 +                    as_bad( _( "Invalid vector register" ) );
 +                  INSERT_OPERAND( VRR, *ip, regno );
 +                  continue;
 +                case 'D':
-+                  ok = reg_lookup( &s, RCLASS_VEC_FPR, &regno );
-+                  if ( !ok )
++                  if (!reg_lookup( &s, RCLASS_VEC_FPR, &regno ))
 +                    as_bad( _( "Invalid vector register" ) );
 +                  INSERT_OPERAND( VFD, *ip, regno );
 +                  continue;
 +                case 'S':
-+                  ok = reg_lookup( &s, RCLASS_VEC_FPR, &regno );
-+                  if ( !ok )
++                  if (!reg_lookup( &s, RCLASS_VEC_FPR, &regno ))
 +                    as_bad( _( "Invalid vector register" ) );
 +                  INSERT_OPERAND( VFS, *ip, regno );
 +                  continue;
 +                case 'T':
-+                  ok = reg_lookup( &s, RCLASS_VEC_FPR, &regno );
-+                  if ( !ok )
++                  if (!reg_lookup( &s, RCLASS_VEC_FPR, &regno ))
 +                    as_bad( _( "Invalid vector register" ) );
 +                  INSERT_OPERAND( VFT, *ip, regno );
 +                  continue;
 +                case 'R':
-+                  ok = reg_lookup( &s, RCLASS_VEC_FPR, &regno );
-+                  if ( !ok )
++                  if (!reg_lookup( &s, RCLASS_VEC_FPR, &regno ))
 +                    as_bad( _( "Invalid vector register" ) );
 +                  INSERT_OPERAND( VFR, *ip, regno );
 +                  continue;
 +                }
 +              break;
 +
++	    case 'C': /* RVC */
++	      switch (*++args)
++		{
++		case 'd': /* RD x8-x15 */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
++		      || !(regno >= 8 && regno <= 15))
++		    break;
++		  INSERT_OPERAND (CRDS, *ip, regno % 8);
++		  continue;
++		case 's': /* RS1 x8-x15 */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
++		      || !(regno >= 8 && regno <= 15))
++		    break;
++		  INSERT_OPERAND (CRS1S, *ip, regno % 8);
++		  continue;
++		case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15 */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
++		      || EXTRACT_OPERAND (CRS1S, *ip) + 8 != regno)
++		    break;
++		  continue;
++		case 't': /* RS2 x8-x15 */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
++		      || !(regno >= 8 && regno <= 15))
++		    break;
++		  INSERT_OPERAND (CRS2S, *ip, regno % 8);
++		  continue;
++		case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15 */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
++		      || EXTRACT_OPERAND (CRS2S, *ip) + 8 != regno)
++		    break;
++		  continue;
++		case 'D': /* RD, nonzero */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno) || regno == 0)
++		    break;
++		  INSERT_OPERAND (RD, *ip, regno);
++		  continue;
++		case 'U': /* RS1, constrained to equal RD */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
++		      || EXTRACT_OPERAND (RD, *ip) != regno)
++		    break;
++		  continue;
++		case 'T': /* RS2, nonzero */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno) || regno == 0)
++		    break;
++		  INSERT_OPERAND (CRS2, *ip, regno);
++		  continue;
++		case 'V': /* RS2 */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno))
++		    break;
++		  INSERT_OPERAND (CRS2, *ip, regno);
++		  continue;
++		case 'c': /* RS1, constrained to equal sp */
++		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
++		      || regno != X_SP)
++		    break;
++		  continue;
++		case '>':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || imm_expr->X_add_number <= 0
++		      || imm_expr->X_add_number >= 64)
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
++rvc_imm_done:
++		  s = expr_end;
++                  imm_expr->X_op = O_absent;
++		  continue;
++		case '<':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || !VALID_RVC_IMM (imm_expr->X_add_number)
++		      || imm_expr->X_add_number <= 0
++		      || imm_expr->X_add_number >= 32)
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'i':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || imm_expr->X_add_number == 0
++		      || !VALID_RVC_SIMM3 (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'j':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || imm_expr->X_add_number == 0
++		      || !VALID_RVC_IMM (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'k':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || !VALID_RVC_LW_IMM (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'l':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || !VALID_RVC_LD_IMM (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'm':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'n':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'K':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'L':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'M':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'N':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || imm_expr->X_op != O_constant
++		      || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'u':
++		  p = percent_op_utype;
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
++		    break;
++rvc_lui:
++		  if (imm_expr->X_op != O_constant
++		      || imm_expr->X_add_number <= 0
++		      || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
++		      || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH/2
++			  && imm_expr->X_add_number <
++			      RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH/2))
++		    break;
++		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
++		  goto rvc_imm_done;
++		case 'v':
++		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		      || (imm_expr->X_add_number & (RISCV_IMM_REACH-1))
++		      || (int32_t)imm_expr->X_add_number
++			  != imm_expr->X_add_number)
++		    break;
++		  imm_expr->X_add_number
++		    = (uint32_t)imm_expr->X_add_number >> RISCV_IMM_BITS;
++		  goto rvc_lui;
++		case 'p':
++		  goto branch;
++		case 'a':
++		  goto jump;
++		default:
++		  as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
++		}
++	      break;
++
 +	    case ',':
 +	      ++argnum;
 +	      if (*s++ == *args)
@@ -5499,51 +5485,50 @@
 +	      break;
 +
 +	    case '<':		/* shift amount, 0 - 31 */
-+	      my_getExpression (&imm_expr, s);
-+	      check_absolute_expr (ip, &imm_expr);
-+	      if ((unsigned long) imm_expr.X_add_number > 31)
++	      my_getExpression (imm_expr, s);
++	      check_absolute_expr (ip, imm_expr);
++	      if ((unsigned long) imm_expr->X_add_number > 31)
 +		as_warn (_("Improper shift amount (%lu)"),
-+			 (unsigned long) imm_expr.X_add_number);
-+	      INSERT_OPERAND (SHAMTW, *ip, imm_expr.X_add_number);
-+	      imm_expr.X_op = O_absent;
++			 (unsigned long) imm_expr->X_add_number);
++	      INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
++	      imm_expr->X_op = O_absent;
 +	      s = expr_end;
 +	      continue;
 +
 +	    case '>':		/* shift amount, 0 - (XLEN-1) */
-+	      my_getExpression (&imm_expr, s);
-+	      check_absolute_expr (ip, &imm_expr);
-+	      if ((unsigned long) imm_expr.X_add_number > (rv64 ? 63 : 31))
++	      my_getExpression (imm_expr, s);
++	      check_absolute_expr (ip, imm_expr);
++	      if ((unsigned long) imm_expr->X_add_number >= xlen)
 +		as_warn (_("Improper shift amount (%lu)"),
-+			 (unsigned long) imm_expr.X_add_number);
-+	      INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
-+	      imm_expr.X_op = O_absent;
++			 (unsigned long) imm_expr->X_add_number);
++	      INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
++	      imm_expr->X_op = O_absent;
 +	      s = expr_end;
 +	      continue;
 +
 +	    case 'Z':		/* CSRRxI immediate */
-+	      my_getExpression (&imm_expr, s);
-+	      check_absolute_expr (ip, &imm_expr);
-+	      if ((unsigned long) imm_expr.X_add_number > 31)
++	      my_getExpression (imm_expr, s);
++	      check_absolute_expr (ip, imm_expr);
++	      if ((unsigned long) imm_expr->X_add_number > 31)
 +		as_warn (_("Improper CSRxI immediate (%lu)"),
-+			 (unsigned long) imm_expr.X_add_number);
-+	      INSERT_OPERAND (RS1, *ip, imm_expr.X_add_number);
-+	      imm_expr.X_op = O_absent;
++			 (unsigned long) imm_expr->X_add_number);
++	      INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
++	      imm_expr->X_op = O_absent;
 +	      s = expr_end;
 +	      continue;
 +
 +	    case 'E':		/* Control register.  */
-+	      ok = reg_lookup (&s, RCLASS_CSR, &regno);
-+	      if (ok)
++	      if (reg_lookup (&s, RCLASS_CSR, &regno))
 +	        INSERT_OPERAND (CSR, *ip, regno);
 +	      else
 +		{
-+	          my_getExpression (&imm_expr, s);
-+	          check_absolute_expr (ip, &imm_expr);
-+		  if ((unsigned long) imm_expr.X_add_number > 0xfff)
++	          my_getExpression (imm_expr, s);
++	          check_absolute_expr (ip, imm_expr);
++		  if ((unsigned long) imm_expr->X_add_number > 0xfff)
 +	            as_warn(_("Improper CSR address (%lu)"),
-+	                    (unsigned long) imm_expr.X_add_number);
-+	          INSERT_OPERAND (CSR, *ip, imm_expr.X_add_number);
-+		  imm_expr.X_op = O_absent;
++	                    (unsigned long) imm_expr->X_add_number);
++	          INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
 +		  s = expr_end;
 +	        }
 +	      continue;
@@ -5571,8 +5556,7 @@
 +	    case 'd':		/* destination register */
 +	    case 's':		/* source register */
 +	    case 't':		/* target register */
-+	      ok = reg_lookup (&s, RCLASS_GPR, &regno);
-+	      if (ok)
++	      if (reg_lookup (&s, RCLASS_GPR, &regno))
 +		{
 +		  c = *args;
 +		  if (*s == ' ')
@@ -5630,55 +5614,55 @@
 +	      break;
 +
 +	    case 'I':
-+	      my_getExpression (&imm_expr, s);
-+	      if (imm_expr.X_op != O_big
-+		  && imm_expr.X_op != O_constant)
-+		insn_error = _("absolute expression required");
-+	      normalize_constant_expr (&imm_expr);
++	      my_getExpression (imm_expr, s);
++	      if (imm_expr->X_op != O_big
++		  && imm_expr->X_op != O_constant)
++		break;
++	      normalize_constant_expr (imm_expr);
 +	      s = expr_end;
 +	      continue;
 +
 +	    case 'A':
-+	      my_getExpression (&offset_expr, s);
-+	      normalize_constant_expr (&offset_expr);
-+	      imm_reloc = BFD_RELOC_32;
++	      my_getExpression (imm_expr, s);
++	      normalize_constant_expr (imm_expr);
++	      *imm_reloc = BFD_RELOC_32;
 +	      s = expr_end;
 +	      continue;
 +
 +	    case 'j': /* sign-extended immediate */
-+	      imm_reloc = BFD_RELOC_RISCV_LO12_I;
++	      *imm_reloc = BFD_RELOC_RISCV_LO12_I;
 +	      p = percent_op_itype;
 +	      goto alu_op;
 +	    case 'q': /* store displacement */
 +	      p = percent_op_stype;
-+	      offset_reloc = BFD_RELOC_RISCV_LO12_S;
++	      *imm_reloc = BFD_RELOC_RISCV_LO12_S;
 +	      goto load_store;
 +	    case 'o': /* load displacement */
 +	      p = percent_op_itype;
-+	      offset_reloc = BFD_RELOC_RISCV_LO12_I;
++	      *imm_reloc = BFD_RELOC_RISCV_LO12_I;
 +	      goto load_store;
 +	    case '0': /* AMO "displacement," which must be zero */
 +	      p = percent_op_rtype;
-+	      offset_reloc = BFD_RELOC_UNUSED;
++	      *imm_reloc = BFD_RELOC_UNUSED;
 +load_store:
 +	      /* Check whether there is only a single bracketed expression
 +	         left.  If so, it must be the base register and the
 +	         constant must be zero.  */
-+	      offset_expr.X_op = O_constant;
-+	      offset_expr.X_add_number = 0;
++	      imm_expr->X_op = O_constant;
++	      imm_expr->X_add_number = 0;
 +	      if (*s == '(' && strchr (s + 1, '(') == 0)
 +		continue;
 +alu_op:
 +	      /* If this value won't fit into a 16 bit offset, then go
 +	         find a macro that will generate the 32 bit offset
 +	         code pattern.  */
-+	      if (!my_getSmallExpression (&offset_expr, &offset_reloc, s, p))
++	      if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
 +		{
-+		  normalize_constant_expr (&offset_expr);
-+		  if (offset_expr.X_op != O_constant
-+		      || (*args == '0' && offset_expr.X_add_number != 0)
-+	              || offset_expr.X_add_number >= (signed)RISCV_IMM_REACH/2
-+	              || offset_expr.X_add_number < -(signed)RISCV_IMM_REACH/2)
++		  normalize_constant_expr (imm_expr);
++		  if (imm_expr->X_op != O_constant
++		      || (*args == '0' && imm_expr->X_add_number != 0)
++	              || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
++	              || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
 +		    break;
 +		}
 +
@@ -5686,38 +5670,40 @@
 +	      continue;
 +
 +	    case 'p':		/* pc relative offset */
-+	      offset_reloc = BFD_RELOC_12_PCREL;
-+	      my_getExpression (&offset_expr, s);
++branch:
++	      *imm_reloc = BFD_RELOC_12_PCREL;
++	      my_getExpression (imm_expr, s);
 +	      s = expr_end;
 +	      continue;
 +
 +	    case 'u':		/* upper 20 bits */
 +	      p = percent_op_utype;
-+	      if (!my_getSmallExpression (&imm_expr, &imm_reloc, s, p)
-+		  && imm_expr.X_op == O_constant)
++	      if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)
++		  && imm_expr->X_op == O_constant)
 +		{
-+		  if (imm_expr.X_add_number < 0
-+		      || imm_expr.X_add_number >= (signed)RISCV_BIGIMM_REACH)
++		  if (imm_expr->X_add_number < 0
++		      || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
 +		    as_bad (_("lui expression not in range 0..1048575"));
 +	      
-+		  imm_reloc = BFD_RELOC_RISCV_HI20;
-+		  imm_expr.X_add_number <<= RISCV_IMM_BITS;
++		  *imm_reloc = BFD_RELOC_RISCV_HI20;
++		  imm_expr->X_add_number <<= RISCV_IMM_BITS;
 +		}
 +	      s = expr_end;
 +	      continue;
 +
 +	    case 'a':		/* 26 bit address */
-+	      my_getExpression (&offset_expr, s);
++jump:
++	      my_getExpression (imm_expr, s);
 +	      s = expr_end;
-+	      offset_reloc = BFD_RELOC_RISCV_JMP;
++	      *imm_reloc = BFD_RELOC_RISCV_JMP;
 +	      continue;
 +
 +	    case 'c':
-+	      my_getExpression (&offset_expr, s);
++	      my_getExpression (imm_expr, s);
 +	      s = expr_end;
-+	      offset_reloc = BFD_RELOC_RISCV_CALL;
++	      *imm_reloc = BFD_RELOC_RISCV_CALL;
 +	      if (*s == '@')
-+		offset_reloc = BFD_RELOC_RISCV_CALL_PLT, s++;
++		*imm_reloc = BFD_RELOC_RISCV_CALL_PLT, s++;
 +	      continue;
 +
 +	    default:
@@ -5726,51 +5712,37 @@
 +	    }
 +	  break;
 +	}
-+      /* Args don't match.  */
-+      if (insn + 1 < &riscv_opcodes[NUMOPCODES] &&
-+	  !strcmp (insn->name, insn[1].name))
-+	{
-+	  ++insn;
-+	  s = argsStart;
-+	  insn_error = _("illegal operands");
-+	  continue;
-+	}
-+      if (save_c)
-+	*(--argsStart) = save_c;
-+      insn_error = _("illegal operands");
-+      return;
++      s = argsStart;
++      error = _("illegal operands");
 +    }
++
++out:
++  /* Restore the character we might have clobbered above.  */
++  if (save_c)
++    *(argsStart - 1) = save_c;
++
++  return error;
 +}
 +
 +void
 +md_assemble (char *str)
 +{
 +  struct riscv_cl_insn insn;
++  expressionS imm_expr;
++  bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
 +
-+  imm_expr.X_op = O_absent;
-+  offset_expr.X_op = O_absent;
-+  imm_reloc = BFD_RELOC_UNUSED;
-+  offset_reloc = BFD_RELOC_UNUSED;
++  const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc);
 +
-+  riscv_ip (str, &insn);
-+
-+  if (insn_error)
++  if (error)
 +    {
-+      as_bad ("%s `%s'", insn_error, str);
++      as_bad ("%s `%s'", error, str);
 +      return;
 +    }
 +
 +  if (insn.insn_mo->pinfo == INSN_MACRO)
-+    macro (&insn);
++    macro (&insn, &imm_expr, &imm_reloc);
 +  else
-+    {
-+      if (imm_expr.X_op != O_absent)
-+	append_insn (&insn, &imm_expr, imm_reloc);
-+      else if (offset_expr.X_op != O_absent)
-+	append_insn (&insn, &offset_expr, offset_reloc);
-+      else
-+	append_insn (&insn, NULL, BFD_RELOC_UNUSED);
-+    }
++    append_insn (&insn, &imm_expr, imm_reloc);
 +}
 +
 +char *
@@ -5828,15 +5800,16 @@
 +      break;
 +
 +    case OPTION_M32:
-+      rv64 = FALSE;
++      xlen = 32;
 +      break;
 +
 +    case OPTION_M64:
-+      rv64 = TRUE;
++      xlen = 64;
 +      break;
 +
 +    case OPTION_MARCH:
-+      riscv_set_arch(arg);
++      riscv_set_arch (arg);
++      break;
 +
 +    case OPTION_NO_PIC:
 +      riscv_opts.pic = FALSE;
@@ -5857,7 +5830,20 @@
 +riscv_after_parse_args (void)
 +{
 +  if (riscv_subsets == NULL)
-+    riscv_set_arch("RVIMAFDXcustom");
++    riscv_set_arch ("RVIMAFDXcustom");
++
++  if (xlen == 0)
++    {
++      if (strcmp (default_arch, "riscv32") == 0)
++	xlen = 32;
++      else if (strcmp (default_arch, "riscv64") == 0)
++	xlen = 64;
++      else
++	as_bad ("unknown default architecture `%s'", default_arch);
++    }
++
++  if (riscv_opts.rvc)
++    elf_flags |= EF_RISCV_RVC;
 +}
 +
 +void
@@ -5957,7 +5943,7 @@
 +      if (fixP->fx_addsy)
 +	{
 +	  /* Fill in a tentative value to improve objdump readability.  */
-+	  bfd_vma delta = ENCODE_UJTYPE_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP);
++	  bfd_vma delta = ENCODE_UJTYPE_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP - md_pcrel_from (fixP));
 +	  bfd_putl32 (bfd_getl32 (buf) | delta, buf);
 +	}
 +      break;
@@ -5966,11 +5952,29 @@
 +      if (fixP->fx_addsy)
 +	{
 +	  /* Fill in a tentative value to improve objdump readability.  */
-+	  bfd_vma delta = ENCODE_SBTYPE_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP);
++	  bfd_vma delta = ENCODE_SBTYPE_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP - md_pcrel_from (fixP));
 +	  bfd_putl32 (bfd_getl32 (buf) | delta, buf);
 +	}
 +      break;
 +
++    case BFD_RELOC_RISCV_RVC_BRANCH:
++      if (fixP->fx_addsy)
++	{
++	  /* Fill in a tentative value to improve objdump readability.  */
++	  bfd_vma delta = ENCODE_RVC_B_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP - md_pcrel_from (fixP));
++	  bfd_putl16 (bfd_getl16 (buf) | delta, buf);
++	}
++      break;
++
++    case BFD_RELOC_RISCV_RVC_JUMP:
++      if (fixP->fx_addsy)
++	{
++	  /* Fill in a tentative value to improve objdump readability.  */
++	  bfd_vma delta = ENCODE_RVC_J_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP - md_pcrel_from (fixP));
++	  bfd_putl16 (bfd_getl16 (buf) | delta, buf);
++	}
++      break;
++
 +    case BFD_RELOC_RISCV_PCREL_LO12_S:
 +    case BFD_RELOC_RISCV_PCREL_LO12_I:
 +    case BFD_RELOC_RISCV_CALL:
@@ -5985,7 +5989,7 @@
 +    }
 +}
 +
-+/* This structure is used to hold a stack of .set values.  */
++/* This structure is used to hold a stack of .option values.  */
 +
 +struct riscv_option_stack
 +{
@@ -5995,7 +5999,7 @@
 +
 +static struct riscv_option_stack *riscv_opts_stack;
 +
-+/* Handle the .set pseudo-op.  */
++/* Handle the .option pseudo-op.  */
 +
 +static void
 +s_riscv_option (int x ATTRIBUTE_UNUSED)
@@ -6084,11 +6088,23 @@
 +/* Align to a given power of two.  */
 +
 +static void
-+s_align (int x ATTRIBUTE_UNUSED)
++s_align (int bytes_p)
 +{
-+  int alignment, fill_value = 0, fill_value_specified = 0;
++  int fill_value = 0, fill_value_specified = 0;
++  int min_text_alignment = riscv_opts.rvc ? 2 : 4;
++  int alignment = get_absolute_expression(), bytes;
 +
-+  alignment = get_absolute_expression ();
++  if (bytes_p)
++    {
++      bytes = alignment;
++      if (bytes < 1 || (bytes & (bytes-1)) != 0)
++	as_bad (_("alignment not a power of 2: %d"), bytes);
++      for (alignment = 0; bytes > 1; bytes >>= 1)
++	alignment++;
++    }
++
++  bytes = 1 << alignment;
++
 +  if (alignment < 0 || alignment > 31)
 +    as_bad (_("unsatisfiable alignment: %d"), alignment);
 +
@@ -6099,22 +6115,25 @@
 +      fill_value_specified = 1;
 +    }
 +
-+  if (!fill_value_specified && subseg_text_p (now_seg) && alignment > 2)
++  if (!fill_value_specified && subseg_text_p (now_seg)
++      && bytes > min_text_alignment)
 +    {
 +      /* Emit the worst-case NOP string.  The linker will delete any
 +         unnecessary NOPs.  This allows us to support code alignment
 +         in spite of linker relaxations.  */
-+      bfd_vma i, worst_case_nop_bytes = (1L << alignment) - 4;
-+      char *nops = frag_more (worst_case_nop_bytes);
-+      for (i = 0; i < worst_case_nop_bytes; i += 4)
++      bfd_vma i, worst_case_bytes = bytes - min_text_alignment;
++      char *nops = frag_more (worst_case_bytes);
++      for (i = 0; i < worst_case_bytes - 2; i += 4)
 +	md_number_to_chars (nops + i, RISCV_NOP, 4);
++      if (i < worst_case_bytes)
++	md_number_to_chars (nops + i, RVC_NOP, 2);
 +
 +      expressionS ex;
 +      ex.X_op = O_constant;
-+      ex.X_add_number = worst_case_nop_bytes;
++      ex.X_add_number = worst_case_bytes;
 +
 +      fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
-+		   &ex, TRUE, BFD_RELOC_RISCV_ALIGN);
++		   &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
 +    }
 +  else if (alignment)
 +    frag_align (alignment, fill_value, 0);
@@ -6141,13 +6160,7 @@
 +  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
 +  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
 +  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
-+
-+  if (fixp->fx_pcrel)
-+    /* At this point, fx_addnumber is "symbol offset - pcrel address".
-+       Relocations want only the symbol offset.  */
-+    reloc->addend = fixp->fx_addnumber + reloc->address;
-+  else
-+    reloc->addend = fixp->fx_addnumber;
++  reloc->addend = fixp->fx_addnumber;
 +
 +  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
 +  if (reloc->howto == NULL)
@@ -6182,15 +6195,16 @@
 +  return 0;
 +}
 +
-+/* Convert a machine dependent frag.  */
++/* Expand far branches to multi-instruction sequences.  */
 +
 +static void
 +md_convert_frag_branch (fragS *fragp)
 +{
 +  bfd_byte *buf;
-+  insn_t insn;
 +  expressionS exp;
 +  fixS *fixp;
++  insn_t insn;
++  int rs1, reloc;
 +
 +  buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
 +
@@ -6198,10 +6212,51 @@
 +  exp.X_add_symbol = fragp->fr_symbol;
 +  exp.X_add_number = fragp->fr_offset;
 +
-+  if (RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
++  gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
++
++  if (RELAX_BRANCH_RVC (fragp->fr_subtype))
 +    {
-+      gas_assert (fragp->fr_var == 8);
-+      /* We could relax JAL to AUIPC/JALR, but we don't do this yet. */
++      switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
++	{
++	  case 8:
++	  case 4:
++	    /* Expand the RVC branch into a RISC-V one.  */
++	    insn = bfd_getl16 (buf);
++	    rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
++	    if ((insn & MASK_C_J) == MATCH_C_J)
++	      insn = MATCH_JAL;
++	    else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
++	      insn = MATCH_JAL | (X_RA << OP_SH_RD);
++	    else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
++	      insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
++	    else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
++	      insn = MATCH_BNE | (rs1 << OP_SH_RS1);
++	    else if ((insn & MASK_C_BLTZ) == MATCH_C_BLTZ)
++	      insn = MATCH_BLT | (rs1 << OP_SH_RS1);
++	    else if ((insn & MASK_C_BGEZ) == MATCH_C_BGEZ)
++	      insn = MATCH_BGE | (rs1 << OP_SH_RS1);
++	    else
++	      abort ();
++	    bfd_putl32 (insn, buf);
++	    break;
++
++	  case 2:
++	    /* Just keep the RVC branch.  */
++	    reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
++		    ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
++	    fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
++				2, &exp, FALSE, reloc);
++	    buf += 2;
++	    goto done;
++
++	  default:
++	    abort();
++	}
++    }
++
++  switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
++    {
++    case 8:
 +      gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
 +      
 +      /* Invert the branch condition.  Branch over the jump. */
@@ -6216,17 +6271,23 @@
 +			  4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
 +      md_number_to_chars ((char *) buf, MATCH_JAL, 4);
 +      buf += 4;
-+    }
-+  else
-+    {
++      break;
++
++    case 4:
++      reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
++	      ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
 +      fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-+			  4, &exp, FALSE, BFD_RELOC_12_PCREL);
++			  4, &exp, FALSE, reloc);
 +      buf += 4;
++      break;
++
++    default:
++      abort ();
 +    }
 +
++done:
 +  fixp->fx_file = fragp->fr_file;
 +  fixp->fx_line = fragp->fr_line;
-+  fixp->fx_pcrel = 1;
 +
 +  gas_assert (buf == (bfd_byte *)fragp->fr_literal
 +	      + fragp->fr_fix + fragp->fr_var);
@@ -6282,21 +6343,7 @@
 +void
 +riscv_elf_final_processing (void)
 +{
-+  struct riscv_subset* s;
-+
-+  unsigned int Xlen = 0;
-+  for (s = riscv_subsets; s != NULL; s = s->next)
-+    if (s->name[0] == 'X')
-+      Xlen += strlen(s->name);
-+
-+  char extension[Xlen]; 
-+  extension[0] = 0;
-+  for (s = riscv_subsets; s != NULL; s = s->next)
-+    if (s->name[0] == 'X')
-+      strcat(extension, s->name);
-+
-+  EF_SET_RISCV_EXT(elf_elfheader (stdoutput)->e_flags,
-+    riscv_elf_name_to_flag (extension));
++  elf_elfheader (stdoutput)->e_flags |= elf_flags;
 +}
 +
 +/* Pseudo-op table.  */
@@ -6312,6 +6359,8 @@
 +  {"dtpreldword", s_dtprel, 8},
 +  {"bss", s_bss, 0},
 +  {"align", s_align, 0},
++  {"p2align", s_align, 0},
++  {"balign", s_align, 1},
 +
 +  /* leb128 doesn't work with relaxation; disallow it */
 +  {"uleb128", s_err, 0},
@@ -6327,9 +6376,9 @@
 +
 +  pop_insert (riscv_pseudo_table);
 +}
-diff -urN original-binutils/gas/config/tc-riscv.h binutils/gas/config/tc-riscv.h
---- original-binutils/gas/config/tc-riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/gas/config/tc-riscv.h	2015-03-07 09:51:45.659139025 +0100
+diff -urN empty/gas/config/tc-riscv.h binutils-2.25/gas/config/tc-riscv.h
+--- empty/gas/config/tc-riscv.h	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/gas/config/tc-riscv.h	2015-07-18 00:02:36.222287541 +0200
 @@ -0,0 +1,102 @@
 +/* tc-riscv.h -- header file for tc-riscv.c.
 +   Copyright 2011-2014 Free Software Foundation, Inc.
@@ -6425,135 +6474,18 @@
 +#define tc_regname_to_dw2regnum tc_riscv_regname_to_dw2regnum
 +extern int tc_riscv_regname_to_dw2regnum (char *regname);
 +
-+extern bfd_boolean rv64;
++extern unsigned xlen;
 +#define DWARF2_DEFAULT_RETURN_COLUMN X_RA
-+#define DWARF2_CIE_DATA_ALIGNMENT (rv64 ? 8 : 4)
++#define DWARF2_CIE_DATA_ALIGNMENT (xlen / 8)
 +
 +#define elf_tc_final_processing riscv_elf_final_processing
 +extern void riscv_elf_final_processing (void);
 +
 +#endif /* TC_RISCV */
-diff -urN original-binutils/gas/configure.tgt binutils/gas/configure.tgt
---- original-binutils/gas/configure.tgt	2014-10-14 09:32:03.000000000 +0200
-+++ binutils-2.25/gas/configure.tgt	2015-03-07 09:55:02.379135671 +0100
-@@ -86,6 +86,7 @@
-   pj*)			cpu_type=pj endian=big ;;
-   powerpc*le*)		cpu_type=ppc endian=little ;;
-   powerpc*)		cpu_type=ppc endian=big ;;
-+  riscv*)		cpu_type=riscv endian=little ;;
-   rs6000*)		cpu_type=ppc ;;
-   rl78*)		cpu_type=rl78 ;;
-   rx)			cpu_type=rx ;;
-@@ -384,6 +385,8 @@
-   ppc-*-kaos*)				fmt=elf ;;
-   ppc-*-lynxos*)			fmt=elf em=lynx ;;
- 
-+  riscv*-*-*)			fmt=elf endian=little em=linux bfd_gas=yes ;;
-+
-   s390-*-linux-*)			fmt=elf em=linux ;;
-   s390-*-tpf*)				fmt=elf ;;
- 
-diff -urN original-binutils/gas/Makefile.am binutils/gas/Makefile.am
---- original-binutils/gas/Makefile.am	2014-10-14 09:32:02.000000000 +0200
-+++ binutils-2.25/gas/Makefile.am	2015-03-07 09:55:02.379135671 +0100
-@@ -171,6 +171,7 @@
- 	config/tc-pdp11.c \
- 	config/tc-pj.c \
- 	config/tc-ppc.c \
-+	config/tc-riscv.c \
- 	config/tc-rl78.c \
- 	config/tc-rx.c \
- 	config/tc-s390.c \
-@@ -242,6 +243,7 @@
- 	config/tc-pdp11.h \
- 	config/tc-pj.h \
- 	config/tc-ppc.h \
-+	config/tc-riscv.h \
- 	config/tc-rl78.h \
- 	config/tc-rx.h \
- 	config/tc-s390.h \
-diff -urN original-binutils/gas/Makefile.in binutils/gas/Makefile.in
---- original-binutils/gas/Makefile.in	2014-10-14 09:32:02.000000000 +0200
-+++ binutils-2.25/gas/Makefile.in	2015-03-07 09:55:02.379135671 +0100
-@@ -440,6 +440,7 @@
- 	config/tc-pdp11.c \
- 	config/tc-pj.c \
- 	config/tc-ppc.c \
-+	config/tc-riscv.c \
- 	config/tc-rl78.c \
- 	config/tc-rx.c \
- 	config/tc-s390.c \
-@@ -511,6 +512,7 @@
- 	config/tc-pdp11.h \
- 	config/tc-pj.h \
- 	config/tc-ppc.h \
-+	config/tc-riscv.h \
- 	config/tc-rl78.h \
- 	config/tc-rx.h \
- 	config/tc-s390.h \
-@@ -866,6 +868,7 @@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-riscv.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rl78.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rx.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-s390.Po@am__quote@
-@@ -1571,6 +1574,20 @@
- @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- @am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ppc.obj `if test -f 'config/tc-ppc.c'; then $(CYGPATH_W) 'config/tc-ppc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ppc.c'; fi`
- 
-+tc-riscv.o: config/tc-riscv.c
-+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.o -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c
-+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='config/tc-riscv.c' object='tc-riscv.o' libtool=no @AMDEPBACKSLASH@
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c
-+
-+tc-riscv.obj: config/tc-riscv.c
-+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.obj -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi`
-+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='config/tc-riscv.c' object='tc-riscv.obj' libtool=no @AMDEPBACKSLASH@
-+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi`
-+
- tc-rl78.o: config/tc-rl78.c
- @am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-rl78.o -MD -MP -MF $(DEPDIR)/tc-rl78.Tpo -c -o tc-rl78.o `test -f 'config/tc-rl78.c' || echo '$(srcdir)/'`config/tc-rl78.c
- @am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-rl78.Tpo $(DEPDIR)/tc-rl78.Po
-diff -urN original-binutils/include/dis-asm.h binutils/include/dis-asm.h
---- original-binutils/include/dis-asm.h	2014-10-14 09:32:04.000000000 +0200
-+++ binutils-2.25/include/dis-asm.h	2015-03-07 09:55:02.379135671 +0100
-@@ -254,6 +254,7 @@
- extern int print_insn_little_mips	(bfd_vma, disassemble_info *);
- extern int print_insn_little_nios2	(bfd_vma, disassemble_info *);
- extern int print_insn_little_powerpc	(bfd_vma, disassemble_info *);
-+extern int print_insn_riscv		(bfd_vma, disassemble_info *);
- extern int print_insn_little_score      (bfd_vma, disassemble_info *); 
- extern int print_insn_lm32		(bfd_vma, disassemble_info *);
- extern int print_insn_m32c	        (bfd_vma, disassemble_info *);
-@@ -313,6 +314,7 @@
- extern void print_i386_disassembler_options (FILE *);
- extern void print_mips_disassembler_options (FILE *);
- extern void print_ppc_disassembler_options (FILE *);
-+extern void print_riscv_disassembler_options (FILE *);
- extern void print_arm_disassembler_options (FILE *);
- extern void parse_arm_disassembler_option (char *);
- extern void print_s390_disassembler_options (FILE *);
-diff -urN original-binutils/include/elf/common.h binutils/include/elf/common.h
---- original-binutils/include/elf/common.h	2014-10-14 09:32:04.000000000 +0200
-+++ binutils-2.25/include/elf/common.h	2015-03-07 09:55:02.383135671 +0100
-@@ -301,6 +301,7 @@
- #define EM_INTEL207	207	/* Reserved by Intel */
- #define EM_INTEL208	208	/* Reserved by Intel */
- #define EM_INTEL209	209	/* Reserved by Intel */
-+#define EM_RISCV	243	/* Reserved by Intel */
- 
- /* If it is necessary to assign new unofficial EM_* values, please pick large
-    random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
-diff -urN original-binutils/include/elf/riscv.h binutils/include/elf/riscv.h
---- original-binutils/include/elf/riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/include/elf/riscv.h	2015-03-07 09:51:45.659139025 +0100
-@@ -0,0 +1,138 @@
+diff -urN empty/include/elf/riscv.h binutils-2.25/include/elf/riscv.h
+--- empty/include/elf/riscv.h	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/include/elf/riscv.h	2015-07-18 00:02:36.222287541 +0200
+@@ -0,0 +1,143 @@
 +/* RISC-V ELF support for BFD.
 +   Copyright 2011-2014 Free Software Foundation, Inc.
 +
@@ -6630,10 +6562,15 @@
 +  RELOC_NUMBER (R_RISCV_GNU_VTINHERIT, 41)
 +  RELOC_NUMBER (R_RISCV_GNU_VTENTRY, 42)
 +  RELOC_NUMBER (R_RISCV_ALIGN, 43)
++  RELOC_NUMBER (R_RISCV_RVC_BRANCH, 44)
++  RELOC_NUMBER (R_RISCV_RVC_JUMP, 45)
 +END_RELOC_NUMBERS (R_RISCV_max)
 +
 +/* Processor specific flags for the ELF header e_flags field.  */
 +
++/* File may contain compressed instructions.  */
++#define EF_RISCV_RVC 0x0001
++
 +/* Custom flag definitions. */
 +
 +#define EF_RISCV_EXT_MASK 0xffff
@@ -6692,10 +6629,1362 @@
 +}
 +
 +#endif /* _ELF_RISCV_H */
-diff -urN original-binutils/include/opcode/riscv.h binutils/include/opcode/riscv.h
---- original-binutils/include/opcode/riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/include/opcode/riscv.h	2015-03-07 09:51:45.659139025 +0100
-@@ -0,0 +1,320 @@
+diff -urN empty/include/opcode/riscv-opc.h binutils-2.25/include/opcode/riscv-opc.h
+--- empty/include/opcode/riscv-opc.h	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/include/opcode/riscv-opc.h	2015-07-18 00:02:36.222287541 +0200
+@@ -0,0 +1,1348 @@
++/* Automatically generated by parse-opcodes */
++#ifndef RISCV_ENCODING_H
++#define RISCV_ENCODING_H
++#define MATCH_ADD 0x33
++#define MASK_ADD  0xfe00707f
++#define MATCH_ADDI 0x13
++#define MASK_ADDI  0x707f
++#define MATCH_ADDIW 0x1b
++#define MASK_ADDIW  0x707f
++#define MATCH_ADDW 0x3b
++#define MASK_ADDW  0xfe00707f
++#define MATCH_AMOADD_D 0x302f
++#define MASK_AMOADD_D  0xf800707f
++#define MATCH_AMOADD_W 0x202f
++#define MASK_AMOADD_W  0xf800707f
++#define MATCH_AMOAND_D 0x6000302f
++#define MASK_AMOAND_D  0xf800707f
++#define MATCH_AMOAND_W 0x6000202f
++#define MASK_AMOAND_W  0xf800707f
++#define MATCH_AMOMAX_D 0xa000302f
++#define MASK_AMOMAX_D  0xf800707f
++#define MATCH_AMOMAX_W 0xa000202f
++#define MASK_AMOMAX_W  0xf800707f
++#define MATCH_AMOMAXU_D 0xe000302f
++#define MASK_AMOMAXU_D  0xf800707f
++#define MATCH_AMOMAXU_W 0xe000202f
++#define MASK_AMOMAXU_W  0xf800707f
++#define MATCH_AMOMIN_D 0x8000302f
++#define MASK_AMOMIN_D  0xf800707f
++#define MATCH_AMOMIN_W 0x8000202f
++#define MASK_AMOMIN_W  0xf800707f
++#define MATCH_AMOMINU_D 0xc000302f
++#define MASK_AMOMINU_D  0xf800707f
++#define MATCH_AMOMINU_W 0xc000202f
++#define MASK_AMOMINU_W  0xf800707f
++#define MATCH_AMOOR_D 0x4000302f
++#define MASK_AMOOR_D  0xf800707f
++#define MATCH_AMOOR_W 0x4000202f
++#define MASK_AMOOR_W  0xf800707f
++#define MATCH_AMOSWAP_D 0x800302f
++#define MASK_AMOSWAP_D  0xf800707f
++#define MATCH_AMOSWAP_W 0x800202f
++#define MASK_AMOSWAP_W  0xf800707f
++#define MATCH_AMOXOR_D 0x2000302f
++#define MASK_AMOXOR_D  0xf800707f
++#define MATCH_AMOXOR_W 0x2000202f
++#define MASK_AMOXOR_W  0xf800707f
++#define MATCH_AND 0x7033
++#define MASK_AND  0xfe00707f
++#define MATCH_ANDI 0x7013
++#define MASK_ANDI  0x707f
++#define MATCH_AUIPC 0x17
++#define MASK_AUIPC  0x7f
++#define MATCH_BEQ 0x63
++#define MASK_BEQ  0x707f
++#define MATCH_BGE 0x5063
++#define MASK_BGE  0x707f
++#define MATCH_BGEU 0x7063
++#define MASK_BGEU  0x707f
++#define MATCH_BLT 0x4063
++#define MASK_BLT  0x707f
++#define MATCH_BLTU 0x6063
++#define MASK_BLTU  0x707f
++#define MATCH_BNE 0x1063
++#define MASK_BNE  0x707f
++#define MATCH_C_ADD 0x1000
++#define MASK_C_ADD  0xf003
++#define MATCH_C_ADD3 0xa000
++#define MASK_C_ADD3  0xe063
++#define MATCH_C_ADDI 0xc002
++#define MASK_C_ADDI  0xe003
++#define MATCH_C_ADDI16SP 0xc002
++#define MASK_C_ADDI16SP  0xef83
++#define MATCH_C_ADDI4SPN 0xa001
++#define MASK_C_ADDI4SPN  0xe003
++#define MATCH_C_ADDIN 0x8001
++#define MASK_C_ADDIN  0xe063
++#define MATCH_C_ADDIW 0xe002
++#define MASK_C_ADDIW  0xe003
++#define MATCH_C_ADDW 0x9000
++#define MASK_C_ADDW  0xf003
++#define MATCH_C_AND3 0xa060
++#define MASK_C_AND3  0xe063
++#define MATCH_C_ANDI 0xe002
++#define MASK_C_ANDI  0xe003
++#define MATCH_C_ANDIN 0x8061
++#define MASK_C_ANDIN  0xe063
++#define MATCH_C_BEQZ 0x4002
++#define MASK_C_BEQZ  0xe003
++#define MATCH_C_BGEZ 0xe001
++#define MASK_C_BGEZ  0xe003
++#define MATCH_C_BLTZ 0x6001
++#define MASK_C_BLTZ  0xe003
++#define MATCH_C_BNEZ 0x6002
++#define MASK_C_BNEZ  0xe003
++#define MATCH_C_EBREAK 0x1000
++#define MASK_C_EBREAK  0xffff
++#define MATCH_C_J 0x2
++#define MASK_C_J  0xe003
++#define MATCH_C_JAL 0x2002
++#define MASK_C_JAL  0xe003
++#define MATCH_C_JALR 0xa002
++#define MASK_C_JALR  0xf07f
++#define MATCH_C_JR 0x8002
++#define MASK_C_JR  0xf07f
++#define MATCH_C_LD 0xe000
++#define MASK_C_LD  0xe003
++#define MATCH_C_LDSP 0xe001
++#define MASK_C_LDSP  0xe003
++#define MATCH_C_LI 0x8002
++#define MASK_C_LI  0xe003
++#define MATCH_C_LUI 0xa002
++#define MASK_C_LUI  0xe003
++#define MATCH_C_LW 0xc000
++#define MASK_C_LW  0xe003
++#define MATCH_C_LWSP 0xc001
++#define MASK_C_LWSP  0xe003
++#define MATCH_C_MV 0x0
++#define MASK_C_MV  0xf003
++#define MATCH_C_OR3 0xa040
++#define MASK_C_OR3  0xe063
++#define MATCH_C_ORIN 0x8041
++#define MASK_C_ORIN  0xe063
++#define MATCH_C_SD 0x6000
++#define MASK_C_SD  0xe003
++#define MATCH_C_SDSP 0x6001
++#define MASK_C_SDSP  0xe003
++#define MATCH_C_SLL 0x6400
++#define MASK_C_SLL  0xfc63
++#define MATCH_C_SLLI 0x1
++#define MASK_C_SLLI  0xe003
++#define MATCH_C_SLLIW 0x8001
++#define MASK_C_SLLIW  0xe003
++#define MATCH_C_SLLR 0x6c00
++#define MASK_C_SLLR  0xfc63
++#define MATCH_C_SLT 0x6440
++#define MASK_C_SLT  0xfc63
++#define MATCH_C_SLTR 0x6c40
++#define MASK_C_SLTR  0xfc63
++#define MATCH_C_SLTU 0x6460
++#define MASK_C_SLTU  0xfc63
++#define MATCH_C_SLTUR 0x6c60
++#define MASK_C_SLTUR  0xfc63
++#define MATCH_C_SRA 0x6020
++#define MASK_C_SRA  0xfc63
++#define MATCH_C_SRAI 0x2000
++#define MASK_C_SRAI  0xe003
++#define MATCH_C_SRL 0x6420
++#define MASK_C_SRL  0xfc63
++#define MATCH_C_SRLI 0x2001
++#define MASK_C_SRLI  0xe003
++#define MATCH_C_SRLR 0x6c20
++#define MASK_C_SRLR  0xfc63
++#define MATCH_C_SUB 0x8000
++#define MASK_C_SUB  0xf003
++#define MATCH_C_SUB3 0xa020
++#define MASK_C_SUB3  0xe063
++#define MATCH_C_SW 0x4000
++#define MASK_C_SW  0xe003
++#define MATCH_C_SWSP 0x4001
++#define MASK_C_SWSP  0xe003
++#define MATCH_C_XOR 0x6000
++#define MASK_C_XOR  0xfc63
++#define MATCH_C_XORIN 0x8021
++#define MASK_C_XORIN  0xe063
++#define MATCH_CSRRC 0x3073
++#define MASK_CSRRC  0x707f
++#define MATCH_CSRRCI 0x7073
++#define MASK_CSRRCI  0x707f
++#define MATCH_CSRRS 0x2073
++#define MASK_CSRRS  0x707f
++#define MATCH_CSRRSI 0x6073
++#define MASK_CSRRSI  0x707f
++#define MATCH_CSRRW 0x1073
++#define MASK_CSRRW  0x707f
++#define MATCH_CSRRWI 0x5073
++#define MASK_CSRRWI  0x707f
++#define MATCH_CUSTOM0 0xb
++#define MASK_CUSTOM0  0x707f
++#define MATCH_CUSTOM0_RD 0x400b
++#define MASK_CUSTOM0_RD  0x707f
++#define MATCH_CUSTOM0_RD_RS1 0x600b
++#define MASK_CUSTOM0_RD_RS1  0x707f
++#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
++#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM0_RS1 0x200b
++#define MASK_CUSTOM0_RS1  0x707f
++#define MATCH_CUSTOM0_RS1_RS2 0x300b
++#define MASK_CUSTOM0_RS1_RS2  0x707f
++#define MATCH_CUSTOM1 0x2b
++#define MASK_CUSTOM1  0x707f
++#define MATCH_CUSTOM1_RD 0x402b
++#define MASK_CUSTOM1_RD  0x707f
++#define MATCH_CUSTOM1_RD_RS1 0x602b
++#define MASK_CUSTOM1_RD_RS1  0x707f
++#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
++#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM1_RS1 0x202b
++#define MASK_CUSTOM1_RS1  0x707f
++#define MATCH_CUSTOM1_RS1_RS2 0x302b
++#define MASK_CUSTOM1_RS1_RS2  0x707f
++#define MATCH_CUSTOM2 0x5b
++#define MASK_CUSTOM2  0x707f
++#define MATCH_CUSTOM2_RD 0x405b
++#define MASK_CUSTOM2_RD  0x707f
++#define MATCH_CUSTOM2_RD_RS1 0x605b
++#define MASK_CUSTOM2_RD_RS1  0x707f
++#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
++#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM2_RS1 0x205b
++#define MASK_CUSTOM2_RS1  0x707f
++#define MATCH_CUSTOM2_RS1_RS2 0x305b
++#define MASK_CUSTOM2_RS1_RS2  0x707f
++#define MATCH_CUSTOM3 0x7b
++#define MASK_CUSTOM3  0x707f
++#define MATCH_CUSTOM3_RD 0x407b
++#define MASK_CUSTOM3_RD  0x707f
++#define MATCH_CUSTOM3_RD_RS1 0x607b
++#define MASK_CUSTOM3_RD_RS1  0x707f
++#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
++#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM3_RS1 0x207b
++#define MASK_CUSTOM3_RS1  0x707f
++#define MATCH_CUSTOM3_RS1_RS2 0x307b
++#define MASK_CUSTOM3_RS1_RS2  0x707f
++#define MATCH_DIV 0x2004033
++#define MASK_DIV  0xfe00707f
++#define MATCH_DIVU 0x2005033
++#define MASK_DIVU  0xfe00707f
++#define MATCH_DIVUW 0x200503b
++#define MASK_DIVUW  0xfe00707f
++#define MATCH_DIVW 0x200403b
++#define MASK_DIVW  0xfe00707f
++#define MATCH_EBREAK 0x100073
++#define MASK_EBREAK  0xffffffff
++#define MATCH_ECALL 0x73
++#define MASK_ECALL  0xffffffff
++#define MATCH_ERET 0x10000073
++#define MASK_ERET  0xffffffff
++#define MATCH_FADD_D 0x2000053
++#define MASK_FADD_D  0xfe00007f
++#define MATCH_FADD_H 0x4000053
++#define MASK_FADD_H  0xfe00007f
++#define MATCH_FADD_S 0x53
++#define MASK_FADD_S  0xfe00007f
++#define MATCH_FCLASS_D 0xe2001053
++#define MASK_FCLASS_D  0xfff0707f
++#define MATCH_FCLASS_S 0xe0001053
++#define MASK_FCLASS_S  0xfff0707f
++#define MATCH_FCVT_D_H 0x8c000053
++#define MASK_FCVT_D_H  0xfff0007f
++#define MATCH_FCVT_D_L 0xd2200053
++#define MASK_FCVT_D_L  0xfff0007f
++#define MATCH_FCVT_D_LU 0xd2300053
++#define MASK_FCVT_D_LU  0xfff0007f
++#define MATCH_FCVT_D_S 0x42000053
++#define MASK_FCVT_D_S  0xfff0007f
++#define MATCH_FCVT_D_W 0xd2000053
++#define MASK_FCVT_D_W  0xfff0007f
++#define MATCH_FCVT_D_WU 0xd2100053
++#define MASK_FCVT_D_WU  0xfff0007f
++#define MATCH_FCVT_H_D 0x92000053
++#define MASK_FCVT_H_D  0xfff0007f
++#define MATCH_FCVT_H_L 0x64000053
++#define MASK_FCVT_H_L  0xfff0007f
++#define MATCH_FCVT_H_LU 0x6c000053
++#define MASK_FCVT_H_LU  0xfff0007f
++#define MATCH_FCVT_H_S 0x90000053
++#define MASK_FCVT_H_S  0xfff0007f
++#define MATCH_FCVT_H_W 0x74000053
++#define MASK_FCVT_H_W  0xfff0007f
++#define MATCH_FCVT_H_WU 0x7c000053
++#define MASK_FCVT_H_WU  0xfff0007f
++#define MATCH_FCVT_L_D 0xc2200053
++#define MASK_FCVT_L_D  0xfff0007f
++#define MATCH_FCVT_L_H 0x44000053
++#define MASK_FCVT_L_H  0xfff0007f
++#define MATCH_FCVT_L_S 0xc0200053
++#define MASK_FCVT_L_S  0xfff0007f
++#define MATCH_FCVT_LU_D 0xc2300053
++#define MASK_FCVT_LU_D  0xfff0007f
++#define MATCH_FCVT_LU_H 0x4c000053
++#define MASK_FCVT_LU_H  0xfff0007f
++#define MATCH_FCVT_LU_S 0xc0300053
++#define MASK_FCVT_LU_S  0xfff0007f
++#define MATCH_FCVT_S_D 0x40100053
++#define MASK_FCVT_S_D  0xfff0007f
++#define MATCH_FCVT_S_H 0x84000053
++#define MASK_FCVT_S_H  0xfff0007f
++#define MATCH_FCVT_S_L 0xd0200053
++#define MASK_FCVT_S_L  0xfff0007f
++#define MATCH_FCVT_S_LU 0xd0300053
++#define MASK_FCVT_S_LU  0xfff0007f
++#define MATCH_FCVT_S_W 0xd0000053
++#define MASK_FCVT_S_W  0xfff0007f
++#define MATCH_FCVT_S_WU 0xd0100053
++#define MASK_FCVT_S_WU  0xfff0007f
++#define MATCH_FCVT_W_D 0xc2000053
++#define MASK_FCVT_W_D  0xfff0007f
++#define MATCH_FCVT_W_H 0x54000053
++#define MASK_FCVT_W_H  0xfff0007f
++#define MATCH_FCVT_W_S 0xc0000053
++#define MASK_FCVT_W_S  0xfff0007f
++#define MATCH_FCVT_WU_D 0xc2100053
++#define MASK_FCVT_WU_D  0xfff0007f
++#define MATCH_FCVT_WU_H 0x5c000053
++#define MASK_FCVT_WU_H  0xfff0007f
++#define MATCH_FCVT_WU_S 0xc0100053
++#define MASK_FCVT_WU_S  0xfff0007f
++#define MATCH_FDIV_D 0x1a000053
++#define MASK_FDIV_D  0xfe00007f
++#define MATCH_FDIV_H 0x1c000053
++#define MASK_FDIV_H  0xfe00007f
++#define MATCH_FDIV_S 0x18000053
++#define MASK_FDIV_S  0xfe00007f
++#define MATCH_FENCE 0xf
++#define MASK_FENCE  0x707f
++#define MATCH_FENCE_I 0x100f
++#define MASK_FENCE_I  0x707f
++#define MATCH_FEQ_D 0xa2002053
++#define MASK_FEQ_D  0xfe00707f
++#define MATCH_FEQ_H 0xac000053
++#define MASK_FEQ_H  0xfe00707f
++#define MATCH_FEQ_S 0xa0002053
++#define MASK_FEQ_S  0xfe00707f
++#define MATCH_FLD 0x3007
++#define MASK_FLD  0x707f
++#define MATCH_FLE_D 0xa2000053
++#define MASK_FLE_D  0xfe00707f
++#define MATCH_FLE_H 0xbc000053
++#define MASK_FLE_H  0xfe00707f
++#define MATCH_FLE_S 0xa0000053
++#define MASK_FLE_S  0xfe00707f
++#define MATCH_FLH 0x1007
++#define MASK_FLH  0x707f
++#define MATCH_FLT_D 0xa2001053
++#define MASK_FLT_D  0xfe00707f
++#define MATCH_FLT_H 0xb4000053
++#define MASK_FLT_H  0xfe00707f
++#define MATCH_FLT_S 0xa0001053
++#define MASK_FLT_S  0xfe00707f
++#define MATCH_FLW 0x2007
++#define MASK_FLW  0x707f
++#define MATCH_FMADD_D 0x2000043
++#define MASK_FMADD_D  0x600007f
++#define MATCH_FMADD_H 0x4000043
++#define MASK_FMADD_H  0x600007f
++#define MATCH_FMADD_S 0x43
++#define MASK_FMADD_S  0x600007f
++#define MATCH_FMAX_D 0x2a001053
++#define MASK_FMAX_D  0xfe00707f
++#define MATCH_FMAX_H 0xcc000053
++#define MASK_FMAX_H  0xfe00707f
++#define MATCH_FMAX_S 0x28001053
++#define MASK_FMAX_S  0xfe00707f
++#define MATCH_FMIN_D 0x2a000053
++#define MASK_FMIN_D  0xfe00707f
++#define MATCH_FMIN_H 0xc4000053
++#define MASK_FMIN_H  0xfe00707f
++#define MATCH_FMIN_S 0x28000053
++#define MASK_FMIN_S  0xfe00707f
++#define MATCH_FMOVN 0x6007077
++#define MASK_FMOVN  0xfe00707f
++#define MATCH_FMOVZ 0x4007077
++#define MASK_FMOVZ  0xfe00707f
++#define MATCH_FMSUB_D 0x2000047
++#define MASK_FMSUB_D  0x600007f
++#define MATCH_FMSUB_H 0x4000047
++#define MASK_FMSUB_H  0x600007f
++#define MATCH_FMSUB_S 0x47
++#define MASK_FMSUB_S  0x600007f
++#define MATCH_FMUL_D 0x12000053
++#define MASK_FMUL_D  0xfe00007f
++#define MATCH_FMUL_H 0x14000053
++#define MASK_FMUL_H  0xfe00007f
++#define MATCH_FMUL_S 0x10000053
++#define MASK_FMUL_S  0xfe00007f
++#define MATCH_FMV_D_X 0xf2000053
++#define MASK_FMV_D_X  0xfff0707f
++#define MATCH_FMV_H_X 0xf4000053
++#define MASK_FMV_H_X  0xfff0707f
++#define MATCH_FMV_S_X 0xf0000053
++#define MASK_FMV_S_X  0xfff0707f
++#define MATCH_FMV_X_D 0xe2000053
++#define MASK_FMV_X_D  0xfff0707f
++#define MATCH_FMV_X_H 0xe4000053
++#define MASK_FMV_X_H  0xfff0707f
++#define MATCH_FMV_X_S 0xe0000053
++#define MASK_FMV_X_S  0xfff0707f
++#define MATCH_FNMADD_D 0x200004f
++#define MASK_FNMADD_D  0x600007f
++#define MATCH_FNMADD_H 0x400004f
++#define MASK_FNMADD_H  0x600007f
++#define MATCH_FNMADD_S 0x4f
++#define MASK_FNMADD_S  0x600007f
++#define MATCH_FNMSUB_D 0x200004b
++#define MASK_FNMSUB_D  0x600007f
++#define MATCH_FNMSUB_H 0x400004b
++#define MASK_FNMSUB_H  0x600007f
++#define MATCH_FNMSUB_S 0x4b
++#define MASK_FNMSUB_S  0x600007f
++#define MATCH_FRCSR 0x302073
++#define MASK_FRCSR  0xfffff07f
++#define MATCH_FRFLAGS 0x102073
++#define MASK_FRFLAGS  0xfffff07f
++#define MATCH_FRRM 0x202073
++#define MASK_FRRM  0xfffff07f
++#define MATCH_FSCSR 0x301073
++#define MASK_FSCSR  0xfff0707f
++#define MATCH_FSD 0x3027
++#define MASK_FSD  0x707f
++#define MATCH_FSFLAGS 0x101073
++#define MASK_FSFLAGS  0xfff0707f
++#define MATCH_FSFLAGSI 0x105073
++#define MASK_FSFLAGSI  0xfff0707f
++#define MATCH_FSGNJ_D 0x22000053
++#define MASK_FSGNJ_D  0xfe00707f
++#define MATCH_FSGNJ_H 0x2c000053
++#define MASK_FSGNJ_H  0xfe00707f
++#define MATCH_FSGNJ_S 0x20000053
++#define MASK_FSGNJ_S  0xfe00707f
++#define MATCH_FSGNJN_D 0x22001053
++#define MASK_FSGNJN_D  0xfe00707f
++#define MATCH_FSGNJN_H 0x34000053
++#define MASK_FSGNJN_H  0xfe00707f
++#define MATCH_FSGNJN_S 0x20001053
++#define MASK_FSGNJN_S  0xfe00707f
++#define MATCH_FSGNJX_D 0x22002053
++#define MASK_FSGNJX_D  0xfe00707f
++#define MATCH_FSGNJX_H 0x3c000053
++#define MASK_FSGNJX_H  0xfe00707f
++#define MATCH_FSGNJX_S 0x20002053
++#define MASK_FSGNJX_S  0xfe00707f
++#define MATCH_FSH 0x1027
++#define MASK_FSH  0x707f
++#define MATCH_FSQRT_D 0x5a000053
++#define MASK_FSQRT_D  0xfff0007f
++#define MATCH_FSQRT_H 0x24000053
++#define MASK_FSQRT_H  0xfff0007f
++#define MATCH_FSQRT_S 0x58000053
++#define MASK_FSQRT_S  0xfff0007f
++#define MATCH_FSRM 0x201073
++#define MASK_FSRM  0xfff0707f
++#define MATCH_FSRMI 0x205073
++#define MASK_FSRMI  0xfff0707f
++#define MATCH_FSUB_D 0xa000053
++#define MASK_FSUB_D  0xfe00007f
++#define MATCH_FSUB_H 0xc000053
++#define MASK_FSUB_H  0xfe00007f
++#define MATCH_FSUB_S 0x8000053
++#define MASK_FSUB_S  0xfe00007f
++#define MATCH_FSW 0x2027
++#define MASK_FSW  0x707f
++#define MATCH_HRTS 0x20500073
++#define MASK_HRTS  0xffffffff
++#define MATCH_JAL 0x6f
++#define MASK_JAL  0x7f
++#define MATCH_JALR 0x67
++#define MASK_JALR  0x707f
++#define MATCH_LB 0x3
++#define MASK_LB  0x707f
++#define MATCH_LBU 0x4003
++#define MASK_LBU  0x707f
++#define MATCH_LD 0x3003
++#define MASK_LD  0x707f
++#define MATCH_LH 0x1003
++#define MASK_LH  0x707f
++#define MATCH_LHU 0x5003
++#define MASK_LHU  0x707f
++#define MATCH_LR_D 0x1000302f
++#define MASK_LR_D  0xf9f0707f
++#define MATCH_LR_W 0x1000202f
++#define MASK_LR_W  0xf9f0707f
++#define MATCH_LUI 0x37
++#define MASK_LUI  0x7f
++#define MATCH_LW 0x2003
++#define MASK_LW  0x707f
++#define MATCH_LWU 0x6003
++#define MASK_LWU  0x707f
++#define MATCH_MOVN 0x2007077
++#define MASK_MOVN  0xfe00707f
++#define MATCH_MOVZ 0x7077
++#define MASK_MOVZ  0xfe00707f
++#define MATCH_MRTH 0x30600073
++#define MASK_MRTH  0xffffffff
++#define MATCH_MRTS 0x30500073
++#define MASK_MRTS  0xffffffff
++#define MATCH_MUL 0x2000033
++#define MASK_MUL  0xfe00707f
++#define MATCH_MULH 0x2001033
++#define MASK_MULH  0xfe00707f
++#define MATCH_MULHSU 0x2002033
++#define MASK_MULHSU  0xfe00707f
++#define MATCH_MULHU 0x2003033
++#define MASK_MULHU  0xfe00707f
++#define MATCH_MULW 0x200003b
++#define MASK_MULW  0xfe00707f
++#define MATCH_OR 0x6033
++#define MASK_OR  0xfe00707f
++#define MATCH_ORI 0x6013
++#define MASK_ORI  0x707f
++#define MATCH_RDCYCLE 0xc0002073
++#define MASK_RDCYCLE  0xfffff07f
++#define MATCH_RDCYCLEH 0xc8002073
++#define MASK_RDCYCLEH  0xfffff07f
++#define MATCH_RDINSTRET 0xc0202073
++#define MASK_RDINSTRET  0xfffff07f
++#define MATCH_RDINSTRETH 0xc8202073
++#define MASK_RDINSTRETH  0xfffff07f
++#define MATCH_RDTIME 0xc0102073
++#define MASK_RDTIME  0xfffff07f
++#define MATCH_RDTIMEH 0xc8102073
++#define MASK_RDTIMEH  0xfffff07f
++#define MATCH_REM 0x2006033
++#define MASK_REM  0xfe00707f
++#define MATCH_REMU 0x2007033
++#define MASK_REMU  0xfe00707f
++#define MATCH_REMUW 0x200703b
++#define MASK_REMUW  0xfe00707f
++#define MATCH_REMW 0x200603b
++#define MASK_REMW  0xfe00707f
++#define MATCH_SB 0x23
++#define MASK_SB  0x707f
++#define MATCH_SBREAK 0x100073
++#define MASK_SBREAK  0xffffffff
++#define MATCH_SC_D 0x1800302f
++#define MASK_SC_D  0xf800707f
++#define MATCH_SC_W 0x1800202f
++#define MASK_SC_W  0xf800707f
++#define MATCH_SCALL 0x73
++#define MASK_SCALL  0xffffffff
++#define MATCH_SD 0x3023
++#define MASK_SD  0x707f
++#define MATCH_SFENCE_VM 0x10100073
++#define MASK_SFENCE_VM  0xfff07fff
++#define MATCH_SH 0x1023
++#define MASK_SH  0x707f
++#define MATCH_SLL 0x1033
++#define MASK_SLL  0xfe00707f
++#define MATCH_SLLI 0x1013
++#define MASK_SLLI  0xfc00707f
++#define MATCH_SLLI_RV32 0x1013
++#define MASK_SLLI_RV32  0xfe00707f
++#define MATCH_SLLIW 0x101b
++#define MASK_SLLIW  0xfe00707f
++#define MATCH_SLLW 0x103b
++#define MASK_SLLW  0xfe00707f
++#define MATCH_SLT 0x2033
++#define MASK_SLT  0xfe00707f
++#define MATCH_SLTI 0x2013
++#define MASK_SLTI  0x707f
++#define MATCH_SLTIU 0x3013
++#define MASK_SLTIU  0x707f
++#define MATCH_SLTU 0x3033
++#define MASK_SLTU  0xfe00707f
++#define MATCH_SRA 0x40005033
++#define MASK_SRA  0xfe00707f
++#define MATCH_SRAI 0x40005013
++#define MASK_SRAI  0xfc00707f
++#define MATCH_SRAI_RV32 0x40005013
++#define MASK_SRAI_RV32  0xfe00707f
++#define MATCH_SRAIW 0x4000501b
++#define MASK_SRAIW  0xfe00707f
++#define MATCH_SRAW 0x4000503b
++#define MASK_SRAW  0xfe00707f
++#define MATCH_SRET 0x10000073
++#define MASK_SRET  0xffffffff
++#define MATCH_SRL 0x5033
++#define MASK_SRL  0xfe00707f
++#define MATCH_SRLI 0x5013
++#define MASK_SRLI  0xfc00707f
++#define MATCH_SRLI_RV32 0x5013
++#define MASK_SRLI_RV32  0xfe00707f
++#define MATCH_SRLIW 0x501b
++#define MASK_SRLIW  0xfe00707f
++#define MATCH_SRLW 0x503b
++#define MASK_SRLW  0xfe00707f
++#define MATCH_STOP 0x5077
++#define MASK_STOP  0xffffffff
++#define MATCH_SUB 0x40000033
++#define MASK_SUB  0xfe00707f
++#define MATCH_SUBW 0x4000003b
++#define MASK_SUBW  0xfe00707f
++#define MATCH_SW 0x2023
++#define MASK_SW  0x707f
++#define MATCH_UTIDX 0x6077
++#define MASK_UTIDX  0xfffff07f
++#define MATCH_VENQCMD 0xa00302b
++#define MASK_VENQCMD  0xfe007fff
++#define MATCH_VENQCNT 0x1000302b
++#define MASK_VENQCNT  0xfe007fff
++#define MATCH_VENQIMM1 0xc00302b
++#define MASK_VENQIMM1  0xfe007fff
++#define MATCH_VENQIMM2 0xe00302b
++#define MASK_VENQIMM2  0xfe007fff
++#define MATCH_VF 0x10202b
++#define MASK_VF  0x1f0707f
++#define MATCH_VFLD 0x1600205b
++#define MASK_VFLD  0xfff0707f
++#define MATCH_VFLSEGD 0x1600205b
++#define MASK_VFLSEGD  0x1ff0707f
++#define MATCH_VFLSEGSTD 0x1600305b
++#define MASK_VFLSEGSTD  0x1e00707f
++#define MATCH_VFLSEGSTW 0x1400305b
++#define MASK_VFLSEGSTW  0x1e00707f
++#define MATCH_VFLSEGW 0x1400205b
++#define MASK_VFLSEGW  0x1ff0707f
++#define MATCH_VFLSTD 0x1600305b
++#define MASK_VFLSTD  0xfe00707f
++#define MATCH_VFLSTW 0x1400305b
++#define MASK_VFLSTW  0xfe00707f
++#define MATCH_VFLW 0x1400205b
++#define MASK_VFLW  0xfff0707f
++#define MATCH_VFMSV_D 0x1200202b
++#define MASK_VFMSV_D  0xfff0707f
++#define MATCH_VFMSV_S 0x1000202b
++#define MASK_VFMSV_S  0xfff0707f
++#define MATCH_VFMVV 0x1000002b
++#define MASK_VFMVV  0xfff0707f
++#define MATCH_VFSD 0x1600207b
++#define MASK_VFSD  0xfff0707f
++#define MATCH_VFSSEGD 0x1600207b
++#define MASK_VFSSEGD  0x1ff0707f
++#define MATCH_VFSSEGSTD 0x1600307b
++#define MASK_VFSSEGSTD  0x1e00707f
++#define MATCH_VFSSEGSTW 0x1400307b
++#define MASK_VFSSEGSTW  0x1e00707f
++#define MATCH_VFSSEGW 0x1400207b
++#define MASK_VFSSEGW  0x1ff0707f
++#define MATCH_VFSSTD 0x1600307b
++#define MASK_VFSSTD  0xfe00707f
++#define MATCH_VFSSTW 0x1400307b
++#define MASK_VFSSTW  0xfe00707f
++#define MATCH_VFSW 0x1400207b
++#define MASK_VFSW  0xfff0707f
++#define MATCH_VGETCFG 0x400b
++#define MASK_VGETCFG  0xfffff07f
++#define MATCH_VGETVL 0x200400b
++#define MASK_VGETVL  0xfffff07f
++#define MATCH_VLB 0x205b
++#define MASK_VLB  0xfff0707f
++#define MATCH_VLBU 0x800205b
++#define MASK_VLBU  0xfff0707f
++#define MATCH_VLD 0x600205b
++#define MASK_VLD  0xfff0707f
++#define MATCH_VLH 0x200205b
++#define MASK_VLH  0xfff0707f
++#define MATCH_VLHU 0xa00205b
++#define MASK_VLHU  0xfff0707f
++#define MATCH_VLSEGB 0x205b
++#define MASK_VLSEGB  0x1ff0707f
++#define MATCH_VLSEGBU 0x800205b
++#define MASK_VLSEGBU  0x1ff0707f
++#define MATCH_VLSEGD 0x600205b
++#define MASK_VLSEGD  0x1ff0707f
++#define MATCH_VLSEGH 0x200205b
++#define MASK_VLSEGH  0x1ff0707f
++#define MATCH_VLSEGHU 0xa00205b
++#define MASK_VLSEGHU  0x1ff0707f
++#define MATCH_VLSEGSTB 0x305b
++#define MASK_VLSEGSTB  0x1e00707f
++#define MATCH_VLSEGSTBU 0x800305b
++#define MASK_VLSEGSTBU  0x1e00707f
++#define MATCH_VLSEGSTD 0x600305b
++#define MASK_VLSEGSTD  0x1e00707f
++#define MATCH_VLSEGSTH 0x200305b
++#define MASK_VLSEGSTH  0x1e00707f
++#define MATCH_VLSEGSTHU 0xa00305b
++#define MASK_VLSEGSTHU  0x1e00707f
++#define MATCH_VLSEGSTW 0x400305b
++#define MASK_VLSEGSTW  0x1e00707f
++#define MATCH_VLSEGSTWU 0xc00305b
++#define MASK_VLSEGSTWU  0x1e00707f
++#define MATCH_VLSEGW 0x400205b
++#define MASK_VLSEGW  0x1ff0707f
++#define MATCH_VLSEGWU 0xc00205b
++#define MASK_VLSEGWU  0x1ff0707f
++#define MATCH_VLSTB 0x305b
++#define MASK_VLSTB  0xfe00707f
++#define MATCH_VLSTBU 0x800305b
++#define MASK_VLSTBU  0xfe00707f
++#define MATCH_VLSTD 0x600305b
++#define MASK_VLSTD  0xfe00707f
++#define MATCH_VLSTH 0x200305b
++#define MASK_VLSTH  0xfe00707f
++#define MATCH_VLSTHU 0xa00305b
++#define MASK_VLSTHU  0xfe00707f
++#define MATCH_VLSTW 0x400305b
++#define MASK_VLSTW  0xfe00707f
++#define MATCH_VLSTWU 0xc00305b
++#define MASK_VLSTWU  0xfe00707f
++#define MATCH_VLW 0x400205b
++#define MASK_VLW  0xfff0707f
++#define MATCH_VLWU 0xc00205b
++#define MASK_VLWU  0xfff0707f
++#define MATCH_VMSV 0x200202b
++#define MASK_VMSV  0xfff0707f
++#define MATCH_VMVV 0x200002b
++#define MASK_VMVV  0xfff0707f
++#define MATCH_VSB 0x207b
++#define MASK_VSB  0xfff0707f
++#define MATCH_VSD 0x600207b
++#define MASK_VSD  0xfff0707f
++#define MATCH_VSETCFG 0x200b
++#define MASK_VSETCFG  0x7fff
++#define MATCH_VSETVL 0x600b
++#define MASK_VSETVL  0xfff0707f
++#define MATCH_VSH 0x200207b
++#define MASK_VSH  0xfff0707f
++#define MATCH_VSSEGB 0x207b
++#define MASK_VSSEGB  0x1ff0707f
++#define MATCH_VSSEGD 0x600207b
++#define MASK_VSSEGD  0x1ff0707f
++#define MATCH_VSSEGH 0x200207b
++#define MASK_VSSEGH  0x1ff0707f
++#define MATCH_VSSEGSTB 0x307b
++#define MASK_VSSEGSTB  0x1e00707f
++#define MATCH_VSSEGSTD 0x600307b
++#define MASK_VSSEGSTD  0x1e00707f
++#define MATCH_VSSEGSTH 0x200307b
++#define MASK_VSSEGSTH  0x1e00707f
++#define MATCH_VSSEGSTW 0x400307b
++#define MASK_VSSEGSTW  0x1e00707f
++#define MATCH_VSSEGW 0x400207b
++#define MASK_VSSEGW  0x1ff0707f
++#define MATCH_VSSTB 0x307b
++#define MASK_VSSTB  0xfe00707f
++#define MATCH_VSSTD 0x600307b
++#define MASK_VSSTD  0xfe00707f
++#define MATCH_VSSTH 0x200307b
++#define MASK_VSSTH  0xfe00707f
++#define MATCH_VSSTW 0x400307b
++#define MASK_VSSTW  0xfe00707f
++#define MATCH_VSW 0x400207b
++#define MASK_VSW  0xfff0707f
++#define MATCH_VXCPTAUX 0x200402b
++#define MASK_VXCPTAUX  0xfffff07f
++#define MATCH_VXCPTCAUSE 0x402b
++#define MASK_VXCPTCAUSE  0xfffff07f
++#define MATCH_VXCPTEVAC 0x600302b
++#define MASK_VXCPTEVAC  0xfff07fff
++#define MATCH_VXCPTHOLD 0x800302b
++#define MASK_VXCPTHOLD  0xfff07fff
++#define MATCH_VXCPTKILL 0x400302b
++#define MASK_VXCPTKILL  0xffffffff
++#define MATCH_VXCPTRESTORE 0x200302b
++#define MASK_VXCPTRESTORE  0xfff07fff
++#define MATCH_VXCPTSAVE 0x302b
++#define MASK_VXCPTSAVE  0xfff07fff
++#define MATCH_WFI 0x10200073
++#define MASK_WFI  0xffffffff
++#define MATCH_XOR 0x4033
++#define MASK_XOR  0xfe00707f
++#define MATCH_XORI 0x4013
++#define MASK_XORI  0x707f
++#define CSR_FFLAGS 0x1
++#define CSR_FRM 0x2
++#define CSR_FCSR 0x3
++#define CSR_CYCLE 0xc00
++#define CSR_TIME 0xc01
++#define CSR_INSTRET 0xc02
++#define CSR_STATS 0xc0
++#define CSR_UARCH0 0xcc0
++#define CSR_UARCH1 0xcc1
++#define CSR_UARCH2 0xcc2
++#define CSR_UARCH3 0xcc3
++#define CSR_UARCH4 0xcc4
++#define CSR_UARCH5 0xcc5
++#define CSR_UARCH6 0xcc6
++#define CSR_UARCH7 0xcc7
++#define CSR_UARCH8 0xcc8
++#define CSR_UARCH9 0xcc9
++#define CSR_UARCH10 0xcca
++#define CSR_UARCH11 0xccb
++#define CSR_UARCH12 0xccc
++#define CSR_UARCH13 0xccd
++#define CSR_UARCH14 0xcce
++#define CSR_UARCH15 0xccf
++#define CSR_SSTATUS 0x100
++#define CSR_STVEC 0x101
++#define CSR_SIE 0x104
++#define CSR_SSCRATCH 0x140
++#define CSR_SEPC 0x141
++#define CSR_SIP 0x144
++#define CSR_SPTBR 0x180
++#define CSR_SASID 0x181
++#define CSR_CYCLEW 0x900
++#define CSR_TIMEW 0x901
++#define CSR_INSTRETW 0x902
++#define CSR_STIME 0xd01
++#define CSR_SCAUSE 0xd42
++#define CSR_SBADADDR 0xd43
++#define CSR_STIMEW 0xa01
++#define CSR_MSTATUS 0x300
++#define CSR_MTVEC 0x301
++#define CSR_MTDELEG 0x302
++#define CSR_MIE 0x304
++#define CSR_MTIMECMP 0x321
++#define CSR_MSCRATCH 0x340
++#define CSR_MEPC 0x341
++#define CSR_MCAUSE 0x342
++#define CSR_MBADADDR 0x343
++#define CSR_MIP 0x344
++#define CSR_MTIME 0x701
++#define CSR_MCPUID 0xf00
++#define CSR_MIMPID 0xf01
++#define CSR_MHARTID 0xf10
++#define CSR_MTOHOST 0x780
++#define CSR_MFROMHOST 0x781
++#define CSR_MRESET 0x782
++#define CSR_SEND_IPI 0x783
++#define CSR_CYCLEH 0xc80
++#define CSR_TIMEH 0xc81
++#define CSR_INSTRETH 0xc82
++#define CSR_CYCLEHW 0x980
++#define CSR_TIMEHW 0x981
++#define CSR_INSTRETHW 0x982
++#define CSR_STIMEH 0xd81
++#define CSR_STIMEHW 0xa81
++#define CSR_MTIMECMPH 0x361
++#define CSR_MTIMEH 0x741
++#define CAUSE_MISALIGNED_FETCH 0x0
++#define CAUSE_FAULT_FETCH 0x1
++#define CAUSE_ILLEGAL_INSTRUCTION 0x2
++#define CAUSE_BREAKPOINT 0x3
++#define CAUSE_MISALIGNED_LOAD 0x4
++#define CAUSE_FAULT_LOAD 0x5
++#define CAUSE_MISALIGNED_STORE 0x6
++#define CAUSE_FAULT_STORE 0x7
++#define CAUSE_USER_ECALL 0x8
++#define CAUSE_SUPERVISOR_ECALL 0x9
++#define CAUSE_HYPERVISOR_ECALL 0xa
++#define CAUSE_MACHINE_ECALL 0xb
++#endif
++#ifdef DECLARE_INSN
++DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
++DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
++DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
++DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
++DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
++DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
++DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
++DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
++DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
++DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
++DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
++DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
++DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
++DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
++DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
++DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
++DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
++DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
++DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
++DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
++DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
++DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
++DECLARE_INSN(and, MATCH_AND, MASK_AND)
++DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
++DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
++DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
++DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
++DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
++DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
++DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
++DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
++DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
++DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
++DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
++DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
++DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
++DECLARE_INSN(c_addin, MATCH_C_ADDIN, MASK_C_ADDIN)
++DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
++DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
++DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
++DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
++DECLARE_INSN(c_andin, MATCH_C_ANDIN, MASK_C_ANDIN)
++DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
++DECLARE_INSN(c_bgez, MATCH_C_BGEZ, MASK_C_BGEZ)
++DECLARE_INSN(c_bltz, MATCH_C_BLTZ, MASK_C_BLTZ)
++DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
++DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
++DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
++DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
++DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
++DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
++DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
++DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
++DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
++DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
++DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
++DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
++DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
++DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
++DECLARE_INSN(c_orin, MATCH_C_ORIN, MASK_C_ORIN)
++DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
++DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
++DECLARE_INSN(c_sll, MATCH_C_SLL, MASK_C_SLL)
++DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
++DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
++DECLARE_INSN(c_sllr, MATCH_C_SLLR, MASK_C_SLLR)
++DECLARE_INSN(c_slt, MATCH_C_SLT, MASK_C_SLT)
++DECLARE_INSN(c_sltr, MATCH_C_SLTR, MASK_C_SLTR)
++DECLARE_INSN(c_sltu, MATCH_C_SLTU, MASK_C_SLTU)
++DECLARE_INSN(c_sltur, MATCH_C_SLTUR, MASK_C_SLTUR)
++DECLARE_INSN(c_sra, MATCH_C_SRA, MASK_C_SRA)
++DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
++DECLARE_INSN(c_srl, MATCH_C_SRL, MASK_C_SRL)
++DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
++DECLARE_INSN(c_srlr, MATCH_C_SRLR, MASK_C_SRLR)
++DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
++DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
++DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
++DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
++DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
++DECLARE_INSN(c_xorin, MATCH_C_XORIN, MASK_C_XORIN)
++DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
++DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
++DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
++DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
++DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
++DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
++DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
++DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
++DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
++DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
++DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
++DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
++DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
++DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
++DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
++DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
++DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
++DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
++DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
++DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
++DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
++DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
++DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
++DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
++DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
++DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
++DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
++DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
++DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
++DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
++DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
++DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
++DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
++DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
++DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
++DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
++DECLARE_INSN(eret, MATCH_ERET, MASK_ERET)
++DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
++DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
++DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
++DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
++DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
++DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
++DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
++DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
++DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
++DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
++DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
++DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
++DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
++DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
++DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
++DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
++DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
++DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
++DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
++DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
++DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
++DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
++DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
++DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
++DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
++DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
++DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
++DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
++DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
++DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
++DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
++DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
++DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
++DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
++DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
++DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
++DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
++DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
++DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
++DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
++DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
++DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
++DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
++DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
++DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
++DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
++DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
++DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
++DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
++DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
++DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
++DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
++DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
++DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
++DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
++DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
++DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
++DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
++DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
++DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
++DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
++DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
++DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
++DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
++DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
++DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
++DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
++DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
++DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
++DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
++DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
++DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
++DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
++DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
++DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
++DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
++DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
++DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
++DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
++DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
++DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
++DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
++DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
++DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
++DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
++DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
++DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
++DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
++DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
++DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
++DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
++DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
++DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
++DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
++DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
++DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
++DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
++DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
++DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
++DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
++DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
++DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
++DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
++DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
++DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
++DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
++DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
++DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS)
++DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
++DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
++DECLARE_INSN(lb, MATCH_LB, MASK_LB)
++DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
++DECLARE_INSN(ld, MATCH_LD, MASK_LD)
++DECLARE_INSN(lh, MATCH_LH, MASK_LH)
++DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
++DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
++DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
++DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
++DECLARE_INSN(lw, MATCH_LW, MASK_LW)
++DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
++DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
++DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
++DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH)
++DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS)
++DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
++DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
++DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
++DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
++DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
++DECLARE_INSN(or, MATCH_OR, MASK_OR)
++DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
++DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
++DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
++DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
++DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
++DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
++DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
++DECLARE_INSN(rem, MATCH_REM, MASK_REM)
++DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
++DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
++DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
++DECLARE_INSN(sb, MATCH_SB, MASK_SB)
++DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
++DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
++DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
++DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
++DECLARE_INSN(sd, MATCH_SD, MASK_SD)
++DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
++DECLARE_INSN(sh, MATCH_SH, MASK_SH)
++DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
++DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
++DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
++DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
++DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
++DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
++DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
++DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
++DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
++DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
++DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
++DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
++DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
++DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
++DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
++DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
++DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
++DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
++DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
++DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
++DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
++DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
++DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
++DECLARE_INSN(sw, MATCH_SW, MASK_SW)
++DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
++DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
++DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
++DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
++DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
++DECLARE_INSN(vf, MATCH_VF, MASK_VF)
++DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
++DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
++DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
++DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
++DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
++DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
++DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
++DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
++DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
++DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
++DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
++DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
++DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
++DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
++DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
++DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
++DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
++DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
++DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
++DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
++DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
++DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
++DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
++DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
++DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
++DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
++DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
++DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
++DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
++DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
++DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
++DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
++DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
++DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
++DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
++DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
++DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
++DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
++DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
++DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
++DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
++DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
++DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
++DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
++DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
++DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
++DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
++DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
++DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
++DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
++DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
++DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
++DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
++DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
++DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
++DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
++DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
++DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
++DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
++DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
++DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
++DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
++DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
++DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
++DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
++DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
++DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
++DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
++DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
++DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
++DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
++DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
++DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
++DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
++DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
++DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
++DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
++DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
++DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
++#endif
++#ifdef DECLARE_CSR
++DECLARE_CSR(fflags, CSR_FFLAGS)
++DECLARE_CSR(frm, CSR_FRM)
++DECLARE_CSR(fcsr, CSR_FCSR)
++DECLARE_CSR(cycle, CSR_CYCLE)
++DECLARE_CSR(time, CSR_TIME)
++DECLARE_CSR(instret, CSR_INSTRET)
++DECLARE_CSR(stats, CSR_STATS)
++DECLARE_CSR(uarch0, CSR_UARCH0)
++DECLARE_CSR(uarch1, CSR_UARCH1)
++DECLARE_CSR(uarch2, CSR_UARCH2)
++DECLARE_CSR(uarch3, CSR_UARCH3)
++DECLARE_CSR(uarch4, CSR_UARCH4)
++DECLARE_CSR(uarch5, CSR_UARCH5)
++DECLARE_CSR(uarch6, CSR_UARCH6)
++DECLARE_CSR(uarch7, CSR_UARCH7)
++DECLARE_CSR(uarch8, CSR_UARCH8)
++DECLARE_CSR(uarch9, CSR_UARCH9)
++DECLARE_CSR(uarch10, CSR_UARCH10)
++DECLARE_CSR(uarch11, CSR_UARCH11)
++DECLARE_CSR(uarch12, CSR_UARCH12)
++DECLARE_CSR(uarch13, CSR_UARCH13)
++DECLARE_CSR(uarch14, CSR_UARCH14)
++DECLARE_CSR(uarch15, CSR_UARCH15)
++DECLARE_CSR(sstatus, CSR_SSTATUS)
++DECLARE_CSR(stvec, CSR_STVEC)
++DECLARE_CSR(sie, CSR_SIE)
++DECLARE_CSR(sscratch, CSR_SSCRATCH)
++DECLARE_CSR(sepc, CSR_SEPC)
++DECLARE_CSR(sip, CSR_SIP)
++DECLARE_CSR(sptbr, CSR_SPTBR)
++DECLARE_CSR(sasid, CSR_SASID)
++DECLARE_CSR(cyclew, CSR_CYCLEW)
++DECLARE_CSR(timew, CSR_TIMEW)
++DECLARE_CSR(instretw, CSR_INSTRETW)
++DECLARE_CSR(stime, CSR_STIME)
++DECLARE_CSR(scause, CSR_SCAUSE)
++DECLARE_CSR(sbadaddr, CSR_SBADADDR)
++DECLARE_CSR(stimew, CSR_STIMEW)
++DECLARE_CSR(mstatus, CSR_MSTATUS)
++DECLARE_CSR(mtvec, CSR_MTVEC)
++DECLARE_CSR(mtdeleg, CSR_MTDELEG)
++DECLARE_CSR(mie, CSR_MIE)
++DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
++DECLARE_CSR(mscratch, CSR_MSCRATCH)
++DECLARE_CSR(mepc, CSR_MEPC)
++DECLARE_CSR(mcause, CSR_MCAUSE)
++DECLARE_CSR(mbadaddr, CSR_MBADADDR)
++DECLARE_CSR(mip, CSR_MIP)
++DECLARE_CSR(mtime, CSR_MTIME)
++DECLARE_CSR(mcpuid, CSR_MCPUID)
++DECLARE_CSR(mimpid, CSR_MIMPID)
++DECLARE_CSR(mhartid, CSR_MHARTID)
++DECLARE_CSR(mtohost, CSR_MTOHOST)
++DECLARE_CSR(mfromhost, CSR_MFROMHOST)
++DECLARE_CSR(mreset, CSR_MRESET)
++DECLARE_CSR(send_ipi, CSR_SEND_IPI)
++DECLARE_CSR(cycleh, CSR_CYCLEH)
++DECLARE_CSR(timeh, CSR_TIMEH)
++DECLARE_CSR(instreth, CSR_INSTRETH)
++DECLARE_CSR(cyclehw, CSR_CYCLEHW)
++DECLARE_CSR(timehw, CSR_TIMEHW)
++DECLARE_CSR(instrethw, CSR_INSTRETHW)
++DECLARE_CSR(stimeh, CSR_STIMEH)
++DECLARE_CSR(stimehw, CSR_STIMEHW)
++DECLARE_CSR(mtimecmph, CSR_MTIMECMPH)
++DECLARE_CSR(mtimeh, CSR_MTIMEH)
++#endif
++#ifdef DECLARE_CAUSE
++DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
++DECLARE_CAUSE("frm", CAUSE_FRM)
++DECLARE_CAUSE("fcsr", CAUSE_FCSR)
++DECLARE_CAUSE("cycle", CAUSE_CYCLE)
++DECLARE_CAUSE("time", CAUSE_TIME)
++DECLARE_CAUSE("instret", CAUSE_INSTRET)
++DECLARE_CAUSE("stats", CAUSE_STATS)
++DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
++DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
++DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
++DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
++DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
++DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
++DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
++DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
++DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
++DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
++DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
++DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
++DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
++DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
++DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
++DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
++DECLARE_CAUSE("sstatus", CAUSE_SSTATUS)
++DECLARE_CAUSE("stvec", CAUSE_STVEC)
++DECLARE_CAUSE("sie", CAUSE_SIE)
++DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH)
++DECLARE_CAUSE("sepc", CAUSE_SEPC)
++DECLARE_CAUSE("sip", CAUSE_SIP)
++DECLARE_CAUSE("sptbr", CAUSE_SPTBR)
++DECLARE_CAUSE("sasid", CAUSE_SASID)
++DECLARE_CAUSE("cyclew", CAUSE_CYCLEW)
++DECLARE_CAUSE("timew", CAUSE_TIMEW)
++DECLARE_CAUSE("instretw", CAUSE_INSTRETW)
++DECLARE_CAUSE("stime", CAUSE_STIME)
++DECLARE_CAUSE("scause", CAUSE_SCAUSE)
++DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR)
++DECLARE_CAUSE("stimew", CAUSE_STIMEW)
++DECLARE_CAUSE("mstatus", CAUSE_MSTATUS)
++DECLARE_CAUSE("mtvec", CAUSE_MTVEC)
++DECLARE_CAUSE("mtdeleg", CAUSE_MTDELEG)
++DECLARE_CAUSE("mie", CAUSE_MIE)
++DECLARE_CAUSE("mtimecmp", CAUSE_MTIMECMP)
++DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH)
++DECLARE_CAUSE("mepc", CAUSE_MEPC)
++DECLARE_CAUSE("mcause", CAUSE_MCAUSE)
++DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR)
++DECLARE_CAUSE("mip", CAUSE_MIP)
++DECLARE_CAUSE("mtime", CAUSE_MTIME)
++DECLARE_CAUSE("mcpuid", CAUSE_MCPUID)
++DECLARE_CAUSE("mimpid", CAUSE_MIMPID)
++DECLARE_CAUSE("mhartid", CAUSE_MHARTID)
++DECLARE_CAUSE("mtohost", CAUSE_MTOHOST)
++DECLARE_CAUSE("mfromhost", CAUSE_MFROMHOST)
++DECLARE_CAUSE("mreset", CAUSE_MRESET)
++DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
++DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
++DECLARE_CAUSE("timeh", CAUSE_TIMEH)
++DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
++DECLARE_CAUSE("cyclehw", CAUSE_CYCLEHW)
++DECLARE_CAUSE("timehw", CAUSE_TIMEHW)
++DECLARE_CAUSE("instrethw", CAUSE_INSTRETHW)
++DECLARE_CAUSE("stimeh", CAUSE_STIMEH)
++DECLARE_CAUSE("stimehw", CAUSE_STIMEHW)
++DECLARE_CAUSE("mtimecmph", CAUSE_MTIMECMPH)
++DECLARE_CAUSE("mtimeh", CAUSE_MTIMEH)
++#endif
+diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
+--- empty/include/opcode/riscv.h	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/include/opcode/riscv.h	2015-07-18 00:02:36.222287541 +0200
+@@ -0,0 +1,366 @@
 +/* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
 +   Copyright 2011
 +   Free Software Foundation, Inc.
@@ -6726,26 +8015,14 @@
 +
 +/* RVC fields */
 +
-+#define OP_MASK_CRD		0x1f
-+#define OP_SH_CRD		5
-+#define OP_MASK_CRS2	0x1f
-+#define OP_SH_CRS2	5
-+#define OP_MASK_CRS1	0x1f
-+#define OP_SH_CRS1	10
-+#define OP_MASK_CRDS		0x7
-+#define OP_SH_CRDS		13
-+#define OP_MASK_CRS2S	0x7
-+#define OP_SH_CRS2S	13
-+#define OP_MASK_CRS2BS	0x7
-+#define OP_SH_CRS2BS	5
-+#define OP_MASK_CRS1S	0x7
-+#define OP_SH_CRS1S	10
-+#define OP_MASK_CIMM6	0x3f
-+#define OP_SH_CIMM6	10
-+#define OP_MASK_CIMM5	0x1f
-+#define OP_SH_CIMM5	5
-+#define OP_MASK_CIMM10	0x3ff
-+#define OP_SH_CIMM10	5
++#define OP_MASK_CRS2 0x1f
++#define OP_SH_CRS2 2
++#define OP_MASK_CRS1S 0x7
++#define OP_SH_CRS1S 7
++#define OP_MASK_CRS2S 0x7
++#define OP_SH_CRS2S 2
++#define OP_MASK_CRDS 0x7
++#define OP_SH_CRDS 10
 +
 +static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
 +#define rvc_rd_regmap rvc_rs1_regmap
@@ -6776,15 +8053,11 @@
 +  "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw",
 +};
 +
-+#define RVC_JUMP_BITS 10
-+#define RVC_JUMP_ALIGN_BITS 1
-+#define RVC_JUMP_ALIGN (1 << RVC_JUMP_ALIGN_BITS)
-+#define RVC_JUMP_REACH ((1ULL<<RVC_JUMP_BITS)*RVC_JUMP_ALIGN)
++#define RVC_JUMP_BITS 11
++#define RVC_JUMP_REACH ((1ULL<<RVC_JUMP_BITS)*RISCV_JUMP_ALIGN)
 +
-+#define RVC_BRANCH_BITS 5
-+#define RVC_BRANCH_ALIGN_BITS RVC_JUMP_ALIGN_BITS
-+#define RVC_BRANCH_ALIGN (1 << RVC_BRANCH_ALIGN_BITS)
-+#define RVC_BRANCH_REACH ((1ULL<<RVC_BRANCH_BITS)*RVC_BRANCH_ALIGN)
++#define RVC_BRANCH_BITS 8
++#define RVC_BRANCH_REACH ((1ULL<<RVC_BRANCH_BITS)*RISCV_BRANCH_ALIGN)
 +
 +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
 +#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
@@ -6799,6 +8072,30 @@
 +  ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
 +#define EXTRACT_UJTYPE_IMM(x) \
 +  ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
++#define EXTRACT_RVC_IMM(x) \
++  (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
++#define EXTRACT_RVC_SIMM3(x) \
++  (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
++#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
++  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
++#define EXTRACT_RVC_ADDI16SP_IMM(x) \
++  ((RV_X(x, 6, 1) << 4) | (RV_X(x, 5, 1) << 5) | (RV_X(x, 2, 3) << 6) | (-RV_X(x, 12, 1) << 9))
++#define EXTRACT_RVC_LW_IMM(x) \
++  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
++#define EXTRACT_RVC_LD_IMM(x) \
++  ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
++#define EXTRACT_RVC_LWSP_IMM(x) \
++  ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
++#define EXTRACT_RVC_LDSP_IMM(x) \
++  ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
++#define EXTRACT_RVC_SWSP_IMM(x) \
++  ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
++#define EXTRACT_RVC_SDSP_IMM(x) \
++  ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
++#define EXTRACT_RVC_B_IMM(x) \
++  ((RV_X(x, 3, 4) << 1) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 10, 2) << 6) | (-RV_X(x, 12, 1) << 8))
++#define EXTRACT_RVC_J_IMM(x) \
++  ((RV_X(x, 3, 4) << 1) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 5) << 6) | (-RV_X(x, 12, 1) << 11))
 +
 +#define ENCODE_ITYPE_IMM(x) \
 +  (RV_X(x, 0, 12) << 20)
@@ -6810,12 +8107,48 @@
 +  (RV_X(x, 12, 20) << 12)
 +#define ENCODE_UJTYPE_IMM(x) \
 +  ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
++#define ENCODE_RVC_IMM(x) \
++  ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
++#define ENCODE_RVC_SIMM3(x) \
++  (RV_X(x, 0, 3) << 10)
++#define ENCODE_RVC_ADDI4SPN_IMM(x) \
++  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
++#define ENCODE_RVC_ADDI16SP_IMM(x) \
++  ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 5) | (RV_X(x, 6, 3) << 2) | (RV_X(x, 9, 1) << 12))
++#define ENCODE_RVC_LW_IMM(x) \
++  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
++#define ENCODE_RVC_LD_IMM(x) \
++  ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
++#define ENCODE_RVC_LWSP_IMM(x) \
++  ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
++#define ENCODE_RVC_LDSP_IMM(x) \
++  ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
++#define ENCODE_RVC_SWSP_IMM(x) \
++  ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
++#define ENCODE_RVC_SDSP_IMM(x) \
++  ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
++#define ENCODE_RVC_B_IMM(x) \
++  ((RV_X(x, 1, 4) << 3) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 3) << 10))
++#define ENCODE_RVC_J_IMM(x) \
++  ((RV_X(x, 1, 4) << 3) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 6) << 7))
 +
 +#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 +#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
 +#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
 +#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
 +#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
++#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
++#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
++#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
++#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
++#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
++#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
++#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
++#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
++#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
++#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
++#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
++#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
 +
 +#define RISCV_RTYPE(insn, rd, rs1, rs2) \
 +  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
@@ -6831,6 +8164,7 @@
 +  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
 +
 +#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
++#define RVC_NOP MATCH_C_ADDI
 +
 +#define RISCV_CONST_HIGH_PART(VALUE) \
 +  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
@@ -6917,6 +8251,7 @@
 +#define RISCV_BIGIMM_BITS (32-RISCV_IMM_BITS)
 +#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
 +#define RISCV_BIGIMM_REACH (1LL<<RISCV_BIGIMM_BITS)
++#define RISCV_RVC_IMM_REACH (1LL<<6)
 +#define RISCV_BRANCH_BITS RISCV_IMM_BITS
 +#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
 +#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
@@ -7016,1245 +8351,9 @@
 +#define NUMOPCODES bfd_riscv_num_opcodes
 +
 +#endif /* _RISCV_H_ */
-diff -urN original-binutils/include/opcode/riscv-opc.h binutils/include/opcode/riscv-opc.h
---- original-binutils/include/opcode/riscv-opc.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/include/opcode/riscv-opc.h	2015-03-07 09:51:45.659139025 +0100
-@@ -0,0 +1,1216 @@
-+/* Automatically generated by parse-opcodes */
-+#ifndef RISCV_ENCODING_H
-+#define RISCV_ENCODING_H
-+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
-+#define MATCH_VLSEGSTWU 0xc00305b
-+#define MASK_VLSEGSTWU  0x1e00707f
-+#define MATCH_C_LW0 0x12
-+#define MASK_C_LW0  0x801f
-+#define MATCH_FMV_D_X 0xf2000053
-+#define MASK_FMV_D_X  0xfff0707f
-+#define MATCH_VLH 0x200205b
-+#define MASK_VLH  0xfff0707f
-+#define MATCH_C_LI 0x0
-+#define MASK_C_LI  0x1f
-+#define MATCH_FADD_D 0x2000053
-+#define MASK_FADD_D  0xfe00007f
-+#define MATCH_C_LD 0x9
-+#define MASK_C_LD  0x1f
-+#define MATCH_VLD 0x600205b
-+#define MASK_VLD  0xfff0707f
-+#define MATCH_FADD_S 0x53
-+#define MASK_FADD_S  0xfe00007f
-+#define MATCH_C_LW 0xa
-+#define MASK_C_LW  0x1f
-+#define MATCH_VLW 0x400205b
-+#define MASK_VLW  0xfff0707f
-+#define MATCH_VSSEGSTW 0x400307b
-+#define MASK_VSSEGSTW  0x1e00707f
-+#define MATCH_UTIDX 0x6077
-+#define MASK_UTIDX  0xfffff07f
-+#define MATCH_C_FLW 0x14
-+#define MASK_C_FLW  0x1f
-+#define MATCH_FSUB_D 0xa000053
-+#define MASK_FSUB_D  0xfe00007f
-+#define MATCH_VSSEGSTD 0x600307b
-+#define MASK_VSSEGSTD  0x1e00707f
-+#define MATCH_VSSEGSTB 0x307b
-+#define MASK_VSSEGSTB  0x1e00707f
-+#define MATCH_DIV 0x2004033
-+#define MASK_DIV  0xfe00707f
-+#define MATCH_FMV_H_X 0xf4000053
-+#define MASK_FMV_H_X  0xfff0707f
-+#define MATCH_C_FLD 0x15
-+#define MASK_C_FLD  0x1f
-+#define MATCH_FRRM 0x202073
-+#define MASK_FRRM  0xfffff07f
-+#define MATCH_VFMSV_S 0x1000202b
-+#define MASK_VFMSV_S  0xfff0707f
-+#define MATCH_C_LWSP 0x5
-+#define MASK_C_LWSP  0x1f
-+#define MATCH_FENCE 0xf
-+#define MASK_FENCE  0x707f
-+#define MATCH_FNMSUB_S 0x4b
-+#define MASK_FNMSUB_S  0x600007f
-+#define MATCH_FLE_S 0xa0000053
-+#define MASK_FLE_S  0xfe00707f
-+#define MATCH_FNMSUB_H 0x400004b
-+#define MASK_FNMSUB_H  0x600007f
-+#define MATCH_FLE_H 0xbc000053
-+#define MASK_FLE_H  0xfe00707f
-+#define MATCH_FLW 0x2007
-+#define MASK_FLW  0x707f
-+#define MATCH_VSETVL 0x600b
-+#define MASK_VSETVL  0xfff0707f
-+#define MATCH_VFMSV_D 0x1200202b
-+#define MASK_VFMSV_D  0xfff0707f
-+#define MATCH_FLE_D 0xa2000053
-+#define MASK_FLE_D  0xfe00707f
-+#define MATCH_FENCE_I 0x100f
-+#define MASK_FENCE_I  0x707f
-+#define MATCH_FNMSUB_D 0x200004b
-+#define MASK_FNMSUB_D  0x600007f
-+#define MATCH_ADDW 0x3b
-+#define MASK_ADDW  0xfe00707f
-+#define MATCH_XOR 0x4033
-+#define MASK_XOR  0xfe00707f
-+#define MATCH_SUB 0x40000033
-+#define MASK_SUB  0xfe00707f
-+#define MATCH_VSSTW 0x400307b
-+#define MASK_VSSTW  0xfe00707f
-+#define MATCH_VSSTH 0x200307b
-+#define MASK_VSSTH  0xfe00707f
-+#define MATCH_SC_W 0x1800202f
-+#define MASK_SC_W  0xf800707f
-+#define MATCH_VSSTB 0x307b
-+#define MASK_VSSTB  0xfe00707f
-+#define MATCH_VSSTD 0x600307b
-+#define MASK_VSSTD  0xfe00707f
-+#define MATCH_ADDI 0x13
-+#define MASK_ADDI  0x707f
-+#define MATCH_RDTIMEH 0xc8102073
-+#define MASK_RDTIMEH  0xfffff07f
-+#define MATCH_MULH 0x2001033
-+#define MASK_MULH  0xfe00707f
-+#define MATCH_CSRRSI 0x6073
-+#define MASK_CSRRSI  0x707f
-+#define MATCH_FCVT_D_WU 0xd2100053
-+#define MASK_FCVT_D_WU  0xfff0007f
-+#define MATCH_MULW 0x200003b
-+#define MASK_MULW  0xfe00707f
-+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
-+#define MATCH_VENQIMM1 0xc00302b
-+#define MASK_VENQIMM1  0xfe007fff
-+#define MATCH_VENQIMM2 0xe00302b
-+#define MASK_VENQIMM2  0xfe007fff
-+#define MATCH_RDINSTRET 0xc0202073
-+#define MASK_RDINSTRET  0xfffff07f
-+#define MATCH_C_SWSP 0x8
-+#define MASK_C_SWSP  0x1f
-+#define MATCH_VLSTW 0x400305b
-+#define MASK_VLSTW  0xfe00707f
-+#define MATCH_VLSTH 0x200305b
-+#define MASK_VLSTH  0xfe00707f
-+#define MATCH_VLSTB 0x305b
-+#define MASK_VLSTB  0xfe00707f
-+#define MATCH_VLSTD 0x600305b
-+#define MASK_VLSTD  0xfe00707f
-+#define MATCH_ANDI 0x7013
-+#define MASK_ANDI  0x707f
-+#define MATCH_FMV_X_S 0xe0000053
-+#define MASK_FMV_X_S  0xfff0707f
-+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
-+#define MATCH_FNMADD_S 0x4f
-+#define MASK_FNMADD_S  0x600007f
-+#define MATCH_LWU 0x6003
-+#define MASK_LWU  0x707f
-+#define MATCH_CUSTOM0_RS1 0x200b
-+#define MASK_CUSTOM0_RS1  0x707f
-+#define MATCH_VLSEGSTBU 0x800305b
-+#define MASK_VLSEGSTBU  0x1e00707f
-+#define MATCH_FNMADD_D 0x200004f
-+#define MASK_FNMADD_D  0x600007f
-+#define MATCH_FCVT_W_S 0xc0000053
-+#define MASK_FCVT_W_S  0xfff0007f
-+#define MATCH_C_SRAI 0x1019
-+#define MASK_C_SRAI  0x1c1f
-+#define MATCH_MULHSU 0x2002033
-+#define MASK_MULHSU  0xfe00707f
-+#define MATCH_FCVT_D_LU 0xd2300053
-+#define MASK_FCVT_D_LU  0xfff0007f
-+#define MATCH_FCVT_W_D 0xc2000053
-+#define MASK_FCVT_W_D  0xfff0007f
-+#define MATCH_FSUB_H 0xc000053
-+#define MASK_FSUB_H  0xfe00007f
-+#define MATCH_DIVUW 0x200503b
-+#define MASK_DIVUW  0xfe00707f
-+#define MATCH_SLTI 0x2013
-+#define MASK_SLTI  0x707f
-+#define MATCH_VLSTBU 0x800305b
-+#define MASK_VLSTBU  0xfe00707f
-+#define MATCH_SLTU 0x3033
-+#define MASK_SLTU  0xfe00707f
-+#define MATCH_FLH 0x1007
-+#define MASK_FLH  0x707f
-+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
-+#define MATCH_FLD 0x3007
-+#define MASK_FLD  0x707f
-+#define MATCH_FSUB_S 0x8000053
-+#define MASK_FSUB_S  0xfe00007f
-+#define MATCH_FCVT_H_LU 0x6c000053
-+#define MASK_FCVT_H_LU  0xfff0007f
-+#define MATCH_CUSTOM0 0xb
-+#define MASK_CUSTOM0  0x707f
-+#define MATCH_CUSTOM1 0x2b
-+#define MASK_CUSTOM1  0x707f
-+#define MATCH_CUSTOM2 0x5b
-+#define MASK_CUSTOM2  0x707f
-+#define MATCH_CUSTOM3 0x7b
-+#define MASK_CUSTOM3  0x707f
-+#define MATCH_VXCPTSAVE 0x302b
-+#define MASK_VXCPTSAVE  0xfff07fff
-+#define MATCH_VMSV 0x200202b
-+#define MASK_VMSV  0xfff0707f
-+#define MATCH_FCVT_LU_S 0xc0300053
-+#define MASK_FCVT_LU_S  0xfff0007f
-+#define MATCH_AUIPC 0x17
-+#define MASK_AUIPC  0x7f
-+#define MATCH_FRFLAGS 0x102073
-+#define MASK_FRFLAGS  0xfffff07f
-+#define MATCH_FCVT_LU_D 0xc2300053
-+#define MASK_FCVT_LU_D  0xfff0007f
-+#define MATCH_CSRRWI 0x5073
-+#define MASK_CSRRWI  0x707f
-+#define MATCH_FADD_H 0x4000053
-+#define MASK_FADD_H  0xfe00007f
-+#define MATCH_FSQRT_S 0x58000053
-+#define MASK_FSQRT_S  0xfff0007f
-+#define MATCH_VXCPTKILL 0x400302b
-+#define MASK_VXCPTKILL  0xffffffff
-+#define MATCH_STOP 0x5077
-+#define MASK_STOP  0xffffffff
-+#define MATCH_FSGNJN_S 0x20001053
-+#define MASK_FSGNJN_S  0xfe00707f
-+#define MATCH_FSGNJN_H 0x34000053
-+#define MASK_FSGNJN_H  0xfe00707f
-+#define MATCH_FSQRT_D 0x5a000053
-+#define MASK_FSQRT_D  0xfff0007f
-+#define MATCH_XORI 0x4013
-+#define MASK_XORI  0x707f
-+#define MATCH_DIVU 0x2005033
-+#define MASK_DIVU  0xfe00707f
-+#define MATCH_FSGNJN_D 0x22001053
-+#define MASK_FSGNJN_D  0xfe00707f
-+#define MATCH_FSQRT_H 0x24000053
-+#define MASK_FSQRT_H  0xfff0007f
-+#define MATCH_VSSEGSTH 0x200307b
-+#define MASK_VSSEGSTH  0x1e00707f
-+#define MATCH_SW 0x2023
-+#define MASK_SW  0x707f
-+#define MATCH_VLSTWU 0xc00305b
-+#define MASK_VLSTWU  0xfe00707f
-+#define MATCH_VFSSEGW 0x1400207b
-+#define MASK_VFSSEGW  0x1ff0707f
-+#define MATCH_LHU 0x5003
-+#define MASK_LHU  0x707f
-+#define MATCH_SH 0x1023
-+#define MASK_SH  0x707f
-+#define MATCH_FMSUB_H 0x4000047
-+#define MASK_FMSUB_H  0x600007f
-+#define MATCH_VXCPTAUX 0x200402b
-+#define MASK_VXCPTAUX  0xfffff07f
-+#define MATCH_FMSUB_D 0x2000047
-+#define MASK_FMSUB_D  0x600007f
-+#define MATCH_VFSSEGD 0x1600207b
-+#define MASK_VFSSEGD  0x1ff0707f
-+#define MATCH_VLSEGHU 0xa00205b
-+#define MASK_VLSEGHU  0x1ff0707f
-+#define MATCH_MOVN 0x2007077
-+#define MASK_MOVN  0xfe00707f
-+#define MATCH_CUSTOM1_RS1 0x202b
-+#define MASK_CUSTOM1_RS1  0x707f
-+#define MATCH_VLSTHU 0xa00305b
-+#define MASK_VLSTHU  0xfe00707f
-+#define MATCH_MOVZ 0x7077
-+#define MASK_MOVZ  0xfe00707f
-+#define MATCH_CSRRW 0x1073
-+#define MASK_CSRRW  0x707f
-+#define MATCH_LD 0x3003
-+#define MASK_LD  0x707f
-+#define MATCH_LB 0x3
-+#define MASK_LB  0x707f
-+#define MATCH_VLWU 0xc00205b
-+#define MASK_VLWU  0xfff0707f
-+#define MATCH_LH 0x1003
-+#define MASK_LH  0x707f
-+#define MATCH_LW 0x2003
-+#define MASK_LW  0x707f
-+#define MATCH_CSRRC 0x3073
-+#define MASK_CSRRC  0x707f
-+#define MATCH_FCVT_LU_H 0x4c000053
-+#define MASK_FCVT_LU_H  0xfff0007f
-+#define MATCH_FCVT_S_D 0x40100053
-+#define MASK_FCVT_S_D  0xfff0007f
-+#define MATCH_BGEU 0x7063
-+#define MASK_BGEU  0x707f
-+#define MATCH_VFLSTD 0x1600305b
-+#define MASK_VFLSTD  0xfe00707f
-+#define MATCH_FCVT_S_L 0xd0200053
-+#define MASK_FCVT_S_L  0xfff0007f
-+#define MATCH_FCVT_S_H 0x84000053
-+#define MASK_FCVT_S_H  0xfff0007f
-+#define MATCH_FSCSR 0x301073
-+#define MASK_FSCSR  0xfff0707f
-+#define MATCH_FCVT_S_W 0xd0000053
-+#define MASK_FCVT_S_W  0xfff0007f
-+#define MATCH_VFLSTW 0x1400305b
-+#define MASK_VFLSTW  0xfe00707f
-+#define MATCH_VXCPTEVAC 0x600302b
-+#define MASK_VXCPTEVAC  0xfff07fff
-+#define MATCH_AMOMINU_D 0xc000302f
-+#define MASK_AMOMINU_D  0xf800707f
-+#define MATCH_FSFLAGS 0x101073
-+#define MASK_FSFLAGS  0xfff0707f
-+#define MATCH_SRLI 0x5013
-+#define MASK_SRLI  0xfc00707f
-+#define MATCH_C_SRLI 0x819
-+#define MASK_C_SRLI  0x1c1f
-+#define MATCH_AMOMINU_W 0xc000202f
-+#define MASK_AMOMINU_W  0xf800707f
-+#define MATCH_SRLW 0x503b
-+#define MASK_SRLW  0xfe00707f
-+#define MATCH_VFLSEGW 0x1400205b
-+#define MASK_VFLSEGW  0x1ff0707f
-+#define MATCH_C_LD0 0x8012
-+#define MASK_C_LD0  0x801f
-+#define MATCH_VLSEGBU 0x800205b
-+#define MASK_VLSEGBU  0x1ff0707f
-+#define MATCH_JALR 0x67
-+#define MASK_JALR  0x707f
-+#define MATCH_BLT 0x4063
-+#define MASK_BLT  0x707f
-+#define MATCH_CUSTOM2_RD_RS1 0x605b
-+#define MASK_CUSTOM2_RD_RS1  0x707f
-+#define MATCH_FCLASS_S 0xe0001053
-+#define MASK_FCLASS_S  0xfff0707f
-+#define MATCH_REM 0x2006033
-+#define MASK_REM  0xfe00707f
-+#define MATCH_FCLASS_D 0xe2001053
-+#define MASK_FCLASS_D  0xfff0707f
-+#define MATCH_FMUL_S 0x10000053
-+#define MASK_FMUL_S  0xfe00007f
-+#define MATCH_RDCYCLEH 0xc8002073
-+#define MASK_RDCYCLEH  0xfffff07f
-+#define MATCH_VLSEGSTHU 0xa00305b
-+#define MASK_VLSEGSTHU  0x1e00707f
-+#define MATCH_FMUL_D 0x12000053
-+#define MASK_FMUL_D  0xfe00007f
-+#define MATCH_ORI 0x6013
-+#define MASK_ORI  0x707f
-+#define MATCH_FMUL_H 0x14000053
-+#define MASK_FMUL_H  0xfe00007f
-+#define MATCH_VFLSEGD 0x1600205b
-+#define MASK_VFLSEGD  0x1ff0707f
-+#define MATCH_FEQ_S 0xa0002053
-+#define MASK_FEQ_S  0xfe00707f
-+#define MATCH_FSGNJX_D 0x22002053
-+#define MASK_FSGNJX_D  0xfe00707f
-+#define MATCH_SRAIW 0x4000501b
-+#define MASK_SRAIW  0xfe00707f
-+#define MATCH_FSGNJX_H 0x3c000053
-+#define MASK_FSGNJX_H  0xfe00707f
-+#define MATCH_FSGNJX_S 0x20002053
-+#define MASK_FSGNJX_S  0xfe00707f
-+#define MATCH_FEQ_D 0xa2002053
-+#define MASK_FEQ_D  0xfe00707f
-+#define MATCH_CUSTOM1_RD_RS1 0x602b
-+#define MASK_CUSTOM1_RD_RS1  0x707f
-+#define MATCH_FEQ_H 0xac000053
-+#define MASK_FEQ_H  0xfe00707f
-+#define MATCH_AMOMAXU_D 0xe000302f
-+#define MASK_AMOMAXU_D  0xf800707f
-+#define MATCH_DIVW 0x200403b
-+#define MASK_DIVW  0xfe00707f
-+#define MATCH_AMOMAXU_W 0xe000202f
-+#define MASK_AMOMAXU_W  0xf800707f
-+#define MATCH_SRAI_RV32 0x40005013
-+#define MASK_SRAI_RV32  0xfe00707f
-+#define MATCH_C_SRLI32 0xc19
-+#define MASK_C_SRLI32  0x1c1f
-+#define MATCH_VFSSTW 0x1400307b
-+#define MASK_VFSSTW  0xfe00707f
-+#define MATCH_CUSTOM0_RD 0x400b
-+#define MASK_CUSTOM0_RD  0x707f
-+#define MATCH_C_BEQ 0x10
-+#define MASK_C_BEQ  0x1f
-+#define MATCH_VFSSTD 0x1600307b
-+#define MASK_VFSSTD  0xfe00707f
-+#define MATCH_CUSTOM3_RD_RS1 0x607b
-+#define MASK_CUSTOM3_RD_RS1  0x707f
-+#define MATCH_LR_D 0x1000302f
-+#define MASK_LR_D  0xf9f0707f
-+#define MATCH_LR_W 0x1000202f
-+#define MASK_LR_W  0xf9f0707f
-+#define MATCH_FCVT_H_WU 0x7c000053
-+#define MASK_FCVT_H_WU  0xfff0007f
-+#define MATCH_VMVV 0x200002b
-+#define MASK_VMVV  0xfff0707f
-+#define MATCH_SLLW 0x103b
-+#define MASK_SLLW  0xfe00707f
-+#define MATCH_SLLI 0x1013
-+#define MASK_SLLI  0xfc00707f
-+#define MATCH_BEQ 0x63
-+#define MASK_BEQ  0x707f
-+#define MATCH_AND 0x7033
-+#define MASK_AND  0xfe00707f
-+#define MATCH_LBU 0x4003
-+#define MASK_LBU  0x707f
-+#define MATCH_FSGNJ_S 0x20000053
-+#define MASK_FSGNJ_S  0xfe00707f
-+#define MATCH_FMSUB_S 0x47
-+#define MASK_FMSUB_S  0x600007f
-+#define MATCH_C_SUB3 0x11c
-+#define MASK_C_SUB3  0x31f
-+#define MATCH_FSGNJ_H 0x2c000053
-+#define MASK_FSGNJ_H  0xfe00707f
-+#define MATCH_VLB 0x205b
-+#define MASK_VLB  0xfff0707f
-+#define MATCH_C_ADDIW 0x1d
-+#define MASK_C_ADDIW  0x1f
-+#define MATCH_CUSTOM3_RS1_RS2 0x307b
-+#define MASK_CUSTOM3_RS1_RS2  0x707f
-+#define MATCH_FSGNJ_D 0x22000053
-+#define MASK_FSGNJ_D  0xfe00707f
-+#define MATCH_VLSEGWU 0xc00205b
-+#define MASK_VLSEGWU  0x1ff0707f
-+#define MATCH_FCVT_S_WU 0xd0100053
-+#define MASK_FCVT_S_WU  0xfff0007f
-+#define MATCH_CUSTOM3_RS1 0x207b
-+#define MASK_CUSTOM3_RS1  0x707f
-+#define MATCH_SC_D 0x1800302f
-+#define MASK_SC_D  0xf800707f
-+#define MATCH_VFSW 0x1400207b
-+#define MASK_VFSW  0xfff0707f
-+#define MATCH_AMOSWAP_D 0x800302f
-+#define MASK_AMOSWAP_D  0xf800707f
-+#define MATCH_SB 0x23
-+#define MASK_SB  0x707f
-+#define MATCH_AMOSWAP_W 0x800202f
-+#define MASK_AMOSWAP_W  0xf800707f
-+#define MATCH_VFSD 0x1600207b
-+#define MASK_VFSD  0xfff0707f
-+#define MATCH_CUSTOM2_RS1 0x205b
-+#define MASK_CUSTOM2_RS1  0x707f
-+#define MATCH_SD 0x3023
-+#define MASK_SD  0x707f
-+#define MATCH_FMV_S_X 0xf0000053
-+#define MASK_FMV_S_X  0xfff0707f
-+#define MATCH_REMUW 0x200703b
-+#define MASK_REMUW  0xfe00707f
-+#define MATCH_JAL 0x6f
-+#define MASK_JAL  0x7f
-+#define MATCH_C_FSD 0x18
-+#define MASK_C_FSD  0x1f
-+#define MATCH_RDCYCLE 0xc0002073
-+#define MASK_RDCYCLE  0xfffff07f
-+#define MATCH_C_BNE 0x11
-+#define MASK_C_BNE  0x1f
-+#define MATCH_C_ADD 0x1a
-+#define MASK_C_ADD  0x801f
-+#define MATCH_VXCPTCAUSE 0x402b
-+#define MASK_VXCPTCAUSE  0xfffff07f
-+#define MATCH_VGETCFG 0x400b
-+#define MASK_VGETCFG  0xfffff07f
-+#define MATCH_LUI 0x37
-+#define MASK_LUI  0x7f
-+#define MATCH_VSETCFG 0x200b
-+#define MASK_VSETCFG  0x7fff
-+#define MATCH_C_SDSP 0x6
-+#define MASK_C_SDSP  0x1f
-+#define MATCH_C_LDSP 0x4
-+#define MASK_C_LDSP  0x1f
-+#define MATCH_FNMADD_H 0x400004f
-+#define MASK_FNMADD_H  0x600007f
-+#define MATCH_CUSTOM0_RS1_RS2 0x300b
-+#define MASK_CUSTOM0_RS1_RS2  0x707f
-+#define MATCH_SLLI_RV32 0x1013
-+#define MASK_SLLI_RV32  0xfe00707f
-+#define MATCH_MUL 0x2000033
-+#define MASK_MUL  0xfe00707f
-+#define MATCH_CSRRCI 0x7073
-+#define MASK_CSRRCI  0x707f
-+#define MATCH_C_SRAI32 0x1419
-+#define MASK_C_SRAI32  0x1c1f
-+#define MATCH_FLT_H 0xb4000053
-+#define MASK_FLT_H  0xfe00707f
-+#define MATCH_SRAI 0x40005013
-+#define MASK_SRAI  0xfc00707f
-+#define MATCH_AMOAND_D 0x6000302f
-+#define MASK_AMOAND_D  0xf800707f
-+#define MATCH_FLT_D 0xa2001053
-+#define MASK_FLT_D  0xfe00707f
-+#define MATCH_SRAW 0x4000503b
-+#define MASK_SRAW  0xfe00707f
-+#define MATCH_CSRRS 0x2073
-+#define MASK_CSRRS  0x707f
-+#define MATCH_FLT_S 0xa0001053
-+#define MASK_FLT_S  0xfe00707f
-+#define MATCH_ADDIW 0x1b
-+#define MASK_ADDIW  0x707f
-+#define MATCH_AMOAND_W 0x6000202f
-+#define MASK_AMOAND_W  0xf800707f
-+#define MATCH_CUSTOM2_RD 0x405b
-+#define MASK_CUSTOM2_RD  0x707f
-+#define MATCH_FCVT_WU_D 0xc2100053
-+#define MASK_FCVT_WU_D  0xfff0007f
-+#define MATCH_AMOXOR_W 0x2000202f
-+#define MASK_AMOXOR_W  0xf800707f
-+#define MATCH_FCVT_D_L 0xd2200053
-+#define MASK_FCVT_D_L  0xfff0007f
-+#define MATCH_FCVT_WU_H 0x5c000053
-+#define MASK_FCVT_WU_H  0xfff0007f
-+#define MATCH_C_SLLI 0x19
-+#define MASK_C_SLLI  0x1c1f
-+#define MATCH_AMOXOR_D 0x2000302f
-+#define MASK_AMOXOR_D  0xf800707f
-+#define MATCH_FCVT_WU_S 0xc0100053
-+#define MASK_FCVT_WU_S  0xfff0007f
-+#define MATCH_CUSTOM3_RD 0x407b
-+#define MASK_CUSTOM3_RD  0x707f
-+#define MATCH_FMAX_H 0xcc000053
-+#define MASK_FMAX_H  0xfe00707f
-+#define MATCH_VENQCNT 0x1000302b
-+#define MASK_VENQCNT  0xfe007fff
-+#define MATCH_VLBU 0x800205b
-+#define MASK_VLBU  0xfff0707f
-+#define MATCH_VLHU 0xa00205b
-+#define MASK_VLHU  0xfff0707f
-+#define MATCH_C_SW 0xd
-+#define MASK_C_SW  0x1f
-+#define MATCH_C_SD 0xc
-+#define MASK_C_SD  0x1f
-+#define MATCH_C_OR3 0x21c
-+#define MASK_C_OR3  0x31f
-+#define MATCH_C_AND3 0x31c
-+#define MASK_C_AND3  0x31f
-+#define MATCH_VFSSEGSTW 0x1400307b
-+#define MASK_VFSSEGSTW  0x1e00707f
-+#define MATCH_SLT 0x2033
-+#define MASK_SLT  0xfe00707f
-+#define MATCH_AMOOR_D 0x4000302f
-+#define MASK_AMOOR_D  0xf800707f
-+#define MATCH_REMU 0x2007033
-+#define MASK_REMU  0xfe00707f
-+#define MATCH_REMW 0x200603b
-+#define MASK_REMW  0xfe00707f
-+#define MATCH_SLL 0x1033
-+#define MASK_SLL  0xfe00707f
-+#define MATCH_VFSSEGSTD 0x1600307b
-+#define MASK_VFSSEGSTD  0x1e00707f
-+#define MATCH_AMOOR_W 0x4000202f
-+#define MASK_AMOOR_W  0xf800707f
-+#define MATCH_CUSTOM2_RS1_RS2 0x305b
-+#define MASK_CUSTOM2_RS1_RS2  0x707f
-+#define MATCH_VF 0x10202b
-+#define MASK_VF  0x1f0707f
-+#define MATCH_VFMVV 0x1000002b
-+#define MASK_VFMVV  0xfff0707f
-+#define MATCH_VFLSEGSTW 0x1400305b
-+#define MASK_VFLSEGSTW  0x1e00707f
-+#define MATCH_VXCPTRESTORE 0x200302b
-+#define MASK_VXCPTRESTORE  0xfff07fff
-+#define MATCH_VXCPTHOLD 0x800302b
-+#define MASK_VXCPTHOLD  0xffffffff
-+#define MATCH_SLTIU 0x3013
-+#define MASK_SLTIU  0x707f
-+#define MATCH_VFLSEGSTD 0x1600305b
-+#define MASK_VFLSEGSTD  0x1e00707f
-+#define MATCH_VFLD 0x1600205b
-+#define MASK_VFLD  0xfff0707f
-+#define MATCH_FMADD_S 0x43
-+#define MASK_FMADD_S  0x600007f
-+#define MATCH_VFLW 0x1400205b
-+#define MASK_VFLW  0xfff0707f
-+#define MATCH_FMADD_D 0x2000043
-+#define MASK_FMADD_D  0x600007f
-+#define MATCH_FMADD_H 0x4000043
-+#define MASK_FMADD_H  0x600007f
-+#define MATCH_SRET 0x80000073
-+#define MASK_SRET  0xffffffff
-+#define MATCH_VSSEGW 0x400207b
-+#define MASK_VSSEGW  0x1ff0707f
-+#define MATCH_CUSTOM0_RD_RS1 0x600b
-+#define MASK_CUSTOM0_RD_RS1  0x707f
-+#define MATCH_VSSEGH 0x200207b
-+#define MASK_VSSEGH  0x1ff0707f
-+#define MATCH_FRCSR 0x302073
-+#define MASK_FRCSR  0xfffff07f
-+#define MATCH_VSSEGD 0x600207b
-+#define MASK_VSSEGD  0x1ff0707f
-+#define MATCH_VSSEGB 0x207b
-+#define MASK_VSSEGB  0x1ff0707f
-+#define MATCH_FMIN_H 0xc4000053
-+#define MASK_FMIN_H  0xfe00707f
-+#define MATCH_FMIN_D 0x2a000053
-+#define MASK_FMIN_D  0xfe00707f
-+#define MATCH_BLTU 0x6063
-+#define MASK_BLTU  0x707f
-+#define MATCH_FMIN_S 0x28000053
-+#define MASK_FMIN_S  0xfe00707f
-+#define MATCH_SRLI_RV32 0x5013
-+#define MASK_SRLI_RV32  0xfe00707f
-+#define MATCH_SLLIW 0x101b
-+#define MASK_SLLIW  0xfe00707f
-+#define MATCH_FMAX_S 0x28001053
-+#define MASK_FMAX_S  0xfe00707f
-+#define MATCH_FCVT_D_H 0x8c000053
-+#define MASK_FCVT_D_H  0xfff0007f
-+#define MATCH_FCVT_D_W 0xd2000053
-+#define MASK_FCVT_D_W  0xfff0007f
-+#define MATCH_ADD 0x33
-+#define MASK_ADD  0xfe00707f
-+#define MATCH_FCVT_D_S 0x42000053
-+#define MASK_FCVT_D_S  0xfff0007f
-+#define MATCH_FMAX_D 0x2a001053
-+#define MASK_FMAX_D  0xfe00707f
-+#define MATCH_BNE 0x1063
-+#define MASK_BNE  0x707f
-+#define MATCH_CUSTOM1_RD 0x402b
-+#define MASK_CUSTOM1_RD  0x707f
-+#define MATCH_FSRM 0x201073
-+#define MASK_FSRM  0xfff0707f
-+#define MATCH_FDIV_D 0x1a000053
-+#define MASK_FDIV_D  0xfe00007f
-+#define MATCH_VSW 0x400207b
-+#define MASK_VSW  0xfff0707f
-+#define MATCH_FCVT_L_S 0xc0200053
-+#define MASK_FCVT_L_S  0xfff0007f
-+#define MATCH_FDIV_H 0x1c000053
-+#define MASK_FDIV_H  0xfe00007f
-+#define MATCH_VSB 0x207b
-+#define MASK_VSB  0xfff0707f
-+#define MATCH_FDIV_S 0x18000053
-+#define MASK_FDIV_S  0xfe00007f
-+#define MATCH_FSRMI 0x205073
-+#define MASK_FSRMI  0xfff0707f
-+#define MATCH_FCVT_L_H 0x44000053
-+#define MASK_FCVT_L_H  0xfff0007f
-+#define MATCH_VSH 0x200207b
-+#define MASK_VSH  0xfff0707f
-+#define MATCH_FCVT_L_D 0xc2200053
-+#define MASK_FCVT_L_D  0xfff0007f
-+#define MATCH_FCVT_H_S 0x90000053
-+#define MASK_FCVT_H_S  0xfff0007f
-+#define MATCH_SCALL 0x73
-+#define MASK_SCALL  0xffffffff
-+#define MATCH_FSFLAGSI 0x105073
-+#define MASK_FSFLAGSI  0xfff0707f
-+#define MATCH_FCVT_H_W 0x74000053
-+#define MASK_FCVT_H_W  0xfff0007f
-+#define MATCH_FCVT_H_L 0x64000053
-+#define MASK_FCVT_H_L  0xfff0007f
-+#define MATCH_SRLIW 0x501b
-+#define MASK_SRLIW  0xfe00707f
-+#define MATCH_FCVT_S_LU 0xd0300053
-+#define MASK_FCVT_S_LU  0xfff0007f
-+#define MATCH_FCVT_H_D 0x92000053
-+#define MASK_FCVT_H_D  0xfff0007f
-+#define MATCH_SBREAK 0x100073
-+#define MASK_SBREAK  0xffffffff
-+#define MATCH_RDINSTRETH 0xc8202073
-+#define MASK_RDINSTRETH  0xfffff07f
-+#define MATCH_SRA 0x40005033
-+#define MASK_SRA  0xfe00707f
-+#define MATCH_BGE 0x5063
-+#define MASK_BGE  0x707f
-+#define MATCH_SRL 0x5033
-+#define MASK_SRL  0xfe00707f
-+#define MATCH_VENQCMD 0xa00302b
-+#define MASK_VENQCMD  0xfe007fff
-+#define MATCH_OR 0x6033
-+#define MASK_OR  0xfe00707f
-+#define MATCH_SUBW 0x4000003b
-+#define MASK_SUBW  0xfe00707f
-+#define MATCH_FMV_X_D 0xe2000053
-+#define MASK_FMV_X_D  0xfff0707f
-+#define MATCH_RDTIME 0xc0102073
-+#define MASK_RDTIME  0xfffff07f
-+#define MATCH_AMOADD_D 0x302f
-+#define MASK_AMOADD_D  0xf800707f
-+#define MATCH_AMOMAX_W 0xa000202f
-+#define MASK_AMOMAX_W  0xf800707f
-+#define MATCH_C_MOVE 0x2
-+#define MASK_C_MOVE  0x801f
-+#define MATCH_FMOVN 0x6007077
-+#define MASK_FMOVN  0xfe00707f
-+#define MATCH_C_FSW 0x16
-+#define MASK_C_FSW  0x1f
-+#define MATCH_AMOADD_W 0x202f
-+#define MASK_AMOADD_W  0xf800707f
-+#define MATCH_AMOMAX_D 0xa000302f
-+#define MASK_AMOMAX_D  0xf800707f
-+#define MATCH_FMOVZ 0x4007077
-+#define MASK_FMOVZ  0xfe00707f
-+#define MATCH_CUSTOM1_RS1_RS2 0x302b
-+#define MASK_CUSTOM1_RS1_RS2  0x707f
-+#define MATCH_FMV_X_H 0xe4000053
-+#define MASK_FMV_X_H  0xfff0707f
-+#define MATCH_VSD 0x600207b
-+#define MASK_VSD  0xfff0707f
-+#define MATCH_VLSEGSTW 0x400305b
-+#define MASK_VLSEGSTW  0x1e00707f
-+#define MATCH_C_ADDI 0x1
-+#define MASK_C_ADDI  0x1f
-+#define MATCH_C_SLLIW 0x1819
-+#define MASK_C_SLLIW  0x1c1f
-+#define MATCH_VLSEGSTB 0x305b
-+#define MASK_VLSEGSTB  0x1e00707f
-+#define MATCH_VLSEGSTD 0x600305b
-+#define MASK_VLSEGSTD  0x1e00707f
-+#define MATCH_VLSEGSTH 0x200305b
-+#define MASK_VLSEGSTH  0x1e00707f
-+#define MATCH_MULHU 0x2003033
-+#define MASK_MULHU  0xfe00707f
-+#define MATCH_AMOMIN_W 0x8000202f
-+#define MASK_AMOMIN_W  0xf800707f
-+#define MATCH_C_SLLI32 0x419
-+#define MASK_C_SLLI32  0x1c1f
-+#define MATCH_C_ADD3 0x1c
-+#define MASK_C_ADD3  0x31f
-+#define MATCH_VGETVL 0x200400b
-+#define MASK_VGETVL  0xfffff07f
-+#define MATCH_AMOMIN_D 0x8000302f
-+#define MASK_AMOMIN_D  0xf800707f
-+#define MATCH_FCVT_W_H 0x54000053
-+#define MASK_FCVT_W_H  0xfff0007f
-+#define MATCH_VLSEGB 0x205b
-+#define MASK_VLSEGB  0x1ff0707f
-+#define MATCH_FSD 0x3027
-+#define MASK_FSD  0x707f
-+#define MATCH_VLSEGD 0x600205b
-+#define MASK_VLSEGD  0x1ff0707f
-+#define MATCH_FSH 0x1027
-+#define MASK_FSH  0x707f
-+#define MATCH_VLSEGH 0x200205b
-+#define MASK_VLSEGH  0x1ff0707f
-+#define MATCH_C_SUB 0x801a
-+#define MASK_C_SUB  0x801f
-+#define MATCH_VLSEGW 0x400205b
-+#define MASK_VLSEGW  0x1ff0707f
-+#define MATCH_FSW 0x2027
-+#define MASK_FSW  0x707f
-+#define MATCH_C_J 0x8002
-+#define MASK_C_J  0x801f
-+#define CSR_FFLAGS 0x1
-+#define CSR_FRM 0x2
-+#define CSR_FCSR 0x3
-+#define CSR_STATS 0xc0
-+#define CSR_SUP0 0x500
-+#define CSR_SUP1 0x501
-+#define CSR_EPC 0x502
-+#define CSR_BADVADDR 0x503
-+#define CSR_PTBR 0x504
-+#define CSR_ASID 0x505
-+#define CSR_COUNT 0x506
-+#define CSR_COMPARE 0x507
-+#define CSR_EVEC 0x508
-+#define CSR_CAUSE 0x509
-+#define CSR_STATUS 0x50a
-+#define CSR_HARTID 0x50b
-+#define CSR_IMPL 0x50c
-+#define CSR_FATC 0x50d
-+#define CSR_SEND_IPI 0x50e
-+#define CSR_CLEAR_IPI 0x50f
-+#define CSR_RESET 0x51d
-+#define CSR_TOHOST 0x51e
-+#define CSR_FROMHOST 0x51f
-+#define CSR_CYCLE 0xc00
-+#define CSR_TIME 0xc01
-+#define CSR_INSTRET 0xc02
-+#define CSR_UARCH0 0xcc0
-+#define CSR_UARCH1 0xcc1
-+#define CSR_UARCH2 0xcc2
-+#define CSR_UARCH3 0xcc3
-+#define CSR_UARCH4 0xcc4
-+#define CSR_UARCH5 0xcc5
-+#define CSR_UARCH6 0xcc6
-+#define CSR_UARCH7 0xcc7
-+#define CSR_UARCH8 0xcc8
-+#define CSR_UARCH9 0xcc9
-+#define CSR_UARCH10 0xcca
-+#define CSR_UARCH11 0xccb
-+#define CSR_UARCH12 0xccc
-+#define CSR_UARCH13 0xccd
-+#define CSR_UARCH14 0xcce
-+#define CSR_UARCH15 0xccf
-+#define CSR_COUNTH 0x586
-+#define CSR_CYCLEH 0xc80
-+#define CSR_TIMEH 0xc81
-+#define CSR_INSTRETH 0xc82
-+#define CAUSE_MISALIGNED_FETCH 0x0
-+#define CAUSE_FAULT_FETCH 0x1
-+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
-+#define CAUSE_PRIVILEGED_INSTRUCTION 0x3
-+#define CAUSE_FP_DISABLED 0x4
-+#define CAUSE_SYSCALL 0x6
-+#define CAUSE_BREAKPOINT 0x7
-+#define CAUSE_MISALIGNED_LOAD 0x8
-+#define CAUSE_MISALIGNED_STORE 0x9
-+#define CAUSE_FAULT_LOAD 0xa
-+#define CAUSE_FAULT_STORE 0xb
-+#define CAUSE_ACCELERATOR_DISABLED 0xc
-+#endif
-+#ifdef DECLARE_INSN
-+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-+DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
-+DECLARE_INSN(c_lw0, MATCH_C_LW0, MASK_C_LW0)
-+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
-+DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
-+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
-+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
-+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
-+DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
-+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
-+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
-+DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
-+DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
-+DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
-+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
-+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
-+DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
-+DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
-+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
-+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
-+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
-+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
-+DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
-+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
-+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
-+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
-+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
-+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
-+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
-+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
-+DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
-+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
-+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
-+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
-+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
-+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
-+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
-+DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
-+DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
-+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
-+DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
-+DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
-+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
-+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
-+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
-+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
-+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
-+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
-+DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
-+DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
-+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
-+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
-+DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
-+DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
-+DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
-+DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
-+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
-+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
-+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
-+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
-+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
-+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
-+DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
-+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
-+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
-+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
-+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
-+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
-+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
-+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
-+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
-+DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
-+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
-+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
-+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
-+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
-+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
-+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
-+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
-+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
-+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
-+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
-+DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
-+DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
-+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
-+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
-+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
-+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
-+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
-+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
-+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
-+DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
-+DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
-+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
-+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
-+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
-+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
-+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
-+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
-+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
-+DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
-+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
-+DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
-+DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
-+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
-+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
-+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
-+DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
-+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
-+DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
-+DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
-+DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
-+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
-+DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
-+DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
-+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
-+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-+DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
-+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
-+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
-+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
-+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
-+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
-+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
-+DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
-+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
-+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
-+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
-+DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
-+DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
-+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
-+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
-+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
-+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
-+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
-+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
-+DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
-+DECLARE_INSN(c_ld0, MATCH_C_LD0, MASK_C_LD0)
-+DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
-+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
-+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
-+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
-+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
-+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
-+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
-+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
-+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
-+DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
-+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
-+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
-+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
-+DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
-+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
-+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
-+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
-+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
-+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
-+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
-+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
-+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
-+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
-+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
-+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
-+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
-+DECLARE_INSN(c_srli32, MATCH_C_SRLI32, MASK_C_SRLI32)
-+DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
-+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
-+DECLARE_INSN(c_beq, MATCH_C_BEQ, MASK_C_BEQ)
-+DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
-+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
-+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
-+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
-+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
-+DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
-+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
-+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
-+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
-+DECLARE_INSN(and, MATCH_AND, MASK_AND)
-+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
-+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
-+DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
-+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
-+DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
-+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
-+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
-+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
-+DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
-+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
-+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
-+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
-+DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
-+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
-+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
-+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
-+DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
-+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
-+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
-+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
-+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
-+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
-+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
-+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
-+DECLARE_INSN(c_bne, MATCH_C_BNE, MASK_C_BNE)
-+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
-+DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
-+DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
-+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
-+DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
-+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
-+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
-+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
-+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
-+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
-+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
-+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
-+DECLARE_INSN(c_srai32, MATCH_C_SRAI32, MASK_C_SRAI32)
-+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
-+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
-+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
-+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
-+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
-+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
-+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
-+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
-+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
-+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
-+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
-+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
-+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
-+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
-+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
-+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
-+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
-+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
-+DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
-+DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
-+DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
-+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
-+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
-+DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
-+DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
-+DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
-+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
-+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
-+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
-+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
-+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
-+DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
-+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
-+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
-+DECLARE_INSN(vf, MATCH_VF, MASK_VF)
-+DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
-+DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
-+DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
-+DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
-+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
-+DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
-+DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
-+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
-+DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
-+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
-+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
-+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
-+DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
-+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
-+DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
-+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
-+DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
-+DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
-+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
-+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
-+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
-+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
-+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
-+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
-+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
-+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
-+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
-+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
-+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
-+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
-+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
-+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
-+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
-+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
-+DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
-+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
-+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
-+DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
-+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
-+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
-+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
-+DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
-+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
-+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
-+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
-+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
-+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
-+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
-+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
-+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
-+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
-+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
-+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
-+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
-+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
-+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
-+DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
-+DECLARE_INSN(or, MATCH_OR, MASK_OR)
-+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
-+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
-+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
-+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
-+DECLARE_INSN(c_move, MATCH_C_MOVE, MASK_C_MOVE)
-+DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
-+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
-+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
-+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
-+DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
-+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
-+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
-+DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
-+DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
-+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
-+DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
-+DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
-+DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
-+DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
-+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
-+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
-+DECLARE_INSN(c_slli32, MATCH_C_SLLI32, MASK_C_SLLI32)
-+DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
-+DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
-+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
-+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
-+DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
-+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
-+DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
-+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
-+DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
-+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
-+DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
-+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
-+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
-+#endif
-+#ifdef DECLARE_CSR
-+DECLARE_CSR(fflags, CSR_FFLAGS)
-+DECLARE_CSR(frm, CSR_FRM)
-+DECLARE_CSR(fcsr, CSR_FCSR)
-+DECLARE_CSR(stats, CSR_STATS)
-+DECLARE_CSR(sup0, CSR_SUP0)
-+DECLARE_CSR(sup1, CSR_SUP1)
-+DECLARE_CSR(epc, CSR_EPC)
-+DECLARE_CSR(badvaddr, CSR_BADVADDR)
-+DECLARE_CSR(ptbr, CSR_PTBR)
-+DECLARE_CSR(asid, CSR_ASID)
-+DECLARE_CSR(count, CSR_COUNT)
-+DECLARE_CSR(compare, CSR_COMPARE)
-+DECLARE_CSR(evec, CSR_EVEC)
-+DECLARE_CSR(cause, CSR_CAUSE)
-+DECLARE_CSR(status, CSR_STATUS)
-+DECLARE_CSR(hartid, CSR_HARTID)
-+DECLARE_CSR(impl, CSR_IMPL)
-+DECLARE_CSR(fatc, CSR_FATC)
-+DECLARE_CSR(send_ipi, CSR_SEND_IPI)
-+DECLARE_CSR(clear_ipi, CSR_CLEAR_IPI)
-+DECLARE_CSR(reset, CSR_RESET)
-+DECLARE_CSR(tohost, CSR_TOHOST)
-+DECLARE_CSR(fromhost, CSR_FROMHOST)
-+DECLARE_CSR(cycle, CSR_CYCLE)
-+DECLARE_CSR(time, CSR_TIME)
-+DECLARE_CSR(instret, CSR_INSTRET)
-+DECLARE_CSR(uarch0, CSR_UARCH0)
-+DECLARE_CSR(uarch1, CSR_UARCH1)
-+DECLARE_CSR(uarch2, CSR_UARCH2)
-+DECLARE_CSR(uarch3, CSR_UARCH3)
-+DECLARE_CSR(uarch4, CSR_UARCH4)
-+DECLARE_CSR(uarch5, CSR_UARCH5)
-+DECLARE_CSR(uarch6, CSR_UARCH6)
-+DECLARE_CSR(uarch7, CSR_UARCH7)
-+DECLARE_CSR(uarch8, CSR_UARCH8)
-+DECLARE_CSR(uarch9, CSR_UARCH9)
-+DECLARE_CSR(uarch10, CSR_UARCH10)
-+DECLARE_CSR(uarch11, CSR_UARCH11)
-+DECLARE_CSR(uarch12, CSR_UARCH12)
-+DECLARE_CSR(uarch13, CSR_UARCH13)
-+DECLARE_CSR(uarch14, CSR_UARCH14)
-+DECLARE_CSR(uarch15, CSR_UARCH15)
-+DECLARE_CSR(counth, CSR_COUNTH)
-+DECLARE_CSR(cycleh, CSR_CYCLEH)
-+DECLARE_CSR(timeh, CSR_TIMEH)
-+DECLARE_CSR(instreth, CSR_INSTRETH)
-+#endif
-+#ifdef DECLARE_CAUSE
-+DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
-+DECLARE_CAUSE("frm", CAUSE_FRM)
-+DECLARE_CAUSE("fcsr", CAUSE_FCSR)
-+DECLARE_CAUSE("stats", CAUSE_STATS)
-+DECLARE_CAUSE("sup0", CAUSE_SUP0)
-+DECLARE_CAUSE("sup1", CAUSE_SUP1)
-+DECLARE_CAUSE("epc", CAUSE_EPC)
-+DECLARE_CAUSE("badvaddr", CAUSE_BADVADDR)
-+DECLARE_CAUSE("ptbr", CAUSE_PTBR)
-+DECLARE_CAUSE("asid", CAUSE_ASID)
-+DECLARE_CAUSE("count", CAUSE_COUNT)
-+DECLARE_CAUSE("compare", CAUSE_COMPARE)
-+DECLARE_CAUSE("evec", CAUSE_EVEC)
-+DECLARE_CAUSE("cause", CAUSE_CAUSE)
-+DECLARE_CAUSE("status", CAUSE_STATUS)
-+DECLARE_CAUSE("hartid", CAUSE_HARTID)
-+DECLARE_CAUSE("impl", CAUSE_IMPL)
-+DECLARE_CAUSE("fatc", CAUSE_FATC)
-+DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
-+DECLARE_CAUSE("clear_ipi", CAUSE_CLEAR_IPI)
-+DECLARE_CAUSE("reset", CAUSE_RESET)
-+DECLARE_CAUSE("tohost", CAUSE_TOHOST)
-+DECLARE_CAUSE("fromhost", CAUSE_FROMHOST)
-+DECLARE_CAUSE("cycle", CAUSE_CYCLE)
-+DECLARE_CAUSE("time", CAUSE_TIME)
-+DECLARE_CAUSE("instret", CAUSE_INSTRET)
-+DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
-+DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
-+DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
-+DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
-+DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
-+DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
-+DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
-+DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
-+DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
-+DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
-+DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
-+DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
-+DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
-+DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
-+DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
-+DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
-+DECLARE_CAUSE("counth", CAUSE_COUNTH)
-+DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
-+DECLARE_CAUSE("timeh", CAUSE_TIMEH)
-+DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
-+#endif
-diff -urN original-binutils/ld/configure.tgt binutils/ld/configure.tgt
---- original-binutils/ld/configure.tgt	2014-10-14 09:32:04.000000000 +0200
-+++ binutils-2.25/ld/configure.tgt	2015-03-07 09:55:02.383135671 +0100
-@@ -604,6 +604,12 @@
- powerpc-*-beos*)	targ_emul=aixppc ;;
- powerpc-*-windiss*)	targ_emul=elf32ppcwindiss ;;
- powerpc-*-lynxos*)	targ_emul=ppclynx ;;
-+riscv32*-*-*)		targ_emul=elf32lriscv
-+			targ_extra_emuls="elf64lriscv"
-+			targ_extra_libpath=$targ_extra_emuls ;;
-+riscv*-*-*)		targ_emul=elf64lriscv
-+			targ_extra_emuls="elf32lriscv"
-+			targ_extra_libpath=$targ_extra_emuls ;;
- rs6000-*-aix[5-9]*)	targ_emul=aix5rs6 ;;
- rs6000-*-aix*)		targ_emul=aixrs6
- 			;;
-diff -urN original-binutils/ld/emulparams/elf32lriscv-defs.sh binutils/ld/emulparams/elf32lriscv-defs.sh
---- original-binutils/ld/emulparams/elf32lriscv-defs.sh	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emulparams/elf32lriscv-defs.sh	2015-03-07 09:51:45.659139025 +0100
+diff -urN empty/ld/emulparams/elf32lriscv-defs.sh binutils-2.25/ld/emulparams/elf32lriscv-defs.sh
+--- empty/ld/emulparams/elf32lriscv-defs.sh	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/ld/emulparams/elf32lriscv-defs.sh	2015-07-18 00:02:36.222287541 +0200
 @@ -0,0 +1,39 @@
 +# This is an ELF platform.
 +SCRIPT_NAME=elf
@@ -8295,26 +8394,26 @@
 +  OTHER_READONLY_SECTIONS=".srodata      ${RELOCATING-0} : { *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) }"
 +  unset GOT
 +fi
-diff -urN original-binutils/ld/emulparams/elf32lriscv.sh binutils/ld/emulparams/elf32lriscv.sh
---- original-binutils/ld/emulparams/elf32lriscv.sh	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emulparams/elf32lriscv.sh	2015-03-07 09:51:45.659139025 +0100
+diff -urN empty/ld/emulparams/elf32lriscv.sh binutils-2.25/ld/emulparams/elf32lriscv.sh
+--- empty/ld/emulparams/elf32lriscv.sh	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/ld/emulparams/elf32lriscv.sh	2015-07-18 00:02:36.222287541 +0200
 @@ -0,0 +1,2 @@
 +. ${srcdir}/emulparams/elf32lriscv-defs.sh
 +OUTPUT_FORMAT="elf32-littleriscv"
-diff -urN original-binutils/ld/emulparams/elf64lriscv-defs.sh binutils/ld/emulparams/elf64lriscv-defs.sh
---- original-binutils/ld/emulparams/elf64lriscv-defs.sh	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emulparams/elf64lriscv-defs.sh	2015-03-07 09:51:45.659139025 +0100
+diff -urN empty/ld/emulparams/elf64lriscv-defs.sh binutils-2.25/ld/emulparams/elf64lriscv-defs.sh
+--- empty/ld/emulparams/elf64lriscv-defs.sh	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/ld/emulparams/elf64lriscv-defs.sh	2015-07-18 00:02:36.222287541 +0200
 @@ -0,0 +1 @@
 +. ${srcdir}/emulparams/elf32lriscv-defs.sh
-diff -urN original-binutils/ld/emulparams/elf64lriscv.sh binutils/ld/emulparams/elf64lriscv.sh
---- original-binutils/ld/emulparams/elf64lriscv.sh	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emulparams/elf64lriscv.sh	2015-03-07 09:51:45.659139025 +0100
+diff -urN empty/ld/emulparams/elf64lriscv.sh binutils-2.25/ld/emulparams/elf64lriscv.sh
+--- empty/ld/emulparams/elf64lriscv.sh	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/ld/emulparams/elf64lriscv.sh	2015-07-18 00:02:36.222287541 +0200
 @@ -0,0 +1,2 @@
 +. ${srcdir}/emulparams/elf64lriscv-defs.sh
 +OUTPUT_FORMAT="elf64-littleriscv"
-diff -urN original-binutils/ld/emultempl/riscvelf.em binutils/ld/emultempl/riscvelf.em
---- original-binutils/ld/emultempl/riscvelf.em	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emultempl/riscvelf.em	2015-03-07 09:51:45.659139025 +0100
+diff -urN empty/ld/emultempl/riscvelf.em binutils-2.25/ld/emultempl/riscvelf.em
+--- empty/ld/emultempl/riscvelf.em	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/ld/emultempl/riscvelf.em	2015-07-18 00:02:36.222287541 +0200
 @@ -0,0 +1,68 @@
 +# This shell script emits a C file. -*- C -*-
 +#   Copyright 2004, 2006, 2007, 2008 Free Software Foundation, Inc.
@@ -8384,150 +8483,10 @@
 +
 +LDEMUL_BEFORE_ALLOCATION=riscv_elf_before_allocation
 +LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
-diff -urN original-binutils/ld/Makefile.am binutils/ld/Makefile.am
---- original-binutils/ld/Makefile.am	2014-10-14 09:32:04.000000000 +0200
-+++ binutils-2.25/ld/Makefile.am	2015-03-07 09:55:02.383135671 +0100
-@@ -258,6 +258,7 @@
- 	eelf32ppcsim.c \
- 	eelf32ppcvxworks.c \
- 	eelf32ppcwindiss.c \
-+	eelf32lriscv.c \
- 	eelf32rl78.c \
- 	eelf32rx.c \
- 	eelf32tilegx.c \
-@@ -464,6 +465,7 @@
- 	eelf64btsmip_fbsd.c \
- 	eelf64hppa.c \
- 	eelf64lppc.c \
-+	eelf64lriscv.c \
- 	eelf64ltsmip.c \
- 	eelf64ltsmip_fbsd.c \
- 	eelf64mmix.c \
-@@ -1104,6 +1106,11 @@
-   ldemul-list.h \
-   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
- 
-+eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \
-+  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
-+  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
-+  ${GEN_DEPENDS}
-+
- eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \
-   $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \
-   $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
-@@ -1861,6 +1868,12 @@
-   ldemul-list.h \
-   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
- 
-+eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \
-+  $(srcdir)/emulparams/elf64lriscv-defs.sh \
-+  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
-+  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
-+  ${GEN_DEPENDS}
-+
- eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \
-   $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \
-   $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \
-diff -urN original-binutils/ld/Makefile.in binutils/ld/Makefile.in
---- original-binutils/ld/Makefile.in	2014-10-14 09:32:04.000000000 +0200
-+++ binutils-2.25/ld/Makefile.in	2015-03-07 09:55:02.383135671 +0100
-@@ -546,6 +546,7 @@
- 	eelf32lppclinux.c \
- 	eelf32lppcnto.c \
- 	eelf32lppcsim.c \
-+	eelf32lriscv.c \
- 	eelf32m32c.c \
- 	eelf32mb_linux.c \
- 	eelf32mbel_linux.c \
-@@ -771,6 +772,7 @@
- 	eelf64btsmip_fbsd.c \
- 	eelf64hppa.c \
- 	eelf64lppc.c \
-+	eelf64lriscv.c \
- 	eelf64ltsmip.c \
- 	eelf64ltsmip_fbsd.c \
- 	eelf64mmix.c \
-@@ -1157,6 +1159,7 @@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppclinux.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcnto.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcsim.Po@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900n32.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lsmip.Po@am__quote@
-@@ -1211,6 +1214,7 @@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Po@am__quote@
-@@ -2545,6 +2549,11 @@
-   ldemul-list.h \
-   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
- 
-+eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \
-+  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
-+  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
-+  ${GEN_DEPENDS}
-+
- eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \
-   $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \
-   $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
-@@ -3302,6 +3311,12 @@
-   ldemul-list.h \
-   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
- 
-+eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \
-+  $(srcdir)/emulparams/elf64lriscv-defs.sh \
-+  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
-+  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
-+  ${GEN_DEPENDS}
-+
- eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \
-   $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \
-   $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \
-diff -urN original-binutils/opcodes/configure binutils/opcodes/configure
---- original-binutils/opcodes/configure	2014-12-23 15:22:07.000000000 +0100
-+++ binutils-2.25/opcodes/configure	2015-03-07 09:55:02.387135671 +0100
-@@ -12590,6 +12590,7 @@
- 	bfd_powerpc_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
- 	bfd_powerpc_64_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
- 	bfd_pyramid_arch)	;;
-+	bfd_riscv_arch)		ta="$ta riscv-dis.lo riscv-opc.lo" ;;
- 	bfd_romp_arch)		;;
- 	bfd_rs6000_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
- 	bfd_rl78_arch)		ta="$ta rl78-dis.lo rl78-decode.lo";;
-diff -urN original-binutils/opcodes/disassemble.c binutils/opcodes/disassemble.c
---- original-binutils/opcodes/disassemble.c	2014-10-14 09:32:04.000000000 +0200
-+++ binutils-2.25/opcodes/disassemble.c	2015-03-07 09:55:02.391135671 +0100
-@@ -373,6 +373,11 @@
- 	disassemble = print_insn_little_powerpc;
-       break;
- #endif
-+#ifdef ARCH_riscv
-+    case bfd_arch_riscv:
-+      disassemble = print_insn_riscv;
-+      break;
-+#endif
- #ifdef ARCH_rs6000
-     case bfd_arch_rs6000:
-       if (bfd_get_mach (abfd) == bfd_mach_ppc_620)
-@@ -545,6 +550,9 @@
- #ifdef ARCH_powerpc
-   print_ppc_disassembler_options (stream);
- #endif
-+#ifdef ARCH_riscv
-+  print_riscv_disassembler_options (stream);
-+#endif
- #ifdef ARCH_i386
-   print_i386_disassembler_options (stream);
- #endif
-diff -urN original-binutils/opcodes/riscv-dis.c binutils/opcodes/riscv-dis.c
---- original-binutils/opcodes/riscv-dis.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/opcodes/riscv-dis.c	2015-03-07 09:51:45.659139025 +0100
-@@ -0,0 +1,492 @@
+diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
+--- empty/opcodes/riscv-dis.c	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/opcodes/riscv-dis.c	2015-07-18 00:02:36.222287541 +0200
+@@ -0,0 +1,590 @@
 +/* RISC-V disassembler
 +   Copyright 2011-2014 Free Software Foundation, Inc.
 +
@@ -8560,7 +8519,7 @@
 +#include "elf/riscv.h"
 +
 +#include <stdint.h>
-+#include <assert.h>
++#include <ctype.h>
 +
 +struct riscv_private_data
 +{
@@ -8593,9 +8552,11 @@
 +      riscv_gpr_names = riscv_gpr_names_numeric;
 +      riscv_fpr_names = riscv_fpr_names_numeric;
 +    }
-+
-+  /* Invalid option.  */
-+  fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option);
++  else
++    {
++      /* Invalid option.  */
++      fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option);
++    }
 +}
 +
 +static void
@@ -8647,9 +8608,10 @@
 +  struct riscv_private_data *pd = info->private_data;
 +  int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
 +  int rd = (l >> OP_SH_RD) & OP_MASK_RD;
++  fprintf_ftype print = info->fprintf_func;
 +
 +  if (*d != '\0')
-+    (*info->fprintf_func) (info->stream, "\t");
++    print (info->stream, "\t");
 +
 +  for (; *d != '\0'; d++)
 +    {
@@ -8742,6 +8704,86 @@
 +          }
 +          break;
 +
++	case 'C': /* RVC */
++	  switch (*++d)
++	    {
++	    case 'd': /* RD x8-x15 */
++	      print (info->stream, "%s",
++		     riscv_gpr_names[((l >> OP_SH_CRDS) & OP_MASK_CRDS) + 8]);
++	      break;
++	    case 's': /* RS1 x8-x15 */
++	    case 'w': /* RS1 x8-x15 */
++	      print (info->stream, "%s",
++		     riscv_gpr_names[((l >> OP_SH_CRS1S) & OP_MASK_CRS1S) + 8]);
++	      break;
++	    case 't': /* RS2 x8-x15 */
++	    case 'x': /* RS2 x8-x15 */
++	      print (info->stream, "%s",
++		     riscv_gpr_names[((l >> OP_SH_CRS2S) & OP_MASK_CRS2S) + 8]);
++	      break;
++	    case 'U': /* RS1, constrained to equal RD */
++	    case 'D': /* RS1 or RD, nonzero */
++	      print (info->stream, "%s", riscv_gpr_names[rd]);
++	      break;
++	    case 'c': /* RS1, constrained to equal sp */
++	      print (info->stream, "%s", riscv_gpr_names[X_SP]);
++	      continue;
++	    case 'T': /* RS2, nonzero */
++	    case 'V': /* RS2 */
++	      print (info->stream, "%s",
++		     riscv_gpr_names[(l >> OP_SH_CRS2) & OP_MASK_CRS2]);
++	      continue;
++	    case 'i':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
++	      break;
++	    case 'j':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
++	      break;
++	    case 'k':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l));
++	      break;
++	    case 'l':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l));
++	      break;
++	    case 'm':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l));
++	      break;
++	    case 'n':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l));
++	      break;
++	    case 'K':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l));
++	      break;
++	    case 'L':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l));
++	      break;
++	    case 'M':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l));
++	      break;
++	    case 'N':
++	      print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l));
++	      break;
++	    case 'p':
++	      info->target = EXTRACT_RVC_B_IMM (l) + pc;
++	      (*info->print_address_func) (info->target, info);
++	      break;
++	    case 'a':
++	      info->target = EXTRACT_RVC_J_IMM (l) + pc;
++	      (*info->print_address_func) (info->target, info);
++	      break;
++	    case 'u':
++	      print (info->stream, "0x%x",
++		     (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
++	      break;
++	    case '>':
++	      print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
++	      break;
++	    case '<':
++	      print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
++	      break;
++	    }
++	  break;
++
 +	case ',':
 +	case '(':
 +	case ')':
@@ -8751,6 +8793,9 @@
 +	  break;
 +
 +	case '0':
++	  /* Only print constant 0 if it is the last argument */
++	  if (!d[1])
++	    print (info->stream, "0");
 +	  break;
 +
 +	case 'b':
@@ -8887,25 +8932,20 @@
 +{
 +  const struct riscv_opcode *op;
 +  static bfd_boolean init = 0;
-+  static const char *extension = NULL;
 +  static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
 +  struct riscv_private_data *pd;
 +  int insnlen;
 +
++#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : 0x7f))
++
 +  /* Build a hash table to shorten the search time.  */
 +  if (! init)
 +    {
-+      unsigned int i;
-+      unsigned int e_flags = elf_elfheader (info->section->owner)->e_flags;
-+      extension = riscv_elf_flag_to_name(EF_GET_RISCV_EXT(e_flags));
-+
-+      for (i = 0; i <= OP_MASK_OP; i++)
-+        for (op = riscv_opcodes; op < &riscv_opcodes[NUMOPCODES]; op++)
-+          if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
-+            {
-+              riscv_hash[i] = op;
-+              break;
-+            }
++      for (op = riscv_opcodes; op < &riscv_opcodes[NUMOPCODES]; op++)
++        {
++	  if (!riscv_hash[OP_HASH_IDX (op->match)])
++	    riscv_hash[OP_HASH_IDX (op->match)] = op;
++        }
 +
 +      init = 1;
 +    }
@@ -8914,7 +8954,7 @@
 +    {
 +      int i;
 +
-+      pd = info->private_data = calloc(1, sizeof (struct riscv_private_data));
++      pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
 +      pd->gp = -1;
 +      pd->print_addr = -1;
 +      for (i = 0; i < (int) ARRAY_SIZE(pd->hi_addr); i++)
@@ -8939,14 +8979,31 @@
 +  info->target = 0;
 +  info->target2 = 0;
 +
-+  op = riscv_hash[(word >> OP_SH_OP) & OP_MASK_OP];
++  op = riscv_hash[OP_HASH_IDX (word)];
 +  if (op != NULL)
 +    {
++      const char *extension = NULL;
++      int xlen = 0;
++
++      /* The incoming section might not always be complete.  */
++      if (info->section != NULL)
++	{
++	  Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
++	  unsigned int e_flags = ehdr->e_flags;
++	  extension = riscv_elf_flag_to_name (EF_GET_RISCV_EXT (e_flags));
++
++	  xlen = 32;
++	  if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
++	    xlen = 64;
++	}
++
 +      for (; op < &riscv_opcodes[NUMOPCODES]; op++)
 +	{
 +	  if ((op->match_func) (op, word)
 +	      && !(no_aliases && (op->pinfo & INSN_ALIAS))
-+	      && !(op->subset[0] == 'X' && strcmp(op->subset, extension)))
++	      && !(op->subset[0] == 'X' && extension != NULL
++		   && strcmp (op->subset, extension))
++	      && !(isdigit(op->subset[0]) && atoi(op->subset) != xlen))
 +	    {
 +	      (*info->fprintf_func) (info->stream, "%s", op->name);
 +	      print_insn_args (op->args, word, memaddr, info);
@@ -9020,10 +9077,10 @@
 +
 +  fprintf (stream, _("\n"));
 +}
-diff -urN original-binutils/opcodes/riscv-opc.c binutils/opcodes/riscv-opc.c
---- original-binutils/opcodes/riscv-opc.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/opcodes/riscv-opc.c	2015-03-07 09:51:45.659139025 +0100
-@@ -0,0 +1,729 @@
+diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
+--- empty/opcodes/riscv-opc.c	1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.25/opcodes/riscv-opc.c	2015-07-18 00:02:36.222287541 +0200
+@@ -0,0 +1,867 @@
 +/* RISC-V opcode list
 +   Copyright 2011-2014 Free Software Foundation, Inc.
 +
@@ -9121,6 +9178,7 @@
 +#define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
 +#define MASK_RD (OP_MASK_RD << OP_SH_RD)
 +#define MASK_IMM ENCODE_ITYPE_IMM(-1U)
++#define MASK_RVC_IMM ENCODE_RVC_IMM(-1U)
 +#define MASK_UIMM ENCODE_UTYPE_IMM(-1U)
 +#define MASK_RM (OP_MASK_RM << OP_SH_RM)
 +#define MASK_PRED (OP_MASK_PRED << OP_SH_PRED)
@@ -9131,7 +9189,7 @@
 +
 +static int match_opcode(const struct riscv_opcode *op, insn_t insn)
 +{
-+  return (insn & op->mask) == op->match;
++  return ((insn ^ op->match) & op->mask) == 0;
 +}
 +
 +static int match_never(const struct riscv_opcode *op ATTRIBUTE_UNUSED,
@@ -9146,38 +9204,92 @@
 +    ((insn & MASK_RS1) >> OP_SH_RS1) == ((insn & MASK_RS2) >> OP_SH_RS2);
 +}
 +
++static int match_rd_nonzero(const struct riscv_opcode *op, insn_t insn)
++{
++  return match_opcode(op, insn) && ((insn & MASK_RD) != 0);
++}
++
 +const struct riscv_opcode riscv_builtin_opcodes[] =
 +{
-+/* These instructions appear first so that the disassembler will find
-+   them first.  The assemblers uses a hash table based on the
-+   instruction name anyhow.  */
-+/* name,      isa,   operands, match, mask, pinfo */
-+{"unimp",     "I",   "",         0, 0xffff,  match_opcode, 0 },
++/* name,      isa,   operands, match, mask, match_func, pinfo */
++{"unimp",     "C",   "",  0, 0xffffU,  match_opcode, 0 },
++{"unimp",     "I",   "",  MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU,  match_opcode, 0 }, /* csrw cycle, x0 */
++{"ebreak",    "C",   "",  MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
++{"ebreak",    "I",   "",    MATCH_EBREAK, MASK_EBREAK, match_opcode,   0 },
++{"sbreak",    "C",   "",  MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
++{"sbreak",    "I",   "",    MATCH_EBREAK, MASK_EBREAK, match_opcode,   INSN_ALIAS },
++{"ret",       "C",   "",  MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS },
++{"ret",       "I",   "",  MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"jr",        "C",   "CD",  MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS },
++{"jr",        "I",   "s",  MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"jr",        "I",   "s,j",  MATCH_JALR, MASK_JALR | MASK_RD, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"jalr",      "C",   "CD",  MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS },
++{"jalr",      "I",   "s",  MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"jalr",      "I",   "s,j",  MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"jalr",      "I",   "d,s",  MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"jalr",      "I",   "d,s,j",  MATCH_JALR, MASK_JALR, match_opcode,   WR_xd|RD_xs1 },
++{"j",         "C",   "Ca",  MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS },
++{"j",         "I",   "a",  MATCH_JAL, MASK_JAL | MASK_RD, match_opcode,   INSN_ALIAS },
++{"jal",       "C",   "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
++{"jal",       "I",   "a",  MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode,   INSN_ALIAS|WR_xd },
++{"jal",       "I",   "d,a",  MATCH_JAL, MASK_JAL, match_opcode,   WR_xd },
++{"call",      "I",   "c", (X_T0 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
++{"call",      "I",   "d,c", (X_T0 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
++{"tail",      "I",   "c", (X_T0 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
++{"jump",      "I",   "c,s", 0, (int) M_CALL,  match_never, INSN_MACRO },
++{"nop",       "C",   "",  MATCH_C_ADDI16SP, 0xffff, match_opcode, INSN_ALIAS },
 +{"nop",       "I",   "",         MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode,  INSN_ALIAS },
++{"lui",       "C",   "CD,Cu",  MATCH_C_LUI, MASK_C_LUI, match_rd_nonzero, INSN_ALIAS },
++{"lui",       "I",   "d,u",  MATCH_LUI, MASK_LUI, match_opcode,   WR_xd },
++{"li",        "C",   "CD,Cv",  MATCH_C_LUI, MASK_C_LUI, match_rd_nonzero, INSN_ALIAS },
++{"li",        "C",   "CD,Cj",  MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
++{"li",        "C",   "CD,0",  MATCH_C_MV, MASK_C_MV | (OP_MASK_CRS2 << OP_SH_CRS2), match_rd_nonzero, INSN_ALIAS },
 +{"li",        "I",   "d,j",      MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode,  INSN_ALIAS|WR_xd }, /* addi */
 +{"li",        "I",   "d,I",  0,    (int) M_LI,  match_never, INSN_MACRO },
++{"mv",        "C",   "CD,CV",  MATCH_C_MV, MASK_C_MV, match_rd_nonzero, INSN_ALIAS },
 +{"mv",        "I",   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"move",      "C",   "CD,CV",  MATCH_C_MV, MASK_C_MV, match_rd_nonzero, INSN_ALIAS },
 +{"move",      "I",   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"andi",      "32C", "CD,CU,Cj",  MATCH_C_ANDI, MASK_C_ANDI, match_rd_nonzero, INSN_ALIAS },
++{"andi",      "32C", "Ct,Cs,Ci",  MATCH_C_ANDIN, MASK_C_ANDIN, match_opcode, INSN_ALIAS },
 +{"andi",      "I",   "d,s,j",  MATCH_ANDI, MASK_ANDI, match_opcode,   WR_xd|RD_xs1 },
++{"and",       "C",   "Cd,Cs,Ct",  MATCH_C_AND3, MASK_C_AND3, match_opcode, INSN_ALIAS },
++{"and",       "32C", "CD,CU,Cj",  MATCH_C_ANDI, MASK_C_ANDI, match_rd_nonzero, INSN_ALIAS },
++{"and",       "32C", "Ct,Cs,Ci",  MATCH_C_ANDIN, MASK_C_ANDIN, match_opcode, INSN_ALIAS },
 +{"and",       "I",   "d,s,t",  MATCH_AND, MASK_AND, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"and",       "I",   "d,s,j",  MATCH_ANDI, MASK_ANDI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"beqz",      "C",   "Cs,Cp",  MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS },
 +{"beqz",      "I",   "s,p",  MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode,   INSN_ALIAS|RD_xs1 },
 +{"beq",       "I",   "s,t,p",  MATCH_BEQ, MASK_BEQ, match_opcode,   RD_xs1|RD_xs2 },
 +{"blez",      "I",   "t,p",  MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode,   INSN_ALIAS|RD_xs2 },
++{"bgez",      "32C", "Cs,Cp",  MATCH_C_BGEZ, MASK_C_BGEZ, match_opcode, INSN_ALIAS },
 +{"bgez",      "I",   "s,p",  MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode,   INSN_ALIAS|RD_xs1 },
 +{"ble",       "I",   "t,s,p",  MATCH_BGE, MASK_BGE, match_opcode,   INSN_ALIAS|RD_xs1|RD_xs2 },
 +{"bleu",      "I",   "t,s,p",  MATCH_BGEU, MASK_BGEU, match_opcode,   INSN_ALIAS|RD_xs1|RD_xs2 },
 +{"bge",       "I",   "s,t,p",  MATCH_BGE, MASK_BGE, match_opcode,   RD_xs1|RD_xs2 },
 +{"bgeu",      "I",   "s,t,p",  MATCH_BGEU, MASK_BGEU, match_opcode,   RD_xs1|RD_xs2 },
++{"bltz",      "32C", "Cs,Cp",  MATCH_C_BLTZ, MASK_C_BLTZ, match_opcode, INSN_ALIAS },
 +{"bltz",      "I",   "s,p",  MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode,   INSN_ALIAS|RD_xs1 },
 +{"bgtz",      "I",   "t,p",  MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode,   INSN_ALIAS|RD_xs2 },
 +{"blt",       "I",   "s,t,p",  MATCH_BLT, MASK_BLT, match_opcode,   RD_xs1|RD_xs2 },
 +{"bltu",      "I",   "s,t,p",  MATCH_BLTU, MASK_BLTU, match_opcode,   RD_xs1|RD_xs2 },
 +{"bgt",       "I",   "t,s,p",  MATCH_BLT, MASK_BLT, match_opcode,   INSN_ALIAS|RD_xs1|RD_xs2 },
 +{"bgtu",      "I",   "t,s,p",  MATCH_BLTU, MASK_BLTU, match_opcode,   INSN_ALIAS|RD_xs1|RD_xs2 },
++{"bnez",      "C",   "Cs,Cp",  MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS },
 +{"bnez",      "I",   "s,p",  MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode,   INSN_ALIAS|RD_xs1 },
 +{"bne",       "I",   "s,t,p",  MATCH_BNE, MASK_BNE, match_opcode,   RD_xs1|RD_xs2 },
++{"addi",      "C",   "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS },
++{"addi",      "C",   "CD,CU,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
++{"addi",      "C",   "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS },
++{"addi",      "32C", "Ct,Cs,Ci",  MATCH_C_ADDIN, MASK_C_ADDIN, match_opcode, INSN_ALIAS },
 +{"addi",      "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode,  WR_xd|RD_xs1 },
++{"add",       "C",   "CD,CU,CT",  MATCH_C_ADD, MASK_C_ADD, match_rd_nonzero, INSN_ALIAS },
++{"add",       "C",   "CD,CT,CU",  MATCH_C_ADD, MASK_C_ADD, match_rd_nonzero, INSN_ALIAS },
++{"add",       "C",   "CD,CU,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
++{"add",       "C",   "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS },
++{"add",       "C",   "Cd,Cs,Ct",  MATCH_C_ADD3, MASK_C_ADD3, match_opcode, INSN_ALIAS },
++{"add",       "C",   "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS },
++{"add",       "32C", "Ct,Cs,Ci",  MATCH_C_ADDIN, MASK_C_ADDIN, match_opcode, INSN_ALIAS },
 +{"add",       "I",   "d,s,t",  MATCH_ADD, MASK_ADD, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
 +{"add",       "I",   "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
 +{"add",       "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode,  INSN_ALIAS|WR_xd|RD_xs1 },
@@ -9186,29 +9298,29 @@
 +{"la.tls.gd", "I",   "d,A",  0,    (int) M_LA_TLS_GD,  match_never, INSN_MACRO },
 +{"la.tls.ie", "I",   "d,A",  0,    (int) M_LA_TLS_IE,  match_never, INSN_MACRO },
 +{"neg",       "I",   "d,t",  MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode,   INSN_ALIAS|WR_xd|RD_xs2 }, /* sub 0 */
++{"slli",      "C",   "CD,CU,C>",  MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
 +{"slli",      "I",   "d,s,>",   MATCH_SLLI, MASK_SLLI, match_opcode,   WR_xd|RD_xs1 },
++{"sll",       "C",   "CD,CU,C>",  MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
++{"sll",       "32C", "Cs,Cw,Ct",  MATCH_C_SLL, MASK_C_SLL, match_opcode, INSN_ALIAS },
++{"sll",       "32C", "Ct,Cs,Cx",  MATCH_C_SLLR, MASK_C_SLLR, match_opcode, INSN_ALIAS },
 +{"sll",       "I",   "d,s,t",   MATCH_SLL, MASK_SLL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"sll",       "I",   "d,s,>",   MATCH_SLLI, MASK_SLLI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"srli",      "C",   "CD,CU,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
 +{"srli",      "I",   "d,s,>",   MATCH_SRLI, MASK_SRLI, match_opcode,   WR_xd|RD_xs1 },
++{"srl",       "C",   "CD,CU,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
++{"srl",       "32C", "Cs,Cw,Ct",  MATCH_C_SRL, MASK_C_SRL, match_opcode, INSN_ALIAS },
++{"srl",       "32C", "Ct,Cs,Cx",  MATCH_C_SRLR, MASK_C_SRLR, match_opcode, INSN_ALIAS },
 +{"srl",       "I",   "d,s,t",   MATCH_SRL, MASK_SRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"srl",       "I",   "d,s,>",   MATCH_SRLI, MASK_SRLI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"srai",      "C",   "CD,CU,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
 +{"srai",      "I",   "d,s,>",   MATCH_SRAI, MASK_SRAI, match_opcode,   WR_xd|RD_xs1 },
++{"sra",       "C",   "CD,CU,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
++{"sra",       "32C", "Cs,Cw,Ct",  MATCH_C_SRA, MASK_C_SRA, match_opcode, INSN_ALIAS },
 +{"sra",       "I",   "d,s,t",   MATCH_SRA, MASK_SRA, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"sra",       "I",   "d,s,>",   MATCH_SRAI, MASK_SRAI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"sub",       "C",   "CD,CU,CT",  MATCH_C_SUB, MASK_C_SUB, match_rd_nonzero, INSN_ALIAS },
++{"sub",       "C",   "Cd,Cs,Ct",  MATCH_C_SUB3, MASK_C_SUB3, match_opcode, INSN_ALIAS },
 +{"sub",       "I",   "d,s,t",  MATCH_SUB, MASK_SUB, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"ret",       "I",   "",  MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"j",         "I",   "a",  MATCH_JAL, MASK_JAL | MASK_RD, match_opcode,   INSN_ALIAS },
-+{"jal",       "I",   "a",  MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode,   INSN_ALIAS|WR_xd },
-+{"jal",       "I",   "d,a",  MATCH_JAL, MASK_JAL, match_opcode,   WR_xd },
-+{"call",      "I",   "c", (X_T0 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
-+{"tail",      "I",   "c", (X_T0 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
-+{"jump",      "I",   "c,s", 0, (int) M_CALL,  match_never, INSN_MACRO },
-+{"jr",        "I",   "s",  MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jr",        "I",   "s,j",  MATCH_JALR, MASK_JALR | MASK_RD, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr",      "I",   "s",  MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr",      "I",   "s,j",  MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr",      "I",   "d,s",  MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr",      "I",   "d,s,j",  MATCH_JALR, MASK_JALR, match_opcode,   WR_xd|RD_xs1 },
 +{"lb",        "I",   "d,o(s)",  MATCH_LB, MASK_LB, match_opcode,   WR_xd|RD_xs1 },
 +{"lb",        "I",   "d,A",  0, (int) M_LB, match_never, INSN_MACRO },
 +{"lbu",       "I",   "d,o(s)",  MATCH_LBU, MASK_LBU, match_opcode,   WR_xd|RD_xs1 },
@@ -9217,11 +9329,15 @@
 +{"lh",        "I",   "d,A",  0, (int) M_LH, match_never, INSN_MACRO },
 +{"lhu",       "I",   "d,o(s)",  MATCH_LHU, MASK_LHU, match_opcode,   WR_xd|RD_xs1 },
 +{"lhu",       "I",   "d,A",  0, (int) M_LHU, match_never, INSN_MACRO },
++{"lw",        "C",   "CD,Cm(Cc)",  MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS },
++{"lw",        "C",   "Ct,Ck(Cs)",  MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS },
 +{"lw",        "I",   "d,o(s)",  MATCH_LW, MASK_LW, match_opcode,   WR_xd|RD_xs1 },
 +{"lw",        "I",   "d,A",  0, (int) M_LW, match_never, INSN_MACRO },
-+{"lui",       "I",   "d,u",  MATCH_LUI, MASK_LUI, match_opcode,   WR_xd },
 +{"not",       "I",   "d,s",  MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"ori",       "32C", "Ct,Cs,Ci",  MATCH_C_ORIN, MASK_C_ORIN, match_opcode, INSN_ALIAS },
 +{"ori",       "I",   "d,s,j",  MATCH_ORI, MASK_ORI, match_opcode,   WR_xd|RD_xs1 },
++{"or",        "C",   "Cd,Cs,Ct",  MATCH_C_OR3, MASK_C_OR3, match_opcode, INSN_ALIAS },
++{"or",        "32C", "Ct,Cs,Ci",  MATCH_C_ORIN, MASK_C_ORIN, match_opcode, INSN_ALIAS },
 +{"or",        "I",   "d,s,t",  MATCH_OR, MASK_OR, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"or",        "I",   "d,s,j",  MATCH_ORI, MASK_ORI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
 +{"auipc",     "I",   "d,u",  MATCH_AUIPC, MASK_AUIPC, match_opcode,  WR_xd },
@@ -9230,9 +9346,13 @@
 +{"sltz",      "I",   "d,s",  MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
 +{"sgtz",      "I",   "d,t",  MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode,   INSN_ALIAS|WR_xd|RD_xs2 },
 +{"slti",      "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"slt",       "32C", "Cs,Cw,Ct",  MATCH_C_SLT, MASK_C_SLT, match_opcode, INSN_ALIAS },
++{"slt",       "32C", "Ct,Cs,Cx",  MATCH_C_SLTR, MASK_C_SLTR, match_opcode, INSN_ALIAS },
 +{"slt",       "I",   "d,s,t",  MATCH_SLT, MASK_SLT, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"slt",       "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode,   WR_xd|RD_xs1 },
 +{"sltiu",     "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode,   WR_xd|RD_xs1 },
++{"sltu",      "32C", "Cs,Cw,Ct",  MATCH_C_SLTU, MASK_C_SLTU, match_opcode, INSN_ALIAS },
++{"sltu",      "32C", "Ct,Cs,Cx",  MATCH_C_SLTUR, MASK_C_SLTUR, match_opcode, INSN_ALIAS },
 +{"sltu",      "I",   "d,s,t",  MATCH_SLTU, MASK_SLTU, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"sltu",      "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
 +{"sgt",       "I",   "d,t,s",  MATCH_SLT, MASK_SLT, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1|RD_xs2 },
@@ -9241,6 +9361,8 @@
 +{"sb",        "I",   "t,A,s",  0, (int) M_SB, match_never,  INSN_MACRO },
 +{"sh",        "I",   "t,q(s)",  MATCH_SH, MASK_SH, match_opcode,   RD_xs1|RD_xs2 },
 +{"sh",        "I",   "t,A,s",  0, (int) M_SH, match_never,  INSN_MACRO },
++{"sw",        "C",   "CV,CM(Cc)",  MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS },
++{"sw",        "C",   "Ct,Ck(Cs)",  MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS },
 +{"sw",        "I",   "t,q(s)",  MATCH_SW, MASK_SW, match_opcode,   RD_xs1|RD_xs2 },
 +{"sw",        "I",   "t,A,s",  0, (int) M_SW, match_never,  INSN_MACRO },
 +{"fence",     "I",   "",  MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode,   INSN_ALIAS },
@@ -9252,23 +9374,38 @@
 +{"rdcycleh",  "32I", "d",  MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode,  WR_xd },
 +{"rdinstreth","32I", "d",  MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode,  WR_xd },
 +{"rdtimeh",   "32I", "d",  MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode,  WR_xd },
-+{"sbreak",    "I",   "",    MATCH_SBREAK, MASK_SBREAK, match_opcode,   0 },
++{"ecall",     "I",   "",    MATCH_SCALL, MASK_SCALL, match_opcode,   0 },
 +{"scall",     "I",   "",    MATCH_SCALL, MASK_SCALL, match_opcode,   0 },
++{"xori",      "32C", "Ct,Cs,Ci",  MATCH_C_XORIN, MASK_C_XORIN, match_opcode, INSN_ALIAS },
 +{"xori",      "I",   "d,s,j",  MATCH_XORI, MASK_XORI, match_opcode,   WR_xd|RD_xs1 },
++{"xor",       "32C", "Cs,Cw,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
++{"xor",       "32C", "Cs,Ct,Cw",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
++{"xor",       "32C", "Ct,Cs,Ci",  MATCH_C_XORIN, MASK_C_XORIN, match_opcode, INSN_ALIAS },
 +{"xor",       "I",   "d,s,t",  MATCH_XOR, MASK_XOR, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"xor",       "I",   "d,s,j",  MATCH_XORI, MASK_XORI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
 +{"lwu",       "64I", "d,o(s)",  MATCH_LWU, MASK_LWU, match_opcode,   WR_xd|RD_xs1 },
 +{"lwu",       "64I", "d,A",  0, (int) M_LWU, match_never, INSN_MACRO },
++{"ld",        "64C", "CD,Cn(Cc)",  MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS },
++{"ld",        "64C", "Ct,Cl(Cs)",  MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS },
 +{"ld",        "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode,  WR_xd|RD_xs1 },
 +{"ld",        "64I", "d,A",  0, (int) M_LD, match_never, INSN_MACRO },
++{"sd",        "64C", "CV,CN(Cc)",  MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS },
++{"sd",        "64C", "Ct,Cl(Cs)",  MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS },
 +{"sd",        "64I", "t,q(s)",  MATCH_SD, MASK_SD, match_opcode,   RD_xs1|RD_xs2 },
 +{"sd",        "64I", "t,A,s",  0, (int) M_SD, match_never,  INSN_MACRO },
++{"sext.w",    "64C", "CD,CU",  MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
 +{"sext.w",    "64I", "d,s",  MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"addiw",     "64C", "CD,CU,Cj",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
 +{"addiw",     "64I", "d,s,j",  MATCH_ADDIW, MASK_ADDIW, match_opcode,   WR_xd|RD_xs1 },
++{"addw",      "64C", "CD,CU,CT",  MATCH_C_ADDW, MASK_C_ADDW, match_rd_nonzero, INSN_ALIAS },
++{"addw",      "64C", "CD,CT,CU",  MATCH_C_ADDW, MASK_C_ADDW, match_rd_nonzero, INSN_ALIAS },
++{"addw",      "64C", "CD,CU,Cj",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
 +{"addw",      "64I", "d,s,t",  MATCH_ADDW, MASK_ADDW, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"addw",      "64I", "d,s,j",  MATCH_ADDIW, MASK_ADDIW, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
 +{"negw",      "64I", "d,t",  MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode,   INSN_ALIAS|WR_xd|RD_xs2 }, /* sub 0 */
++{"slliw",     "64C",   "CD,CU,C<",  MATCH_C_SLLIW, MASK_C_SLLIW, match_rd_nonzero, INSN_ALIAS },
 +{"slliw",     "64I", "d,s,<",   MATCH_SLLIW, MASK_SLLIW, match_opcode,   WR_xd|RD_xs1 },
++{"sllw",      "64C",   "CD,CU,C<",  MATCH_C_SLLIW, MASK_C_SLLIW, match_rd_nonzero, INSN_ALIAS },
 +{"sllw",      "64I", "d,s,t",   MATCH_SLLW, MASK_SLLW, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +{"sllw",      "64I", "d,s,<",   MATCH_SLLIW, MASK_SLLIW, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
 +{"srliw",     "64I", "d,s,<",   MATCH_SRLIW, MASK_SRLIW, match_opcode,   WR_xd|RD_xs1 },
@@ -9279,6 +9416,59 @@
 +{"sraw",      "64I", "d,s,<",   MATCH_SRAIW, MASK_SRAIW, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
 +{"subw",      "64I", "d,s,t",  MATCH_SUBW, MASK_SUBW, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
 +
++/* Compressed instructions */
++{"c.ebreak",  "C",   "",  MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
++{"c.jr",      "C",   "CD",  MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 },
++{"c.jalr",    "C",   "CD",  MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, 0 },
++{"c.j",       "C",   "Ca",  MATCH_C_J, MASK_C_J, match_opcode, 0 },
++{"c.jal",     "C",   "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, 0 },
++{"c.beqz",    "C",   "Cs,Cp",  MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, 0 },
++{"c.bnez",    "C",   "Cs,Cp",  MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, 0 },
++{"c.lwsp",    "C",   "CD,Cm(Cc)",  MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 },
++{"c.lw",      "C",   "Ct,Ck(Cs)",  MATCH_C_LW, MASK_C_LW, match_opcode, 0 },
++{"c.swsp",    "C",   "CV,CM(Cc)",  MATCH_C_SWSP, MASK_C_SWSP, match_opcode, 0 },
++{"c.sw",      "C",   "Ct,Ck(Cs)",  MATCH_C_SW, MASK_C_SW, match_opcode, 0 },
++{"c.nop",     "C",   "",  MATCH_C_ADDI16SP, 0xffff, match_opcode, 0 },
++{"c.mv",      "C",   "CD,CV",  MATCH_C_MV, MASK_C_MV, match_rd_nonzero, 0 },
++{"c.lui",     "C",   "CD,Cu",  MATCH_C_LUI, MASK_C_LUI, match_rd_nonzero, 0 },
++{"c.li",      "C",   "CD,Cj",  MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
++{"c.addi4spn","C",   "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 },
++{"c.addi16sp","C",   "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 },
++{"c.addi",    "C",   "CD,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 },
++{"c.add",     "C",   "CD,CT",  MATCH_C_ADD, MASK_C_ADD, match_rd_nonzero, 0 },
++{"c.sub",     "C",   "CD,CT",  MATCH_C_SUB, MASK_C_SUB, match_rd_nonzero, 0 },
++{"c.add3",    "C",   "Cd,Cs,Ct",  MATCH_C_ADD3, MASK_C_ADD3, match_opcode, 0 },
++{"c.sub3",    "C",   "Cd,Cs,Ct",  MATCH_C_SUB3, MASK_C_SUB3, match_opcode, 0 },
++{"c.and3",    "C",   "Cd,Cs,Ct",  MATCH_C_AND3, MASK_C_AND3, match_opcode, 0 },
++{"c.or3",     "C",   "Cd,Cs,Ct",  MATCH_C_OR3, MASK_C_OR3, match_opcode, 0 },
++{"c.slli",    "C",   "CD,C>",  MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 },
++{"c.srli",    "C",   "CD,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, 0 },
++{"c.srai",    "C",   "CD,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, 0 },
++{"c.slliw",   "64C", "CD,CU,C<",  MATCH_C_SLLIW, MASK_C_SLLIW, match_rd_nonzero, 0 },
++{"c.addiw",   "64C", "CD,Cj",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
++{"c.addw",    "64C", "CD,CT",  MATCH_C_ADDW, MASK_C_ADDW, match_rd_nonzero, 0 },
++{"c.ldsp",    "64C", "CD,Cn(Cc)",  MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 },
++{"c.ld",      "64C", "Ct,Cl(Cs)",  MATCH_C_LD, MASK_C_LD, match_opcode, 0 },
++{"c.sdsp",    "64C", "CV,CN(Cc)",  MATCH_C_SDSP, MASK_C_SDSP, match_opcode, 0 },
++{"c.sd",      "64C", "Ct,Cl(Cs)",  MATCH_C_SD, MASK_C_SD, match_opcode, 0 },
++{"c.xor",     "32C", "Cs,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 },
++{"c.sra",     "32C", "Cs,Ct",  MATCH_C_SRA, MASK_C_SRA, match_opcode, 0 },
++{"c.sll",     "32C", "Cs,Ct",  MATCH_C_SLL, MASK_C_SLL, match_opcode, 0 },
++{"c.srl",     "32C", "Cs,Ct",  MATCH_C_SRL, MASK_C_SRL, match_opcode, 0 },
++{"c.slt",     "32C", "Cs,Ct",  MATCH_C_SLT, MASK_C_SLT, match_opcode, 0 },
++{"c.sltu",    "32C", "Cs,Ct",  MATCH_C_SLTU, MASK_C_SLTU, match_opcode, 0 },
++{"c.sllr",    "32C", "Ct,Cs",  MATCH_C_SLLR, MASK_C_SLLR, match_opcode, 0 },
++{"c.srlr",    "32C", "Ct,Cs",  MATCH_C_SRLR, MASK_C_SRLR, match_opcode, 0 },
++{"c.sltr",    "32C", "Ct,Cs",  MATCH_C_SLTR, MASK_C_SLTR, match_opcode, 0 },
++{"c.sltur",   "32C", "Ct,Cs",  MATCH_C_SLTUR, MASK_C_SLTUR, match_opcode, 0 },
++{"c.addin",   "32C", "Ct,Cs,Ci",  MATCH_C_ADDIN, MASK_C_ADDIN, match_opcode, 0 },
++{"c.xorin",   "32C", "Ct,Cs,Ci",  MATCH_C_XORIN, MASK_C_XORIN, match_opcode, 0 },
++{"c.orin",    "32C", "Ct,Cs,Ci",  MATCH_C_ORIN, MASK_C_ORIN, match_opcode, 0 },
++{"c.andin",   "32C", "Ct,Cs,Ci",  MATCH_C_ANDIN, MASK_C_ANDIN, match_opcode, 0 },
++{"c.andi",    "32C", "CD,Cj",  MATCH_C_ANDI, MASK_C_ANDI, match_rd_nonzero, 0 },
++{"c.bltz",    "32C", "Cs,Cp",  MATCH_C_BLTZ, MASK_C_BLTZ, match_opcode, 0 },
++{"c.bgez",    "32C", "Cs,Cp",  MATCH_C_BGEZ, MASK_C_BGEZ, match_opcode, 0 },
++
 +/* Atomic memory operation instruction subset */
 +{"lr.w",         "A",   "d,0(s)",    MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1 },
 +{"sc.w",         "A",   "d,t,0(s)",  MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
@@ -9529,7 +9719,12 @@
 +{"csrrwi",    "I",   "d,E,Z",  MATCH_CSRRWI, MASK_CSRRWI, match_opcode,  WR_xd|RD_xs1 },
 +{"csrrsi",    "I",   "d,E,Z",  MATCH_CSRRSI, MASK_CSRRSI, match_opcode,  WR_xd|RD_xs1 },
 +{"csrrci",    "I",   "d,E,Z",  MATCH_CSRRCI, MASK_CSRRCI, match_opcode,  WR_xd|RD_xs1 },
++{"eret",      "I",   "",     MATCH_SRET, MASK_SRET, match_opcode,  0 },
 +{"sret",      "I",   "",     MATCH_SRET, MASK_SRET, match_opcode,  0 },
++{"mrts",      "I",   "",     MATCH_MRTS, MASK_MRTS, match_opcode,  0 },
++{"sfence.vm", "I",   "",     MATCH_SFENCE_VM | MASK_RS1, MASK_SFENCE_VM | MASK_RS1, match_opcode,  0 },
++{"sfence.vm", "I",   "s",    MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode,  RD_xs1 },
++{"wfi",       "I",   "",     MATCH_WFI, MASK_WFI, match_opcode,  0 },
 +
 +/* Half-precision floating-point instruction subset */
 +{"flh",       "Xhwacha",   "D,o(s)",  MATCH_FLH, MASK_FLH, match_opcode, WR_fd|RD_xs1 },
@@ -9736,7 +9931,7 @@
 +{"vxcptkill",    "Xhwacha", "", MATCH_VXCPTKILL, MASK_VXCPTKILL, match_opcode, 0},
 +
 +{"vxcptevac",    "Xhwacha", "s", MATCH_VXCPTEVAC, MASK_VXCPTEVAC, match_opcode, 0},
-+{"vxcpthold",    "Xhwacha", "", MATCH_VXCPTHOLD, MASK_VXCPTHOLD, match_opcode, 0},
++{"vxcpthold",    "Xhwacha", "s", MATCH_VXCPTHOLD, MASK_VXCPTHOLD, match_opcode, 0},
 +{"venqcmd",      "Xhwacha", "s,t", MATCH_VENQCMD, MASK_VENQCMD, match_opcode, 0},
 +{"venqimm1",     "Xhwacha", "s,t", MATCH_VENQIMM1, MASK_VENQIMM1, match_opcode, 0},
 +{"venqimm2",     "Xhwacha", "s,t", MATCH_VENQIMM2, MASK_VENQIMM2, match_opcode, 0},
@@ -9753,3 +9948,594 @@
 +  (struct riscv_opcode *) riscv_builtin_opcodes;
 +int bfd_riscv_num_opcodes = RISCV_NUM_OPCODES;
 +#undef RISCV_NUM_OPCODES
+--- original-binutils/bfd/archures.c
++++ binutils-2.25/bfd/archures.c
+@@ -597,6 +597,7 @@ extern const bfd_arch_info_type bfd_pj_a
+ extern const bfd_arch_info_type bfd_plugin_arch;
+ extern const bfd_arch_info_type bfd_powerpc_archs[];
+ #define bfd_powerpc_arch bfd_powerpc_archs[0]
++extern const bfd_arch_info_type bfd_riscv_arch;
+ extern const bfd_arch_info_type bfd_rs6000_arch;
+ extern const bfd_arch_info_type bfd_rl78_arch;
+ extern const bfd_arch_info_type bfd_rx_arch;
+@@ -683,6 +684,7 @@ static const bfd_arch_info_type * const
+     &bfd_or1k_arch,
+     &bfd_pdp11_arch,
+     &bfd_powerpc_arch,
++    &bfd_riscv_arch,
+     &bfd_rs6000_arch,
+     &bfd_rl78_arch,
+     &bfd_rx_arch,
+--- original-binutils/bfd/bfd-in2.h
++++ binutils-2.25/bfd/bfd-in2.h
+@@ -2043,6 +2043,9 @@ enum bfd_architecture
+ #define bfd_mach_ppc_e6500     5007
+ #define bfd_mach_ppc_titan     83
+ #define bfd_mach_ppc_vle       84
++  bfd_arch_riscv, /* RISC-V */
++#define bfd_mach_riscv32 132
++#define bfd_mach_riscv64 164
+   bfd_arch_rs6000,    /* IBM RS/6000 */
+ #define bfd_mach_rs6k          6000
+ #define bfd_mach_rs6k_rs1      6001
+@@ -5531,6 +5534,43 @@ relative offset from _GLOBAL_OFFSET_TABL
+ value in a word.  The relocation is relative offset from  */
+   BFD_RELOC_MICROBLAZE_32_GOTOFF,
+ 
++/* RISC-V relocations */
++  BFD_RELOC_RISCV_HI20,
++  BFD_RELOC_RISCV_PCREL_HI20,
++  BFD_RELOC_RISCV_PCREL_LO12_I,
++  BFD_RELOC_RISCV_PCREL_LO12_S,
++  BFD_RELOC_RISCV_LO12_I,
++  BFD_RELOC_RISCV_LO12_S,
++  BFD_RELOC_RISCV_GPREL12_I,
++  BFD_RELOC_RISCV_GPREL12_S,
++  BFD_RELOC_RISCV_TPREL_HI20,
++  BFD_RELOC_RISCV_TPREL_LO12_I,
++  BFD_RELOC_RISCV_TPREL_LO12_S,
++  BFD_RELOC_RISCV_TPREL_ADD,
++  BFD_RELOC_RISCV_CALL,
++  BFD_RELOC_RISCV_CALL_PLT,
++  BFD_RELOC_RISCV_ADD8,
++  BFD_RELOC_RISCV_ADD16,
++  BFD_RELOC_RISCV_ADD32,
++  BFD_RELOC_RISCV_ADD64,
++  BFD_RELOC_RISCV_SUB8,
++  BFD_RELOC_RISCV_SUB16,
++  BFD_RELOC_RISCV_SUB32,
++  BFD_RELOC_RISCV_SUB64,
++  BFD_RELOC_RISCV_GOT_HI20,
++  BFD_RELOC_RISCV_TLS_GOT_HI20,
++  BFD_RELOC_RISCV_TLS_GD_HI20,
++  BFD_RELOC_RISCV_JMP,
++  BFD_RELOC_RISCV_TLS_DTPMOD32,
++  BFD_RELOC_RISCV_TLS_DTPREL32,
++  BFD_RELOC_RISCV_TLS_DTPMOD64,
++  BFD_RELOC_RISCV_TLS_DTPREL64,
++  BFD_RELOC_RISCV_TLS_TPREL32,
++  BFD_RELOC_RISCV_TLS_TPREL64,
++  BFD_RELOC_RISCV_ALIGN,
++  BFD_RELOC_RISCV_RVC_BRANCH,
++  BFD_RELOC_RISCV_RVC_JUMP,
++
+ /* This is used to tell the dynamic linker to copy the value out of
+ the dynamic object into the runtime process image.  */
+   BFD_RELOC_MICROBLAZE_COPY,
+--- original-binutils/bfd/config.bfd
++++ binutils-2.25/bfd/config.bfd
+@@ -119,6 +119,7 @@ or1k*|or1knd*)	 targ_archs=bfd_or1k_arch
+ pdp11*)		 targ_archs=bfd_pdp11_arch ;;
+ pj*)		 targ_archs="bfd_pj_arch bfd_i386_arch";;
+ powerpc*)	 targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
++riscv*)		 targ_archs=bfd_riscv_arch ;;
+ rs6000)		 targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
+ s390*)		 targ_archs=bfd_s390_arch ;;
+ sh*)		 targ_archs=bfd_sh_arch ;;
+@@ -1319,6 +1320,14 @@ case "${targ}" in
+     targ_defvec=rl78_elf32_vec
+     ;;
+ 
++#ifdef BFD64
++  riscv*-*-*)
++    targ_defvec=riscv_elf64_vec
++    targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
++    want64=true
++    ;;
++#endif
++
+   rx-*-elf)
+     targ_defvec=rx_elf32_le_vec
+     targ_selvecs="rx_elf32_be_vec rx_elf32_le_vec rx_elf32_be_ns_vec"
+--- original-binutils/bfd/configure
++++ binutils-2.25/bfd/configure
+@@ -15506,6 +15506,8 @@ do
+     powerpc_pei_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
+     powerpc_pei_le_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
+     powerpc_xcoff_vec)		 tb="$tb coff-rs6000.lo xcofflink.lo" ;;
++    riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
++    riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
+     rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
+     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
+     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
+--- original-binutils/bfd/configure.ac
++++ binutils-2.25/bfd/configure.ac
+@@ -907,6 +907,8 @@ do
+     powerpc_pei_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
+     powerpc_pei_le_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
+     powerpc_xcoff_vec)		 tb="$tb coff-rs6000.lo xcofflink.lo" ;;
++    riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
++    riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
+     rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
+     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
+     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
+--- original-binutils/bfd/elf-bfd.h
++++ binutils-2.25/bfd/elf-bfd.h
+@@ -433,6 +433,7 @@ enum elf_target_id
+   XGATE_ELF_DATA,
+   TILEGX_ELF_DATA,
+   TILEPRO_ELF_DATA,
++  RISCV_ELF_DATA,
+   GENERIC_ELF_DATA
+ };
+ 
+--- original-binutils/bfd/Makefile.am
++++ binutils-2.25/bfd/Makefile.am
+@@ -931,6 +931,18 @@ elf64-ia64.c : elfnn-ia64.c
+ 	sed -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
+ 	mv -f elf64-ia64.new elf64-ia64.c
+ 
++elf32-riscv.c : elfnn-riscv.c
++	rm -f elf32-riscv.c
++	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new
++	sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new
++	mv -f elf32-riscv.new elf32-riscv.c
++
++elf64-riscv.c : elfnn-riscv.c
++	rm -f elf64-riscv.c
++	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new
++	sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new
++	mv -f elf64-riscv.new elf64-riscv.c
++
+ peigen.c : peXXigen.c
+ 	rm -f peigen.c
+ 	sed -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
+--- original-binutils/bfd/Makefile.in
++++ binutils-2.25/bfd/Makefile.in
+@@ -2009,6 +2009,18 @@ elf64-ia64.c : elfnn-ia64.c
+ 	sed -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
+ 	mv -f elf64-ia64.new elf64-ia64.c
+ 
++elf32-riscv.c : elfnn-riscv.c
++	rm -f elf32-riscv.c
++	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new
++	sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new
++	mv -f elf32-riscv.new elf32-riscv.c
++
++elf64-riscv.c : elfnn-riscv.c
++	rm -f elf64-riscv.c
++	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new
++	sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new
++	mv -f elf64-riscv.new elf64-riscv.c
++
+ peigen.c : peXXigen.c
+ 	rm -f peigen.c
+ 	sed -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
+--- original-binutils/bfd/targets.c
++++ binutils-2.25/bfd/targets.c
+@@ -784,6 +784,8 @@ extern const bfd_target powerpc_pe_le_ve
+ extern const bfd_target powerpc_pei_vec;
+ extern const bfd_target powerpc_pei_le_vec;
+ extern const bfd_target powerpc_xcoff_vec;
++extern const bfd_target riscv_elf32_vec;
++extern const bfd_target riscv_elf64_vec;
+ extern const bfd_target rl78_elf32_vec;
+ extern const bfd_target rs6000_xcoff64_vec;
+ extern const bfd_target rs6000_xcoff64_aix_vec;
+--- original-binutils/binutils/readelf.c
++++ binutils-2.25/binutils/readelf.c
+@@ -125,6 +125,7 @@
+ #include "elf/metag.h"
+ #include "elf/microblaze.h"
+ #include "elf/mips.h"
++#include "elf/riscv.h"
+ #include "elf/mmix.h"
+ #include "elf/mn10200.h"
+ #include "elf/mn10300.h"
+@@ -720,6 +721,7 @@ guess_is_rela (unsigned int e_machine)
+     case EM_OR1K:
+     case EM_PPC64:
+     case EM_PPC:
++    case EM_RISCV:
+     case EM_RL78:
+     case EM_RX:
+     case EM_S390:
+@@ -1252,6 +1254,10 @@ dump_relocations (FILE * file,
+ 	  rtype = elf_mips_reloc_type (type);
+ 	  break;
+ 
++	case EM_RISCV:
++	  rtype = elf_riscv_reloc_type (type);
++	  break;
++
+ 	case EM_ALPHA:
+ 	  rtype = elf_alpha_reloc_type (type);
+ 	  break;
+@@ -2164,6 +2170,7 @@ get_machine_name (unsigned e_machine)
+     case EM_CR16:
+     case EM_MICROBLAZE:
+     case EM_MICROBLAZE_OLD:	return "Xilinx MicroBlaze";
++    case EM_RISCV:		return "RISC-V";
+     case EM_RL78:		return "Renesas RL78";
+     case EM_RX:			return "Renesas RX";
+     case EM_METAG:		return "Imagination Technologies Meta processor architecture";
+@@ -2951,6 +2958,18 @@ get_machine_flags (unsigned e_flags, uns
+ 	  decode_NDS32_machine_flags (e_flags, buf, sizeof buf);
+ 	  break;
+ 
++	case EM_RISCV:
++          {
++	    if (e_flags & EF_RISCV_RVC)
++	      strcat (buf, ", RVC");
++
++	    if (!EF_GET_RISCV_EXT (e_flags))
++	      break;
++	    strcat (buf, ", ");
++	    strcat (buf, riscv_elf_flag_to_name (EF_GET_RISCV_EXT (e_flags)));
++          }
++	  break;
++
+ 	case EM_SH:
+ 	  switch ((e_flags & EF_SH_MACH_MASK))
+ 	    {
+@@ -10789,6 +10808,8 @@ is_32bit_abs_reloc (unsigned int reloc_t
+       return reloc_type == 1; /* R_PPC64_ADDR32.  */
+     case EM_PPC:
+       return reloc_type == 1; /* R_PPC_ADDR32.  */
++    case EM_RISCV:
++      return reloc_type == 1; /* R_RISCV_32.  */
+     case EM_RL78:
+       return reloc_type == 1; /* R_RL78_DIR32.  */
+     case EM_RX:
+@@ -10924,6 +10945,8 @@ is_64bit_abs_reloc (unsigned int reloc_t
+       return reloc_type == 80; /* R_PARISC_DIR64.  */
+     case EM_PPC64:
+       return reloc_type == 38; /* R_PPC64_ADDR64.  */
++    case EM_RISCV:
++      return reloc_type == 2; /* R_RISCV_64.  */
+     case EM_SPARC32PLUS:
+     case EM_SPARCV9:
+     case EM_SPARC:
+@@ -11072,6 +11095,7 @@ is_none_reloc (unsigned int reloc_type)
+     case EM_ADAPTEVA_EPIPHANY:
+     case EM_PPC:     /* R_PPC_NONE.  */
+     case EM_PPC64:   /* R_PPC64_NONE.  */
++    case EM_RISCV:   /* R_RISCV_NONE.  */
+     case EM_ARM:     /* R_ARM_NONE.  */
+     case EM_IA_64:   /* R_IA64_NONE.  */
+     case EM_SH:      /* R_SH_NONE.  */
+--- original-binutils/config.sub
++++ binutils-2.25/config.sub
+@@ -335,6 +335,9 @@ case $basic_machine in
+ 	ms1)
+ 		basic_machine=mt-unknown
+ 		;;
++	riscv)
++		basic_machine=riscv-ucb
++		;;
+ 
+ 	strongarm | thumb | xscale)
+ 		basic_machine=arm-unknown
+--- original-binutils/gas/configure.ac
++++ binutils-2.25/gas/configure.ac
+@@ -453,7 +453,7 @@ changequote([,])dnl
+ 	AC_MSG_RESULT($enable_audio_ext)
+ 	;;
+ 
+-      i386 | s390 | sparc)
++      i386 | riscv | s390 | sparc)
+ 	if test $this_target = $target ; then
+ 	  AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
+ 	fi
+--- original-binutils/gas/configure
++++ binutils-2.25/gas/configure
+@@ -12402,7 +12402,7 @@ $as_echo "#define NDS32_DEFAULT_AUDIO_EXT 1" >>confdefs.h
+ $as_echo "$enable_audio_ext" >&6; }
+ 	;;
+ 
+-      i386 | s390 | sparc)
++      i386 | riscv | s390 | sparc)
+ 	if test $this_target = $target ; then
+ 
+ cat >>confdefs.h <<_ACEOF
+--- original-binutils/gas/configure.tgt
++++ binutils-2.25/gas/configure.tgt
+@@ -86,6 +86,8 @@ case ${cpu} in
+   pj*)			cpu_type=pj endian=big ;;
+   powerpc*le*)		cpu_type=ppc endian=little ;;
+   powerpc*)		cpu_type=ppc endian=big ;;
++  riscv32*)		cpu_type=riscv endian=little arch=riscv32 ;;
++  riscv*)		cpu_type=riscv endian=little arch=riscv64 ;;
+   rs6000*)		cpu_type=ppc ;;
+   rl78*)		cpu_type=rl78 ;;
+   rx)			cpu_type=rx ;;
+@@ -384,6 +385,8 @@ case ${generic_target} in
+   ppc-*-kaos*)				fmt=elf ;;
+   ppc-*-lynxos*)			fmt=elf em=lynx ;;
+ 
++  riscv*-*-*)			fmt=elf endian=little em=linux ;;
++
+   s390-*-linux-*)			fmt=elf em=linux ;;
+   s390-*-tpf*)				fmt=elf ;;
+ 
+@@ -489,7 +490,7 @@ case ${generic_target} in
+ esac
+ 
+ case ${cpu_type} in
+-  aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | or1k | or1knd | pdp11 | ppc | sparc | z80 | z8k)
++  aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | or1k | or1knd | pdp11 | ppc | riscv | sparc | z80 | z8k)
+     bfd_gas=yes
+     ;;
+ esac
+--- original-binutils/gas/Makefile.am
++++ binutils-2.25/gas/Makefile.am
+@@ -171,6 +171,7 @@ TARGET_CPU_CFILES = \
+ 	config/tc-pdp11.c \
+ 	config/tc-pj.c \
+ 	config/tc-ppc.c \
++	config/tc-riscv.c \
+ 	config/tc-rl78.c \
+ 	config/tc-rx.c \
+ 	config/tc-s390.c \
+@@ -242,6 +243,7 @@ TARGET_CPU_HFILES = \
+ 	config/tc-pdp11.h \
+ 	config/tc-pj.h \
+ 	config/tc-ppc.h \
++	config/tc-riscv.h \
+ 	config/tc-rl78.h \
+ 	config/tc-rx.h \
+ 	config/tc-s390.h \
+--- original-binutils/gas/Makefile.in
++++ binutils-2.25/gas/Makefile.in
+@@ -440,6 +440,7 @@ TARGET_CPU_CFILES = \
+ 	config/tc-pdp11.c \
+ 	config/tc-pj.c \
+ 	config/tc-ppc.c \
++	config/tc-riscv.c \
+ 	config/tc-rl78.c \
+ 	config/tc-rx.c \
+ 	config/tc-s390.c \
+@@ -511,6 +512,7 @@ TARGET_CPU_HFILES = \
+ 	config/tc-pdp11.h \
+ 	config/tc-pj.h \
+ 	config/tc-ppc.h \
++	config/tc-riscv.h \
+ 	config/tc-rl78.h \
+ 	config/tc-rx.h \
+ 	config/tc-s390.h \
+@@ -866,6 +868,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-riscv.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rl78.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rx.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-s390.Po@am__quote@
+@@ -1571,6 +1574,20 @@ tc-ppc.obj: config/tc-ppc.c
+ @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ @am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ppc.obj `if test -f 'config/tc-ppc.c'; then $(CYGPATH_W) 'config/tc-ppc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ppc.c'; fi`
+ 
++tc-riscv.o: config/tc-riscv.c
++@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.o -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c
++@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='config/tc-riscv.c' object='tc-riscv.o' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c
++
++tc-riscv.obj: config/tc-riscv.c
++@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.obj -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi`
++@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='config/tc-riscv.c' object='tc-riscv.obj' libtool=no @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi`
++
+ tc-rl78.o: config/tc-rl78.c
+ @am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-rl78.o -MD -MP -MF $(DEPDIR)/tc-rl78.Tpo -c -o tc-rl78.o `test -f 'config/tc-rl78.c' || echo '$(srcdir)/'`config/tc-rl78.c
+ @am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-rl78.Tpo $(DEPDIR)/tc-rl78.Po
+--- original-binutils/include/dis-asm.h
++++ binutils-2.25/include/dis-asm.h
+@@ -254,6 +254,7 @@ extern int print_insn_little_arm	(bfd_vm
+ extern int print_insn_little_mips	(bfd_vma, disassemble_info *);
+ extern int print_insn_little_nios2	(bfd_vma, disassemble_info *);
+ extern int print_insn_little_powerpc	(bfd_vma, disassemble_info *);
++extern int print_insn_riscv		(bfd_vma, disassemble_info *);
+ extern int print_insn_little_score      (bfd_vma, disassemble_info *); 
+ extern int print_insn_lm32		(bfd_vma, disassemble_info *);
+ extern int print_insn_m32c	        (bfd_vma, disassemble_info *);
+@@ -313,6 +314,7 @@ extern void print_aarch64_disassembler_o
+ extern void print_i386_disassembler_options (FILE *);
+ extern void print_mips_disassembler_options (FILE *);
+ extern void print_ppc_disassembler_options (FILE *);
++extern void print_riscv_disassembler_options (FILE *);
+ extern void print_arm_disassembler_options (FILE *);
+ extern void parse_arm_disassembler_option (char *);
+ extern void print_s390_disassembler_options (FILE *);
+--- original-binutils/include/elf/common.h
++++ binutils-2.25/include/elf/common.h
+@@ -301,6 +301,7 @@
+ #define EM_INTEL207	207	/* Reserved by Intel */
+ #define EM_INTEL208	208	/* Reserved by Intel */
+ #define EM_INTEL209	209	/* Reserved by Intel */
++#define EM_RISCV	243	/* Reserved by Intel */
+ 
+ /* If it is necessary to assign new unofficial EM_* values, please pick large
+    random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
+--- original-binutils/ld/configure.tgt
++++ binutils-2.25/ld/configure.tgt
+@@ -604,6 +604,12 @@ powerpc-*-aix*)		targ_emul=aixppc ;;
+ powerpc-*-beos*)	targ_emul=aixppc ;;
+ powerpc-*-windiss*)	targ_emul=elf32ppcwindiss ;;
+ powerpc-*-lynxos*)	targ_emul=ppclynx ;;
++riscv32*-*-*)		targ_emul=elf32lriscv
++			targ_extra_emuls="elf64lriscv"
++			targ_extra_libpath=$targ_extra_emuls ;;
++riscv*-*-*)		targ_emul=elf64lriscv
++			targ_extra_emuls="elf32lriscv"
++			targ_extra_libpath=$targ_extra_emuls ;;
+ rs6000-*-aix[5-9]*)	targ_emul=aix5rs6 ;;
+ rs6000-*-aix*)		targ_emul=aixrs6
+ 			;;
+--- original-binutils/ld/Makefile.am
++++ binutils-2.25/ld/Makefile.am
+@@ -258,6 +258,7 @@ ALL_EMULATION_SOURCES = \
+ 	eelf32ppcsim.c \
+ 	eelf32ppcvxworks.c \
+ 	eelf32ppcwindiss.c \
++	eelf32lriscv.c \
+ 	eelf32rl78.c \
+ 	eelf32rx.c \
+ 	eelf32tilegx.c \
+@@ -464,6 +465,7 @@ ALL_64_EMULATION_SOURCES = \
+ 	eelf64btsmip_fbsd.c \
+ 	eelf64hppa.c \
+ 	eelf64lppc.c \
++	eelf64lriscv.c \
+ 	eelf64ltsmip.c \
+ 	eelf64ltsmip_fbsd.c \
+ 	eelf64mmix.c \
+@@ -1104,6 +1106,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/el
+   ldemul-list.h \
+   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ 
++eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \
++  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
++  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
++  ${GEN_DEPENDS}
++
+ eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \
+   $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \
+   $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
+@@ -1861,6 +1868,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64
+   ldemul-list.h \
+   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ 
++eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \
++  $(srcdir)/emulparams/elf64lriscv-defs.sh \
++  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
++  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
++  ${GEN_DEPENDS}
++
+ eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \
+   $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \
+   $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \
+--- original-binutils/ld/Makefile.in
++++ binutils-2.25/ld/Makefile.in
+@@ -546,6 +546,7 @@ ALL_EMULATION_SOURCES = \
+ 	eelf32lppclinux.c \
+ 	eelf32lppcnto.c \
+ 	eelf32lppcsim.c \
++	eelf32lriscv.c \
+ 	eelf32m32c.c \
+ 	eelf32mb_linux.c \
+ 	eelf32mbel_linux.c \
+@@ -771,6 +772,7 @@ ALL_64_EMULATION_SOURCES = \
+ 	eelf64btsmip_fbsd.c \
+ 	eelf64hppa.c \
+ 	eelf64lppc.c \
++	eelf64lriscv.c \
+ 	eelf64ltsmip.c \
+ 	eelf64ltsmip_fbsd.c \
+ 	eelf64mmix.c \
+@@ -1157,6 +1159,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppclinux.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcnto.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcsim.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900n32.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lsmip.Po@am__quote@
+@@ -1211,6 +1214,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Po@am__quote@
+@@ -2545,6 +2549,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/el
+   ldemul-list.h \
+   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ 
++eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \
++  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
++  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
++  ${GEN_DEPENDS}
++
+ eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \
+   $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \
+   $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
+@@ -3302,6 +3311,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64
+   ldemul-list.h \
+   $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ 
++eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \
++  $(srcdir)/emulparams/elf64lriscv-defs.sh \
++  $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \
++  $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \
++  ${GEN_DEPENDS}
++
+ eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \
+   $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \
+   $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \
+--- original-binutils/opcodes/configure
++++ binutils-2.25/opcodes/configure
+@@ -12590,6 +12590,7 @@ if test x${all_targets} = xfalse ; then
+ 	bfd_powerpc_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
+ 	bfd_powerpc_64_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
+ 	bfd_pyramid_arch)	;;
++	bfd_riscv_arch)		ta="$ta riscv-dis.lo riscv-opc.lo" ;;
+ 	bfd_romp_arch)		;;
+ 	bfd_rs6000_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
+ 	bfd_rl78_arch)		ta="$ta rl78-dis.lo rl78-decode.lo";;
+--- original-binutils/opcodes/disassemble.c
++++ binutils-2.25/opcodes/disassemble.c
+@@ -373,6 +373,11 @@ disassembler (abfd)
+ 	disassemble = print_insn_little_powerpc;
+       break;
+ #endif
++#ifdef ARCH_riscv
++    case bfd_arch_riscv:
++      disassemble = print_insn_riscv;
++      break;
++#endif
+ #ifdef ARCH_rs6000
+     case bfd_arch_rs6000:
+       if (bfd_get_mach (abfd) == bfd_mach_ppc_620)
+@@ -545,6 +550,9 @@ disassembler_usage (stream)
+ #ifdef ARCH_powerpc
+   print_ppc_disassembler_options (stream);
+ #endif
++#ifdef ARCH_riscv
++  print_riscv_disassembler_options (stream);
++#endif
+ #ifdef ARCH_i386
+   print_i386_disassembler_options (stream);
+ #endif
+--- original-binutils/bfd/Makefile.in	2014-10-14 00:32:02.000000000 -0700
++++ binutils-2.25/bfd/Makefile.in	2015-03-31 06:53:23.253426230 -0700
+@@ -442,6 +442,7 @@
+ 	cpu-pj.lo \
+ 	cpu-plugin.lo \
+ 	cpu-powerpc.lo \
++	cpu-riscv.lo \
+ 	cpu-rs6000.lo \
+ 	cpu-rl78.lo \
+ 	cpu-rx.lo \
+@@ -526,6 +527,7 @@
+ 	cpu-pj.c \
+ 	cpu-plugin.c \
+ 	cpu-powerpc.c \
++	cpu-riscv.c \
+ 	cpu-rs6000.c \
+ 	cpu-rl78.c \
+ 	cpu-rx.c \
diff --git a/util/crossgcc/patches/gcc-4.9.2_elf_biarch.patch b/util/crossgcc/patches/gcc-5.2.0_elf_biarch.patch
similarity index 95%
rename from util/crossgcc/patches/gcc-4.9.2_elf_biarch.patch
rename to util/crossgcc/patches/gcc-5.2.0_elf_biarch.patch
index 25749ef..37240f9 100644
--- a/util/crossgcc/patches/gcc-4.9.2_elf_biarch.patch
+++ b/util/crossgcc/patches/gcc-5.2.0_elf_biarch.patch
@@ -1,6 +1,6 @@
 diff -urN gcc-4.9.2/gcc/config/i386/t-elf64 gcc-4.9.2/gcc/config/i386/t-elf64
 --- gcc-4.9.2/gcc/config/i386/t-elf64	1969-12-31 16:00:00.000000000 -0800
-+++ gcc-4.9.2/gcc/config/i386/t-elf64	2015-06-17 11:20:08.032513005 -0700
++++ gcc-5.2.0/gcc/config/i386/t-elf64	2015-06-17 11:20:08.032513005 -0700
 @@ -0,0 +1,38 @@
 +# Copyright (C) 2002-2014 Free Software Foundation, Inc.
 +#
@@ -42,7 +42,7 @@
 +MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-elf-x32)
 diff -urN gcc-4.9.2/gcc/config.gcc gcc-4.9.2/gcc/config.gcc
 --- gcc-4.9.2/gcc/config.gcc	2015-06-17 11:20:57.841008182 -0700
-+++ gcc-4.9.2/gcc/config.gcc	2015-06-17 11:17:24.818890200 -0700
++++ gcc-5.2.0/gcc/config.gcc	2015-06-17 11:17:24.818890200 -0700
 @@ -1353,6 +1353,30 @@
  	;;
  x86_64-*-elf*)
diff --git a/util/crossgcc/patches/gcc-4.9.2_riscv.patch b/util/crossgcc/patches/gcc-5.2.0_riscv.patch
similarity index 90%
rename from util/crossgcc/patches/gcc-4.9.2_riscv.patch
rename to util/crossgcc/patches/gcc-5.2.0_riscv.patch
index 942b48f..ebe355d 100644
--- a/util/crossgcc/patches/gcc-4.9.2_riscv.patch
+++ b/util/crossgcc/patches/gcc-5.2.0_riscv.patch
@@ -1,10 +1,6 @@
-Created from https://github.com/riscv/riscv-gnu-toolchain,
-commit ddce5d17f14831f4957e57c415aca77817c2a82c
-
-diff -urN original-gcc/config.sub gcc/config.sub
---- original-gcc/config.sub	2013-10-01 18:50:56.000000000 +0200
-+++ gcc-4.9.2/config.sub	2015-03-07 09:57:54.195132741 +0100
-@@ -334,6 +334,9 @@
+--- original-gcc/config.sub
++++ gcc-5.2.0/config.sub
+@@ -340,6 +340,9 @@ case $basic_machine in
  	ms1)
  		basic_machine=mt-unknown
  		;;
@@ -14,10 +10,308 @@
  
  	strongarm | thumb | xscale)
  		basic_machine=arm-unknown
-diff -urN original-gcc/gcc/common/config/riscv/riscv-common.c gcc/gcc/common/config/riscv/riscv-common.c
---- original-gcc/gcc/common/config/riscv/riscv-common.c	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/common/config/riscv/riscv-common.c	2015-03-07 09:51:45.663139025 +0100
-@@ -0,0 +1,128 @@
+--- original-gcc/gcc/config.gcc
++++ gcc-5.2.0/gcc/config.gcc
+@@ -439,6 +439,10 @@ powerpc*-*-*)
+ 	esac
+ 	extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
+ 	;;
++riscv*)
++	cpu_type=riscv
++	need_64bit_hwint=yes
++	;;
+ rs6000*-*-*)
+ 	extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
+ 	;;
+@@ -1976,6 +1980,27 @@ microblaze*-*-elf)
+ 	cxx_target_objs="${cxx_target_objs} microblaze-c.o"
+ 	tmake_file="${tmake_file} microblaze/t-microblaze"
+         ;;
++riscv32*-*-linux*)				# Linux RISC-V
++	tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h riscv/default-32.h ${tm_file} riscv/linux.h riscv/linux64.h"
++	tmake_file="${tmake_file} riscv/t-linux64"
++	gnu_ld=yes
++	gas=yes
++	gcc_cv_initfini_array=yes
++	;;
++riscv*-*-linux*)				# Linux RISC-V
++	tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} riscv/linux.h riscv/linux64.h"
++	tmake_file="${tmake_file} riscv/t-linux64"
++	gnu_ld=yes
++	gas=yes
++	gcc_cv_initfini_array=yes
++	;;
++riscv*-*-elf*)				# Linux RISC-V
++	tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
++	tmake_file="${tmake_file} riscv/t-elf"
++	gnu_ld=yes
++	gas=yes
++	gcc_cv_initfini_array=yes
++	;;
+ mips*-*-netbsd*)			# NetBSD/mips, either endian.
+ 	target_cpu_default="MASK_ABICALLS"
+ 	tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h"
+@@ -3851,6 +3876,31 @@ case "${target}" in
+ 		done
+ 		;;
+ 
++	riscv*-*-*)
++		supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64"
++
++		case ${with_float} in
++		"" | soft | hard)
++			# OK
++			;;
++		*)
++			echo "Unknown floating point type used in --with-float=$with_float" 1>&2
++			exit 1
++			;;
++		esac
++
++		case ${with_abi} in
++		"" | 32 | 64)
++			# OK
++			;;
++		*)
++			echo "Unknown ABI used in --with-abi=$with_abi" 1>&2
++			exit 1
++			;;
++		esac
++
++    ;;
++
+ 	mips*-*-*)
+ 		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci"
+ 
+--- original-gcc/gcc/configure
++++ gcc-5.2.0/gcc/configure
+@@ -23708,6 +23708,25 @@ x3:	.space 4
+ 	tls_first_minor=14
+ 	tls_as_opt="-a32 --fatal-warnings"
+ 	;;
++  riscv*-*-*)
++    conftest_s='
++	.section .tdata,"awT",@progbits
++x:
++	.word 2
++	.text
++	la.tls.gd a0,x
++	la.tls.ie a1,x
++	lui a0,%tls_ie_pcrel_hi(x)
++	lw a0,%pcrel_lo(x)(a0)
++	add a0,a0,tp
++	lw a0,0(a0)
++	lui a0,%tprel_hi(x)
++	add a0,a0,tp,%tprel_add(x)
++	lw a0,%tprel_lo(x)(a0)'
++	tls_first_major=2
++	tls_first_minor=21
++	tls_as_opt='-m32 --fatal-warnings'
++	;;
+   s390-*-*)
+     conftest_s='
+ 	.section ".tdata","awT",@progbits
+--- original-gcc/gcc/configure.ac
++++ gcc-5.2.0/gcc/configure.ac
+@@ -3263,6 +3263,25 @@ x3:	.space 4
+ 	tls_first_minor=14
+ 	tls_as_opt="-a32 --fatal-warnings"
+ 	;;
++  riscv*-*-*)
++    conftest_s='
++	.section .tdata,"awT",@progbits
++x:
++	.word 2
++	.text
++	la.tls.gd a0,x
++	la.tls.ie a1,x
++	lui a0,%tls_ie_pcrel_hi(x)
++	lw a0,%pcrel_lo(x)(a0)
++	add a0,a0,tp
++	lw a0,0(a0)
++	lui a0,%tprel_hi(x)
++	add a0,a0,tp,%tprel_add(x)
++	lw a0,%tprel_lo(x)(a0)'
++	tls_first_major=2
++	tls_first_minor=21
++	tls_as_opt='-m32 --fatal-warnings'
++	;;
+   s390-*-*)
+     conftest_s='
+ 	.section ".tdata","awT",@progbits
+--- original-gcc/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
++++ gcc-5.2.0/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
+@@ -6,6 +6,9 @@
+ #elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) || defined (__POWERPC__) || defined (__ppc)
+   /* On PPC division by zero does not trap.  */
+ # define DO_TEST 0
++#elif defined (__riscv__)
++  /* On RISC-V division by zero does not trap.  */
++# define DO_TEST 0
+ #elif defined (__SPU__)
+   /* On SPU division by zero does not trap.  */
+ # define DO_TEST 0
+--- original-gcc/gcc/testsuite/gcc.dg/20020312-2.c
++++ gcc-5.2.0/gcc/testsuite/gcc.dg/20020312-2.c
+@@ -66,6 +66,8 @@ extern void abort (void);
+ # else
+ #  define PIC_REG  "30"
+ # endif
++#elif defined(__riscv__)
++/* No pic register.  */
+ #elif defined(__RX__)
+ /* No pic register.  */
+ #elif defined(__s390__)
+--- original-gcc/gcc/testsuite/gcc.dg/20040813-1.c
++++ gcc-5.2.0/gcc/testsuite/gcc.dg/20040813-1.c
+@@ -2,7 +2,7 @@
+ /* Contributed by Devang Patel  <dpatel@apple.com>  */
+ 
+ /* { dg-do compile } */
+-/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* nios2-*-* *-*-vxworks* nvptx-*-* } { "*" } { "" } } */
++/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* riscv*-*-* tile*-*-* nios2-*-* *-*-vxworks* nvptx-*-* } { "*" } { "" } } */
+ /* { dg-options "-gstabs" } */
+ 
+ int
+--- original-gcc/gcc/testsuite/gcc.dg/stack-usage-1.c
++++ gcc-5.2.0/gcc/testsuite/gcc.dg/stack-usage-1.c
+@@ -61,6 +61,8 @@
+ #  else
+ #    define SIZE 240
+ #  endif
++#elif defined (__riscv__)
++#  define SIZE 240
+ #elif defined (__AVR__)
+ #  define SIZE 254
+ #elif defined (__s390x__)
+--- original-gcc/libatomic/configure.tgt
++++ gcc-5.2.0/libatomic/configure.tgt
+@@ -33,6 +33,7 @@ case "${target_cpu}" in
+ 	ARCH=alpha
+ 	;;
+   rs6000 | powerpc*)	ARCH=powerpc ;;
++  riscv*)		ARCH=riscv ;;
+   sh*)			ARCH=sh ;;
+ 
+   arm*)
+--- original-gcc/libgcc/config.host
++++ gcc-5.2.0/libgcc/config.host
+@@ -167,6 +167,9 @@ powerpc*-*-*)
+ 	;;
+ rs6000*-*-*)
+ 	;;
++riscv*)
++	cpu_type=riscv
++	;;
+ sparc64*-*-*)
+ 	cpu_type=sparc
+ 	;;
+@@ -1057,6 +1060,18 @@ powerpcle-*-eabi*)
+ 	tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-crtstuff t-crtstuff-pic t-fdpbit"
+ 	extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o"
+ 	;;
++riscv32*-*-linux*)
++	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-tpbit riscv/t-elf riscv/t-elf32"
++	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o crtendS.o crtbeginT.o"
++	;;
++riscv*-*-linux*)
++	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-tpbit riscv/t-elf"
++	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o crtendS.o crtbeginT.o"
++	;;
++riscv*-*-*)
++	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-elf"
++	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
++	;;
+ rs6000-ibm-aix4.[3456789]* | powerpc-ibm-aix4.[3456789]*)
+ 	md_unwind_header=rs6000/aix-unwind.h
+ 	tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-slibgcc-aix rs6000/t-ibm-ldouble"
+--- original-gcc/libsanitizer/asan/asan_linux.cc
++++ gcc-5.2.0/libsanitizer/asan/asan_linux.cc
+@@ -213,6 +213,11 @@ void GetPcSpBp(void *context, uptr *pc,
+   *pc = ucontext->uc_mcontext.gregs[31];
+   *bp = ucontext->uc_mcontext.gregs[30];
+   *sp = ucontext->uc_mcontext.gregs[29];
++# elif defined(__riscv__)
++  ucontext_t *ucontext = (ucontext_t*)context;
++  *pc = ucontext->uc_mcontext.gregs[REG_PC];
++  *bp = ucontext->uc_mcontext.gregs[REG_S0];
++  *sp = ucontext->uc_mcontext.gregs[REG_SP];
+ #else
+ # error "Unsupported arch"
+ #endif
+--- original-gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
++++ gcc-5.2.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
+@@ -61,7 +61,8 @@ namespace __sanitizer {
+ }  // namespace __sanitizer
+ 
+ #if !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__aarch64__)\
+-                            && !defined(__mips__) && !defined(__sparc__)
++                            && !defined(__mips__) && !defined(__sparc__)\
++                            && !defined(__riscv__)
+ COMPILER_CHECK(struct___old_kernel_stat_sz == sizeof(struct __old_kernel_stat));
+ #endif
+ 
+--- original-gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
++++ gcc-5.2.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+@@ -72,6 +72,10 @@ namespace __sanitizer {
+   const unsigned struct_kernel_stat_sz = 144;
+   #endif
+   const unsigned struct_kernel_stat64_sz = 104;
++#elif defined(__riscv__)
++  const unsigned struct___old_kernel_stat_sz = 0;
++  const unsigned struct_kernel_stat_sz = 128;
++  const unsigned struct_kernel_stat64_sz = 128;
+ #elif defined(__sparc__) && defined(__arch64__)
+   const unsigned struct___old_kernel_stat_sz = 0;
+   const unsigned struct_kernel_stat_sz = 104;
+@@ -511,7 +515,7 @@ namespace __sanitizer {
+   typedef long __sanitizer___kernel_off_t;
+ #endif
+ 
+-#if defined(__powerpc__) || defined(__mips__)
++#if defined(__powerpc__) || defined(__mips__) || defined(__riscv__)
+   typedef unsigned int __sanitizer___kernel_old_uid_t;
+   typedef unsigned int __sanitizer___kernel_old_gid_t;
+ #else
+diff -ru gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform.h gcc-5.1.0/libsanitizer/sanitizer_common/sanitizer_platform.h
+--- gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform.h	2015-05-13 19:36:27.061421043 -0700
++++ gcc-5.2.0/libsanitizer/sanitizer_common/sanitizer_platform.h	2015-05-13 19:44:19.274355577 -0700
+@@ -98,9 +98,9 @@
+ 
+ // The AArch64 linux port uses the canonical syscall set as mandated by
+ // the upstream linux community for all new ports. Other ports may still
+-// use legacy syscalls.
++// use legacy syscalls.  The RISC-V port also does this.
+ #ifndef SANITIZER_USES_CANONICAL_LINUX_SYSCALLS
+-# if defined(__aarch64__) && SANITIZER_LINUX
++# if (defined(__aarch64__) || defined(__riscv__)) && SANITIZER_LINUX
+ # define SANITIZER_USES_CANONICAL_LINUX_SYSCALLS 1
+ # else
+ # define SANITIZER_USES_CANONICAL_LINUX_SYSCALLS 0
+diff -ru gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h gcc-5.1.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+--- gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	2015-05-13 19:36:27.061421043 -0700
++++ gcc-5.2.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	2015-05-13 19:39:13.515487834 -0700
+@@ -73,7 +73,6 @@
+   #endif
+   const unsigned struct_kernel_stat64_sz = 104;
+ #elif defined(__riscv__)
+-  const unsigned struct___old_kernel_stat_sz = 0;
+   const unsigned struct_kernel_stat_sz = 128;
+   const unsigned struct_kernel_stat64_sz = 128;
+ #elif defined(__sparc__) && defined(__arch64__)
+@@ -104,7 +103,7 @@
+ 
+ #if SANITIZER_LINUX || SANITIZER_FREEBSD
+ 
+-#if defined(__powerpc64__)
++#if defined(__powerpc64__) || defined(__riscv__)
+   const unsigned struct___old_kernel_stat_sz = 0;
+ #elif !defined(__sparc__)
+   const unsigned struct___old_kernel_stat_sz = 32;
+diff -urN empty/gcc/common/config/riscv/riscv-common.c gcc-5.2.0/gcc/common/config/riscv/riscv-common.c
+--- empty/gcc/common/config/riscv/riscv-common.c	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/common/config/riscv/riscv-common.c	2015-07-17 22:36:52.315705931 +0200
+@@ -0,0 +1,140 @@
 +/* Common hooks for RISC-V.
 +   Copyright (C) 1989-2014 Free Software Foundation, Inc.
 +
@@ -92,6 +386,16 @@
 +      return;
 +    }
 +
++  *flags &= ~MASK_RVC;
++  if (*p == 'C')
++    *flags |= MASK_RVC, p++;
++
++  /* FIXME: For now we just stop parsing when faced with a
++     non-standard RISC-V ISA extension, partially becauses of a
++     problem with the naming scheme. */
++  if (*p == 'X')
++    return;
++
 +  if (*p)
 +    {
 +      error ("-march=%s: unsupported ISA substring %s", isa, p);
@@ -131,6 +435,7 @@
 +  {
 +    { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
 +    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
++    { OPT_LEVELS_SIZE, OPT_msave_restore, NULL, 1 },
 +    { OPT_LEVELS_NONE, 0, NULL, 0 }
 +  };
 +
@@ -139,16 +444,17 @@
 +
 +#undef TARGET_DEFAULT_TARGET_FLAGS
 +#define TARGET_DEFAULT_TARGET_FLAGS				\
-+  (riscv_flags_from_arch_string (RISCV_ARCH_STRING_DEFAULT)	\
++  (TARGET_DEFAULT						\
++   | riscv_flags_from_arch_string (RISCV_ARCH_STRING_DEFAULT)	\
 +   | (TARGET_64BIT_DEFAULT ? 0 : MASK_32BIT))
 +
 +#undef TARGET_HANDLE_OPTION
 +#define TARGET_HANDLE_OPTION riscv_handle_option
 +
 +struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
-diff -urN original-gcc/gcc/config/riscv/constraints.md gcc/gcc/config/riscv/constraints.md
---- original-gcc/gcc/config/riscv/constraints.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/constraints.md	2015-03-07 09:51:45.663139025 +0100
+diff -urN empty/gcc/config/riscv/constraints.md gcc-5.2.0/gcc/config/riscv/constraints.md
+--- empty/gcc/config/riscv/constraints.md	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/constraints.md	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,90 @@
 +;; Constraint definitions for RISC-V target.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -240,9 +546,9 @@
 +   A vector zero."
 +  (and (match_code "const_vector")
 +       (match_test "op == CONST0_RTX (mode)")))
-diff -urN original-gcc/gcc/config/riscv/default-32.h gcc/gcc/config/riscv/default-32.h
---- original-gcc/gcc/config/riscv/default-32.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/default-32.h	2015-03-07 09:51:45.663139025 +0100
+diff -urN empty/gcc/config/riscv/default-32.h gcc-5.2.0/gcc/config/riscv/default-32.h
+--- empty/gcc/config/riscv/default-32.h	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/default-32.h	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,22 @@
 +/* Definitions of target machine for GCC, for RISC-V,
 +   defaulting to 32-bit code generation.
@@ -266,9 +572,9 @@
 +<http://www.gnu.org/licenses/>.  */
 +
 +#define TARGET_64BIT_DEFAULT 0
-diff -urN original-gcc/gcc/config/riscv/elf.h gcc/gcc/config/riscv/elf.h
---- original-gcc/gcc/config/riscv/elf.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/elf.h	2015-03-07 09:51:45.663139025 +0100
+diff -urN empty/gcc/config/riscv/elf.h gcc-5.2.0/gcc/config/riscv/elf.h
+--- empty/gcc/config/riscv/elf.h	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/elf.h	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,31 @@
 +/* Target macros for riscv*-elf targets.
 +   Copyright (C) 1994, 1997, 1999, 2000, 2002, 2003, 2004, 2007, 2010
@@ -301,9 +607,9 @@
 +#define ENDFILE_SPEC "crtend%O%s"
 +
 +#define NO_IMPLICIT_EXTERN_C 1
-diff -urN original-gcc/gcc/config/riscv/generic.md gcc/gcc/config/riscv/generic.md
---- original-gcc/gcc/config/riscv/generic.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/generic.md	2015-03-07 09:51:45.663139025 +0100
+diff -urN empty/gcc/config/riscv/generic.md gcc-5.2.0/gcc/config/riscv/generic.md
+--- empty/gcc/config/riscv/generic.md	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/generic.md	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,98 @@
 +;; Generic DFA-based pipeline description for RISC-V targets.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -403,56 +709,9 @@
 +  (and (eq_attr "type" "fsqrt")
 +       (eq_attr "mode" "DF"))
 +  "alu")
-diff -urN original-gcc/gcc/config/riscv/linux64.h gcc/gcc/config/riscv/linux64.h
---- original-gcc/gcc/config/riscv/linux64.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/linux64.h	2015-03-07 09:51:45.663139025 +0100
-@@ -0,0 +1,43 @@
-+/* Definitions for 64-bit RISC-V GNU/Linux systems with ELF format.
-+   Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2011
-+   Free Software Foundation, Inc.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3.  If not see
-+<http://www.gnu.org/licenses/>.  */
-+
-+/* Force the default ABI flags onto the command line
-+   in order to make the other specs easier to write.  */
-+#undef LIB_SPEC
-+#define LIB_SPEC "\
-+%{pthread:-lpthread} \
-+%{shared:-lc} \
-+%{!shared: \
-+  %{profile:-lc_p} %{!profile:-lc}}"
-+
-+#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1"
-+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1"
-+
-+#undef LINK_SPEC
-+#define LINK_SPEC "\
-+%{shared} \
-+  %{!shared: \
-+    %{!static: \
-+      %{rdynamic:-export-dynamic} \
-+      %{" OPT_ARCH64 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "} \
-+      %{" OPT_ARCH32 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
-+    %{static:-static}} \
-+%{" OPT_ARCH64 ":-melf64lriscv} \
-+%{" OPT_ARCH32 ":-melf32lriscv}"
-diff -urN original-gcc/gcc/config/riscv/linux.h gcc/gcc/config/riscv/linux.h
---- original-gcc/gcc/config/riscv/linux.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/linux.h	2015-03-07 09:51:45.663139025 +0100
+diff -urN empty/gcc/config/riscv/linux.h gcc-5.2.0/gcc/config/riscv/linux.h
+--- empty/gcc/config/riscv/linux.h	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/linux.h	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,60 @@
 +/* Definitions for RISC-V GNU/Linux systems with ELF format.
 +   Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
@@ -514,9 +773,56 @@
 +#undef  ENDFILE_SPEC
 +#define ENDFILE_SPEC \
 +   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
-diff -urN original-gcc/gcc/config/riscv/opcode-riscv.h gcc/gcc/config/riscv/opcode-riscv.h
---- original-gcc/gcc/config/riscv/opcode-riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/opcode-riscv.h	2015-03-07 09:51:45.663139025 +0100
+diff -urN empty/gcc/config/riscv/linux64.h gcc-5.2.0/gcc/config/riscv/linux64.h
+--- empty/gcc/config/riscv/linux64.h	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/linux64.h	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,43 @@
++/* Definitions for 64-bit RISC-V GNU/Linux systems with ELF format.
++   Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2011
++   Free Software Foundation, Inc.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++/* Force the default ABI flags onto the command line
++   in order to make the other specs easier to write.  */
++#undef LIB_SPEC
++#define LIB_SPEC "\
++%{pthread:-lpthread} \
++%{shared:-lc} \
++%{!shared: \
++  %{profile:-lc_p} %{!profile:-lc}}"
++
++#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1"
++#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1"
++
++#undef LINK_SPEC
++#define LINK_SPEC "\
++%{shared} \
++  %{!shared: \
++    %{!static: \
++      %{rdynamic:-export-dynamic} \
++      %{" OPT_ARCH64 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "} \
++      %{" OPT_ARCH32 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
++    %{static:-static}} \
++%{" OPT_ARCH64 ":-melf64lriscv} \
++%{" OPT_ARCH32 ":-melf32lriscv}"
+diff -urN empty/gcc/config/riscv/opcode-riscv.h gcc-5.2.0/gcc/config/riscv/opcode-riscv.h
+--- empty/gcc/config/riscv/opcode-riscv.h	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/opcode-riscv.h	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,149 @@
 +/* RISC-V ISA encoding.
 +   Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -667,9 +973,9 @@
 +#include "riscv-opc.h"
 +
 +#endif /* _RISCV_H_ */
-diff -urN original-gcc/gcc/config/riscv/peephole.md gcc/gcc/config/riscv/peephole.md
---- original-gcc/gcc/config/riscv/peephole.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/peephole.md	2015-03-07 09:51:45.663139025 +0100
+diff -urN empty/gcc/config/riscv/peephole.md gcc-5.2.0/gcc/config/riscv/peephole.md
+--- empty/gcc/config/riscv/peephole.md	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/peephole.md	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,100 @@
 +;;........................
 +;; DI -> SI optimizations
@@ -771,10 +1077,10 @@
 +  "TARGET_HARD_FLOAT && !TARGET_64BIT && (flag_pic && SYMBOL_REF_LOCAL_P (operands[0]))"
 +  "<store>\t%1,%0,%2"
 +  [(set (attr "length") (const_int 8))])
-diff -urN original-gcc/gcc/config/riscv/predicates.md gcc/gcc/config/riscv/predicates.md
---- original-gcc/gcc/config/riscv/predicates.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/predicates.md	2015-03-07 09:51:45.663139025 +0100
-@@ -0,0 +1,182 @@
+diff -urN empty/gcc/config/riscv/predicates.md gcc-5.2.0/gcc/config/riscv/predicates.md
+--- empty/gcc/config/riscv/predicates.md	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/predicates.md	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,187 @@
 +;; Predicate description for RISC-V target.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -828,6 +1134,11 @@
 +  (ior (match_operand 0 "const_1_operand")
 +       (match_operand 0 "register_operand")))
 +
++;; Only use branch-on-bit sequences when the mask is not an ANDI immediate.
++(define_predicate "branch_on_bit_operand"
++  (and (match_code "const_int")
++       (match_test "INTVAL (op) >= RISCV_IMM_BITS - 1")))
++
 +;; This is used for indexing into vectors, and hence only accepts const_int.
 +(define_predicate "const_0_or_1_operand"
 +  (and (match_code "const_int")
@@ -957,10 +1268,1535 @@
 +
 +(define_predicate "fp_unorder_operator"
 +  (match_code "ordered,unordered"))
-diff -urN original-gcc/gcc/config/riscv/riscv.c gcc/gcc/config/riscv/riscv.c
---- original-gcc/gcc/config/riscv/riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/riscv.c	2015-03-07 09:51:45.667139025 +0100
-@@ -0,0 +1,4292 @@
+diff -urN empty/gcc/config/riscv/riscv-ftypes.def gcc-5.2.0/gcc/config/riscv/riscv-ftypes.def
+--- empty/gcc/config/riscv/riscv-ftypes.def	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/riscv-ftypes.def	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,39 @@
++/* Definitions of prototypes for RISC-V built-in functions.
++   Copyright (C) 2011-2014 Free Software Foundation, Inc.
++   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
++   Based on MIPS target for GNU compiler.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++/* Invoke DEF_RISCV_FTYPE (NARGS, LIST) for each prototype used by
++   MIPS built-in functions, where:
++
++      NARGS is the number of arguments.
++      LIST contains the return-type code followed by the codes for each
++        argument type.
++
++   Argument- and return-type codes are either modes or one of the following:
++
++      VOID for void_type_node
++      INT for integer_type_node
++      POINTER for ptr_type_node
++
++   (we don't use PTR because that's a ANSI-compatibillity macro).
++
++   Please keep this list lexicographically sorted by the LIST argument.  */
++
++DEF_RISCV_FTYPE (1, (VOID, VOID))
+diff -urN empty/gcc/config/riscv/riscv-modes.def gcc-5.2.0/gcc/config/riscv/riscv-modes.def
+--- empty/gcc/config/riscv/riscv-modes.def	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/riscv-modes.def	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,26 @@
++/* Extra machine modes for RISC-V target.
++   Copyright (C) 2011-2014 Free Software Foundation, Inc.
++   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
++   Based on MIPS target for GNU compiler.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++FLOAT_MODE (TF, 16, ieee_quad_format);
++
++/* Vector modes.  */
++VECTOR_MODES (INT, 4);        /*       V8QI V4HI V2SI */
++VECTOR_MODES (FLOAT, 4);      /*            V4HF V2SF */
+diff -urN empty/gcc/config/riscv/riscv-opc.h gcc-5.2.0/gcc/config/riscv/riscv-opc.h
+--- empty/gcc/config/riscv/riscv-opc.h	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/riscv-opc.h	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,1348 @@
++/* Automatically generated by parse-opcodes */
++#ifndef RISCV_ENCODING_H
++#define RISCV_ENCODING_H
++#define MATCH_ADD 0x33
++#define MASK_ADD  0xfe00707f
++#define MATCH_ADDI 0x13
++#define MASK_ADDI  0x707f
++#define MATCH_ADDIW 0x1b
++#define MASK_ADDIW  0x707f
++#define MATCH_ADDW 0x3b
++#define MASK_ADDW  0xfe00707f
++#define MATCH_AMOADD_D 0x302f
++#define MASK_AMOADD_D  0xf800707f
++#define MATCH_AMOADD_W 0x202f
++#define MASK_AMOADD_W  0xf800707f
++#define MATCH_AMOAND_D 0x6000302f
++#define MASK_AMOAND_D  0xf800707f
++#define MATCH_AMOAND_W 0x6000202f
++#define MASK_AMOAND_W  0xf800707f
++#define MATCH_AMOMAX_D 0xa000302f
++#define MASK_AMOMAX_D  0xf800707f
++#define MATCH_AMOMAX_W 0xa000202f
++#define MASK_AMOMAX_W  0xf800707f
++#define MATCH_AMOMAXU_D 0xe000302f
++#define MASK_AMOMAXU_D  0xf800707f
++#define MATCH_AMOMAXU_W 0xe000202f
++#define MASK_AMOMAXU_W  0xf800707f
++#define MATCH_AMOMIN_D 0x8000302f
++#define MASK_AMOMIN_D  0xf800707f
++#define MATCH_AMOMIN_W 0x8000202f
++#define MASK_AMOMIN_W  0xf800707f
++#define MATCH_AMOMINU_D 0xc000302f
++#define MASK_AMOMINU_D  0xf800707f
++#define MATCH_AMOMINU_W 0xc000202f
++#define MASK_AMOMINU_W  0xf800707f
++#define MATCH_AMOOR_D 0x4000302f
++#define MASK_AMOOR_D  0xf800707f
++#define MATCH_AMOOR_W 0x4000202f
++#define MASK_AMOOR_W  0xf800707f
++#define MATCH_AMOSWAP_D 0x800302f
++#define MASK_AMOSWAP_D  0xf800707f
++#define MATCH_AMOSWAP_W 0x800202f
++#define MASK_AMOSWAP_W  0xf800707f
++#define MATCH_AMOXOR_D 0x2000302f
++#define MASK_AMOXOR_D  0xf800707f
++#define MATCH_AMOXOR_W 0x2000202f
++#define MASK_AMOXOR_W  0xf800707f
++#define MATCH_AND 0x7033
++#define MASK_AND  0xfe00707f
++#define MATCH_ANDI 0x7013
++#define MASK_ANDI  0x707f
++#define MATCH_AUIPC 0x17
++#define MASK_AUIPC  0x7f
++#define MATCH_BEQ 0x63
++#define MASK_BEQ  0x707f
++#define MATCH_BGE 0x5063
++#define MASK_BGE  0x707f
++#define MATCH_BGEU 0x7063
++#define MASK_BGEU  0x707f
++#define MATCH_BLT 0x4063
++#define MASK_BLT  0x707f
++#define MATCH_BLTU 0x6063
++#define MASK_BLTU  0x707f
++#define MATCH_BNE 0x1063
++#define MASK_BNE  0x707f
++#define MATCH_C_ADD 0x1000
++#define MASK_C_ADD  0xf003
++#define MATCH_C_ADD3 0xa000
++#define MASK_C_ADD3  0xe063
++#define MATCH_C_ADDI 0xc002
++#define MASK_C_ADDI  0xe003
++#define MATCH_C_ADDI16SP 0xc002
++#define MASK_C_ADDI16SP  0xef83
++#define MATCH_C_ADDI4SPN 0xa001
++#define MASK_C_ADDI4SPN  0xe003
++#define MATCH_C_ADDIN 0x8001
++#define MASK_C_ADDIN  0xe063
++#define MATCH_C_ADDIW 0xe002
++#define MASK_C_ADDIW  0xe003
++#define MATCH_C_ADDW 0x9000
++#define MASK_C_ADDW  0xf003
++#define MATCH_C_AND3 0xa060
++#define MASK_C_AND3  0xe063
++#define MATCH_C_ANDI 0xe002
++#define MASK_C_ANDI  0xe003
++#define MATCH_C_ANDIN 0x8061
++#define MASK_C_ANDIN  0xe063
++#define MATCH_C_BEQZ 0x4002
++#define MASK_C_BEQZ  0xe003
++#define MATCH_C_BGEZ 0xe001
++#define MASK_C_BGEZ  0xe003
++#define MATCH_C_BLTZ 0x6001
++#define MASK_C_BLTZ  0xe003
++#define MATCH_C_BNEZ 0x6002
++#define MASK_C_BNEZ  0xe003
++#define MATCH_C_EBREAK 0x1000
++#define MASK_C_EBREAK  0xffff
++#define MATCH_C_J 0x2
++#define MASK_C_J  0xe003
++#define MATCH_C_JAL 0x2002
++#define MASK_C_JAL  0xe003
++#define MATCH_C_JALR 0xa002
++#define MASK_C_JALR  0xf07f
++#define MATCH_C_JR 0x8002
++#define MASK_C_JR  0xf07f
++#define MATCH_C_LD 0xe000
++#define MASK_C_LD  0xe003
++#define MATCH_C_LDSP 0xe001
++#define MASK_C_LDSP  0xe003
++#define MATCH_C_LI 0x8002
++#define MASK_C_LI  0xe003
++#define MATCH_C_LUI 0xa002
++#define MASK_C_LUI  0xe003
++#define MATCH_C_LW 0xc000
++#define MASK_C_LW  0xe003
++#define MATCH_C_LWSP 0xc001
++#define MASK_C_LWSP  0xe003
++#define MATCH_C_MV 0x0
++#define MASK_C_MV  0xf003
++#define MATCH_C_OR3 0xa040
++#define MASK_C_OR3  0xe063
++#define MATCH_C_ORIN 0x8041
++#define MASK_C_ORIN  0xe063
++#define MATCH_C_SD 0x6000
++#define MASK_C_SD  0xe003
++#define MATCH_C_SDSP 0x6001
++#define MASK_C_SDSP  0xe003
++#define MATCH_C_SLL 0x6400
++#define MASK_C_SLL  0xfc63
++#define MATCH_C_SLLI 0x1
++#define MASK_C_SLLI  0xe003
++#define MATCH_C_SLLIW 0x8001
++#define MASK_C_SLLIW  0xe003
++#define MATCH_C_SLLR 0x6c00
++#define MASK_C_SLLR  0xfc63
++#define MATCH_C_SLT 0x6440
++#define MASK_C_SLT  0xfc63
++#define MATCH_C_SLTR 0x6c40
++#define MASK_C_SLTR  0xfc63
++#define MATCH_C_SLTU 0x6460
++#define MASK_C_SLTU  0xfc63
++#define MATCH_C_SLTUR 0x6c60
++#define MASK_C_SLTUR  0xfc63
++#define MATCH_C_SRA 0x6020
++#define MASK_C_SRA  0xfc63
++#define MATCH_C_SRAI 0x2000
++#define MASK_C_SRAI  0xe003
++#define MATCH_C_SRL 0x6420
++#define MASK_C_SRL  0xfc63
++#define MATCH_C_SRLI 0x2001
++#define MASK_C_SRLI  0xe003
++#define MATCH_C_SRLR 0x6c20
++#define MASK_C_SRLR  0xfc63
++#define MATCH_C_SUB 0x8000
++#define MASK_C_SUB  0xf003
++#define MATCH_C_SUB3 0xa020
++#define MASK_C_SUB3  0xe063
++#define MATCH_C_SW 0x4000
++#define MASK_C_SW  0xe003
++#define MATCH_C_SWSP 0x4001
++#define MASK_C_SWSP  0xe003
++#define MATCH_C_XOR 0x6000
++#define MASK_C_XOR  0xfc63
++#define MATCH_C_XORIN 0x8021
++#define MASK_C_XORIN  0xe063
++#define MATCH_CSRRC 0x3073
++#define MASK_CSRRC  0x707f
++#define MATCH_CSRRCI 0x7073
++#define MASK_CSRRCI  0x707f
++#define MATCH_CSRRS 0x2073
++#define MASK_CSRRS  0x707f
++#define MATCH_CSRRSI 0x6073
++#define MASK_CSRRSI  0x707f
++#define MATCH_CSRRW 0x1073
++#define MASK_CSRRW  0x707f
++#define MATCH_CSRRWI 0x5073
++#define MASK_CSRRWI  0x707f
++#define MATCH_CUSTOM0 0xb
++#define MASK_CUSTOM0  0x707f
++#define MATCH_CUSTOM0_RD 0x400b
++#define MASK_CUSTOM0_RD  0x707f
++#define MATCH_CUSTOM0_RD_RS1 0x600b
++#define MASK_CUSTOM0_RD_RS1  0x707f
++#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
++#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM0_RS1 0x200b
++#define MASK_CUSTOM0_RS1  0x707f
++#define MATCH_CUSTOM0_RS1_RS2 0x300b
++#define MASK_CUSTOM0_RS1_RS2  0x707f
++#define MATCH_CUSTOM1 0x2b
++#define MASK_CUSTOM1  0x707f
++#define MATCH_CUSTOM1_RD 0x402b
++#define MASK_CUSTOM1_RD  0x707f
++#define MATCH_CUSTOM1_RD_RS1 0x602b
++#define MASK_CUSTOM1_RD_RS1  0x707f
++#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
++#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM1_RS1 0x202b
++#define MASK_CUSTOM1_RS1  0x707f
++#define MATCH_CUSTOM1_RS1_RS2 0x302b
++#define MASK_CUSTOM1_RS1_RS2  0x707f
++#define MATCH_CUSTOM2 0x5b
++#define MASK_CUSTOM2  0x707f
++#define MATCH_CUSTOM2_RD 0x405b
++#define MASK_CUSTOM2_RD  0x707f
++#define MATCH_CUSTOM2_RD_RS1 0x605b
++#define MASK_CUSTOM2_RD_RS1  0x707f
++#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
++#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM2_RS1 0x205b
++#define MASK_CUSTOM2_RS1  0x707f
++#define MATCH_CUSTOM2_RS1_RS2 0x305b
++#define MASK_CUSTOM2_RS1_RS2  0x707f
++#define MATCH_CUSTOM3 0x7b
++#define MASK_CUSTOM3  0x707f
++#define MATCH_CUSTOM3_RD 0x407b
++#define MASK_CUSTOM3_RD  0x707f
++#define MATCH_CUSTOM3_RD_RS1 0x607b
++#define MASK_CUSTOM3_RD_RS1  0x707f
++#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
++#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM3_RS1 0x207b
++#define MASK_CUSTOM3_RS1  0x707f
++#define MATCH_CUSTOM3_RS1_RS2 0x307b
++#define MASK_CUSTOM3_RS1_RS2  0x707f
++#define MATCH_DIV 0x2004033
++#define MASK_DIV  0xfe00707f
++#define MATCH_DIVU 0x2005033
++#define MASK_DIVU  0xfe00707f
++#define MATCH_DIVUW 0x200503b
++#define MASK_DIVUW  0xfe00707f
++#define MATCH_DIVW 0x200403b
++#define MASK_DIVW  0xfe00707f
++#define MATCH_EBREAK 0x100073
++#define MASK_EBREAK  0xffffffff
++#define MATCH_ECALL 0x73
++#define MASK_ECALL  0xffffffff
++#define MATCH_ERET 0x10000073
++#define MASK_ERET  0xffffffff
++#define MATCH_FADD_D 0x2000053
++#define MASK_FADD_D  0xfe00007f
++#define MATCH_FADD_H 0x4000053
++#define MASK_FADD_H  0xfe00007f
++#define MATCH_FADD_S 0x53
++#define MASK_FADD_S  0xfe00007f
++#define MATCH_FCLASS_D 0xe2001053
++#define MASK_FCLASS_D  0xfff0707f
++#define MATCH_FCLASS_S 0xe0001053
++#define MASK_FCLASS_S  0xfff0707f
++#define MATCH_FCVT_D_H 0x8c000053
++#define MASK_FCVT_D_H  0xfff0007f
++#define MATCH_FCVT_D_L 0xd2200053
++#define MASK_FCVT_D_L  0xfff0007f
++#define MATCH_FCVT_D_LU 0xd2300053
++#define MASK_FCVT_D_LU  0xfff0007f
++#define MATCH_FCVT_D_S 0x42000053
++#define MASK_FCVT_D_S  0xfff0007f
++#define MATCH_FCVT_D_W 0xd2000053
++#define MASK_FCVT_D_W  0xfff0007f
++#define MATCH_FCVT_D_WU 0xd2100053
++#define MASK_FCVT_D_WU  0xfff0007f
++#define MATCH_FCVT_H_D 0x92000053
++#define MASK_FCVT_H_D  0xfff0007f
++#define MATCH_FCVT_H_L 0x64000053
++#define MASK_FCVT_H_L  0xfff0007f
++#define MATCH_FCVT_H_LU 0x6c000053
++#define MASK_FCVT_H_LU  0xfff0007f
++#define MATCH_FCVT_H_S 0x90000053
++#define MASK_FCVT_H_S  0xfff0007f
++#define MATCH_FCVT_H_W 0x74000053
++#define MASK_FCVT_H_W  0xfff0007f
++#define MATCH_FCVT_H_WU 0x7c000053
++#define MASK_FCVT_H_WU  0xfff0007f
++#define MATCH_FCVT_L_D 0xc2200053
++#define MASK_FCVT_L_D  0xfff0007f
++#define MATCH_FCVT_L_H 0x44000053
++#define MASK_FCVT_L_H  0xfff0007f
++#define MATCH_FCVT_L_S 0xc0200053
++#define MASK_FCVT_L_S  0xfff0007f
++#define MATCH_FCVT_LU_D 0xc2300053
++#define MASK_FCVT_LU_D  0xfff0007f
++#define MATCH_FCVT_LU_H 0x4c000053
++#define MASK_FCVT_LU_H  0xfff0007f
++#define MATCH_FCVT_LU_S 0xc0300053
++#define MASK_FCVT_LU_S  0xfff0007f
++#define MATCH_FCVT_S_D 0x40100053
++#define MASK_FCVT_S_D  0xfff0007f
++#define MATCH_FCVT_S_H 0x84000053
++#define MASK_FCVT_S_H  0xfff0007f
++#define MATCH_FCVT_S_L 0xd0200053
++#define MASK_FCVT_S_L  0xfff0007f
++#define MATCH_FCVT_S_LU 0xd0300053
++#define MASK_FCVT_S_LU  0xfff0007f
++#define MATCH_FCVT_S_W 0xd0000053
++#define MASK_FCVT_S_W  0xfff0007f
++#define MATCH_FCVT_S_WU 0xd0100053
++#define MASK_FCVT_S_WU  0xfff0007f
++#define MATCH_FCVT_W_D 0xc2000053
++#define MASK_FCVT_W_D  0xfff0007f
++#define MATCH_FCVT_W_H 0x54000053
++#define MASK_FCVT_W_H  0xfff0007f
++#define MATCH_FCVT_W_S 0xc0000053
++#define MASK_FCVT_W_S  0xfff0007f
++#define MATCH_FCVT_WU_D 0xc2100053
++#define MASK_FCVT_WU_D  0xfff0007f
++#define MATCH_FCVT_WU_H 0x5c000053
++#define MASK_FCVT_WU_H  0xfff0007f
++#define MATCH_FCVT_WU_S 0xc0100053
++#define MASK_FCVT_WU_S  0xfff0007f
++#define MATCH_FDIV_D 0x1a000053
++#define MASK_FDIV_D  0xfe00007f
++#define MATCH_FDIV_H 0x1c000053
++#define MASK_FDIV_H  0xfe00007f
++#define MATCH_FDIV_S 0x18000053
++#define MASK_FDIV_S  0xfe00007f
++#define MATCH_FENCE 0xf
++#define MASK_FENCE  0x707f
++#define MATCH_FENCE_I 0x100f
++#define MASK_FENCE_I  0x707f
++#define MATCH_FEQ_D 0xa2002053
++#define MASK_FEQ_D  0xfe00707f
++#define MATCH_FEQ_H 0xac000053
++#define MASK_FEQ_H  0xfe00707f
++#define MATCH_FEQ_S 0xa0002053
++#define MASK_FEQ_S  0xfe00707f
++#define MATCH_FLD 0x3007
++#define MASK_FLD  0x707f
++#define MATCH_FLE_D 0xa2000053
++#define MASK_FLE_D  0xfe00707f
++#define MATCH_FLE_H 0xbc000053
++#define MASK_FLE_H  0xfe00707f
++#define MATCH_FLE_S 0xa0000053
++#define MASK_FLE_S  0xfe00707f
++#define MATCH_FLH 0x1007
++#define MASK_FLH  0x707f
++#define MATCH_FLT_D 0xa2001053
++#define MASK_FLT_D  0xfe00707f
++#define MATCH_FLT_H 0xb4000053
++#define MASK_FLT_H  0xfe00707f
++#define MATCH_FLT_S 0xa0001053
++#define MASK_FLT_S  0xfe00707f
++#define MATCH_FLW 0x2007
++#define MASK_FLW  0x707f
++#define MATCH_FMADD_D 0x2000043
++#define MASK_FMADD_D  0x600007f
++#define MATCH_FMADD_H 0x4000043
++#define MASK_FMADD_H  0x600007f
++#define MATCH_FMADD_S 0x43
++#define MASK_FMADD_S  0x600007f
++#define MATCH_FMAX_D 0x2a001053
++#define MASK_FMAX_D  0xfe00707f
++#define MATCH_FMAX_H 0xcc000053
++#define MASK_FMAX_H  0xfe00707f
++#define MATCH_FMAX_S 0x28001053
++#define MASK_FMAX_S  0xfe00707f
++#define MATCH_FMIN_D 0x2a000053
++#define MASK_FMIN_D  0xfe00707f
++#define MATCH_FMIN_H 0xc4000053
++#define MASK_FMIN_H  0xfe00707f
++#define MATCH_FMIN_S 0x28000053
++#define MASK_FMIN_S  0xfe00707f
++#define MATCH_FMOVN 0x6007077
++#define MASK_FMOVN  0xfe00707f
++#define MATCH_FMOVZ 0x4007077
++#define MASK_FMOVZ  0xfe00707f
++#define MATCH_FMSUB_D 0x2000047
++#define MASK_FMSUB_D  0x600007f
++#define MATCH_FMSUB_H 0x4000047
++#define MASK_FMSUB_H  0x600007f
++#define MATCH_FMSUB_S 0x47
++#define MASK_FMSUB_S  0x600007f
++#define MATCH_FMUL_D 0x12000053
++#define MASK_FMUL_D  0xfe00007f
++#define MATCH_FMUL_H 0x14000053
++#define MASK_FMUL_H  0xfe00007f
++#define MATCH_FMUL_S 0x10000053
++#define MASK_FMUL_S  0xfe00007f
++#define MATCH_FMV_D_X 0xf2000053
++#define MASK_FMV_D_X  0xfff0707f
++#define MATCH_FMV_H_X 0xf4000053
++#define MASK_FMV_H_X  0xfff0707f
++#define MATCH_FMV_S_X 0xf0000053
++#define MASK_FMV_S_X  0xfff0707f
++#define MATCH_FMV_X_D 0xe2000053
++#define MASK_FMV_X_D  0xfff0707f
++#define MATCH_FMV_X_H 0xe4000053
++#define MASK_FMV_X_H  0xfff0707f
++#define MATCH_FMV_X_S 0xe0000053
++#define MASK_FMV_X_S  0xfff0707f
++#define MATCH_FNMADD_D 0x200004f
++#define MASK_FNMADD_D  0x600007f
++#define MATCH_FNMADD_H 0x400004f
++#define MASK_FNMADD_H  0x600007f
++#define MATCH_FNMADD_S 0x4f
++#define MASK_FNMADD_S  0x600007f
++#define MATCH_FNMSUB_D 0x200004b
++#define MASK_FNMSUB_D  0x600007f
++#define MATCH_FNMSUB_H 0x400004b
++#define MASK_FNMSUB_H  0x600007f
++#define MATCH_FNMSUB_S 0x4b
++#define MASK_FNMSUB_S  0x600007f
++#define MATCH_FRCSR 0x302073
++#define MASK_FRCSR  0xfffff07f
++#define MATCH_FRFLAGS 0x102073
++#define MASK_FRFLAGS  0xfffff07f
++#define MATCH_FRRM 0x202073
++#define MASK_FRRM  0xfffff07f
++#define MATCH_FSCSR 0x301073
++#define MASK_FSCSR  0xfff0707f
++#define MATCH_FSD 0x3027
++#define MASK_FSD  0x707f
++#define MATCH_FSFLAGS 0x101073
++#define MASK_FSFLAGS  0xfff0707f
++#define MATCH_FSFLAGSI 0x105073
++#define MASK_FSFLAGSI  0xfff0707f
++#define MATCH_FSGNJ_D 0x22000053
++#define MASK_FSGNJ_D  0xfe00707f
++#define MATCH_FSGNJ_H 0x2c000053
++#define MASK_FSGNJ_H  0xfe00707f
++#define MATCH_FSGNJ_S 0x20000053
++#define MASK_FSGNJ_S  0xfe00707f
++#define MATCH_FSGNJN_D 0x22001053
++#define MASK_FSGNJN_D  0xfe00707f
++#define MATCH_FSGNJN_H 0x34000053
++#define MASK_FSGNJN_H  0xfe00707f
++#define MATCH_FSGNJN_S 0x20001053
++#define MASK_FSGNJN_S  0xfe00707f
++#define MATCH_FSGNJX_D 0x22002053
++#define MASK_FSGNJX_D  0xfe00707f
++#define MATCH_FSGNJX_H 0x3c000053
++#define MASK_FSGNJX_H  0xfe00707f
++#define MATCH_FSGNJX_S 0x20002053
++#define MASK_FSGNJX_S  0xfe00707f
++#define MATCH_FSH 0x1027
++#define MASK_FSH  0x707f
++#define MATCH_FSQRT_D 0x5a000053
++#define MASK_FSQRT_D  0xfff0007f
++#define MATCH_FSQRT_H 0x24000053
++#define MASK_FSQRT_H  0xfff0007f
++#define MATCH_FSQRT_S 0x58000053
++#define MASK_FSQRT_S  0xfff0007f
++#define MATCH_FSRM 0x201073
++#define MASK_FSRM  0xfff0707f
++#define MATCH_FSRMI 0x205073
++#define MASK_FSRMI  0xfff0707f
++#define MATCH_FSUB_D 0xa000053
++#define MASK_FSUB_D  0xfe00007f
++#define MATCH_FSUB_H 0xc000053
++#define MASK_FSUB_H  0xfe00007f
++#define MATCH_FSUB_S 0x8000053
++#define MASK_FSUB_S  0xfe00007f
++#define MATCH_FSW 0x2027
++#define MASK_FSW  0x707f
++#define MATCH_HRTS 0x20500073
++#define MASK_HRTS  0xffffffff
++#define MATCH_JAL 0x6f
++#define MASK_JAL  0x7f
++#define MATCH_JALR 0x67
++#define MASK_JALR  0x707f
++#define MATCH_LB 0x3
++#define MASK_LB  0x707f
++#define MATCH_LBU 0x4003
++#define MASK_LBU  0x707f
++#define MATCH_LD 0x3003
++#define MASK_LD  0x707f
++#define MATCH_LH 0x1003
++#define MASK_LH  0x707f
++#define MATCH_LHU 0x5003
++#define MASK_LHU  0x707f
++#define MATCH_LR_D 0x1000302f
++#define MASK_LR_D  0xf9f0707f
++#define MATCH_LR_W 0x1000202f
++#define MASK_LR_W  0xf9f0707f
++#define MATCH_LUI 0x37
++#define MASK_LUI  0x7f
++#define MATCH_LW 0x2003
++#define MASK_LW  0x707f
++#define MATCH_LWU 0x6003
++#define MASK_LWU  0x707f
++#define MATCH_MOVN 0x2007077
++#define MASK_MOVN  0xfe00707f
++#define MATCH_MOVZ 0x7077
++#define MASK_MOVZ  0xfe00707f
++#define MATCH_MRTH 0x30600073
++#define MASK_MRTH  0xffffffff
++#define MATCH_MRTS 0x30500073
++#define MASK_MRTS  0xffffffff
++#define MATCH_MUL 0x2000033
++#define MASK_MUL  0xfe00707f
++#define MATCH_MULH 0x2001033
++#define MASK_MULH  0xfe00707f
++#define MATCH_MULHSU 0x2002033
++#define MASK_MULHSU  0xfe00707f
++#define MATCH_MULHU 0x2003033
++#define MASK_MULHU  0xfe00707f
++#define MATCH_MULW 0x200003b
++#define MASK_MULW  0xfe00707f
++#define MATCH_OR 0x6033
++#define MASK_OR  0xfe00707f
++#define MATCH_ORI 0x6013
++#define MASK_ORI  0x707f
++#define MATCH_RDCYCLE 0xc0002073
++#define MASK_RDCYCLE  0xfffff07f
++#define MATCH_RDCYCLEH 0xc8002073
++#define MASK_RDCYCLEH  0xfffff07f
++#define MATCH_RDINSTRET 0xc0202073
++#define MASK_RDINSTRET  0xfffff07f
++#define MATCH_RDINSTRETH 0xc8202073
++#define MASK_RDINSTRETH  0xfffff07f
++#define MATCH_RDTIME 0xc0102073
++#define MASK_RDTIME  0xfffff07f
++#define MATCH_RDTIMEH 0xc8102073
++#define MASK_RDTIMEH  0xfffff07f
++#define MATCH_REM 0x2006033
++#define MASK_REM  0xfe00707f
++#define MATCH_REMU 0x2007033
++#define MASK_REMU  0xfe00707f
++#define MATCH_REMUW 0x200703b
++#define MASK_REMUW  0xfe00707f
++#define MATCH_REMW 0x200603b
++#define MASK_REMW  0xfe00707f
++#define MATCH_SB 0x23
++#define MASK_SB  0x707f
++#define MATCH_SBREAK 0x100073
++#define MASK_SBREAK  0xffffffff
++#define MATCH_SC_D 0x1800302f
++#define MASK_SC_D  0xf800707f
++#define MATCH_SC_W 0x1800202f
++#define MASK_SC_W  0xf800707f
++#define MATCH_SCALL 0x73
++#define MASK_SCALL  0xffffffff
++#define MATCH_SD 0x3023
++#define MASK_SD  0x707f
++#define MATCH_SFENCE_VM 0x10100073
++#define MASK_SFENCE_VM  0xfff07fff
++#define MATCH_SH 0x1023
++#define MASK_SH  0x707f
++#define MATCH_SLL 0x1033
++#define MASK_SLL  0xfe00707f
++#define MATCH_SLLI 0x1013
++#define MASK_SLLI  0xfc00707f
++#define MATCH_SLLI_RV32 0x1013
++#define MASK_SLLI_RV32  0xfe00707f
++#define MATCH_SLLIW 0x101b
++#define MASK_SLLIW  0xfe00707f
++#define MATCH_SLLW 0x103b
++#define MASK_SLLW  0xfe00707f
++#define MATCH_SLT 0x2033
++#define MASK_SLT  0xfe00707f
++#define MATCH_SLTI 0x2013
++#define MASK_SLTI  0x707f
++#define MATCH_SLTIU 0x3013
++#define MASK_SLTIU  0x707f
++#define MATCH_SLTU 0x3033
++#define MASK_SLTU  0xfe00707f
++#define MATCH_SRA 0x40005033
++#define MASK_SRA  0xfe00707f
++#define MATCH_SRAI 0x40005013
++#define MASK_SRAI  0xfc00707f
++#define MATCH_SRAI_RV32 0x40005013
++#define MASK_SRAI_RV32  0xfe00707f
++#define MATCH_SRAIW 0x4000501b
++#define MASK_SRAIW  0xfe00707f
++#define MATCH_SRAW 0x4000503b
++#define MASK_SRAW  0xfe00707f
++#define MATCH_SRET 0x10000073
++#define MASK_SRET  0xffffffff
++#define MATCH_SRL 0x5033
++#define MASK_SRL  0xfe00707f
++#define MATCH_SRLI 0x5013
++#define MASK_SRLI  0xfc00707f
++#define MATCH_SRLI_RV32 0x5013
++#define MASK_SRLI_RV32  0xfe00707f
++#define MATCH_SRLIW 0x501b
++#define MASK_SRLIW  0xfe00707f
++#define MATCH_SRLW 0x503b
++#define MASK_SRLW  0xfe00707f
++#define MATCH_STOP 0x5077
++#define MASK_STOP  0xffffffff
++#define MATCH_SUB 0x40000033
++#define MASK_SUB  0xfe00707f
++#define MATCH_SUBW 0x4000003b
++#define MASK_SUBW  0xfe00707f
++#define MATCH_SW 0x2023
++#define MASK_SW  0x707f
++#define MATCH_UTIDX 0x6077
++#define MASK_UTIDX  0xfffff07f
++#define MATCH_VENQCMD 0xa00302b
++#define MASK_VENQCMD  0xfe007fff
++#define MATCH_VENQCNT 0x1000302b
++#define MASK_VENQCNT  0xfe007fff
++#define MATCH_VENQIMM1 0xc00302b
++#define MASK_VENQIMM1  0xfe007fff
++#define MATCH_VENQIMM2 0xe00302b
++#define MASK_VENQIMM2  0xfe007fff
++#define MATCH_VF 0x10202b
++#define MASK_VF  0x1f0707f
++#define MATCH_VFLD 0x1600205b
++#define MASK_VFLD  0xfff0707f
++#define MATCH_VFLSEGD 0x1600205b
++#define MASK_VFLSEGD  0x1ff0707f
++#define MATCH_VFLSEGSTD 0x1600305b
++#define MASK_VFLSEGSTD  0x1e00707f
++#define MATCH_VFLSEGSTW 0x1400305b
++#define MASK_VFLSEGSTW  0x1e00707f
++#define MATCH_VFLSEGW 0x1400205b
++#define MASK_VFLSEGW  0x1ff0707f
++#define MATCH_VFLSTD 0x1600305b
++#define MASK_VFLSTD  0xfe00707f
++#define MATCH_VFLSTW 0x1400305b
++#define MASK_VFLSTW  0xfe00707f
++#define MATCH_VFLW 0x1400205b
++#define MASK_VFLW  0xfff0707f
++#define MATCH_VFMSV_D 0x1200202b
++#define MASK_VFMSV_D  0xfff0707f
++#define MATCH_VFMSV_S 0x1000202b
++#define MASK_VFMSV_S  0xfff0707f
++#define MATCH_VFMVV 0x1000002b
++#define MASK_VFMVV  0xfff0707f
++#define MATCH_VFSD 0x1600207b
++#define MASK_VFSD  0xfff0707f
++#define MATCH_VFSSEGD 0x1600207b
++#define MASK_VFSSEGD  0x1ff0707f
++#define MATCH_VFSSEGSTD 0x1600307b
++#define MASK_VFSSEGSTD  0x1e00707f
++#define MATCH_VFSSEGSTW 0x1400307b
++#define MASK_VFSSEGSTW  0x1e00707f
++#define MATCH_VFSSEGW 0x1400207b
++#define MASK_VFSSEGW  0x1ff0707f
++#define MATCH_VFSSTD 0x1600307b
++#define MASK_VFSSTD  0xfe00707f
++#define MATCH_VFSSTW 0x1400307b
++#define MASK_VFSSTW  0xfe00707f
++#define MATCH_VFSW 0x1400207b
++#define MASK_VFSW  0xfff0707f
++#define MATCH_VGETCFG 0x400b
++#define MASK_VGETCFG  0xfffff07f
++#define MATCH_VGETVL 0x200400b
++#define MASK_VGETVL  0xfffff07f
++#define MATCH_VLB 0x205b
++#define MASK_VLB  0xfff0707f
++#define MATCH_VLBU 0x800205b
++#define MASK_VLBU  0xfff0707f
++#define MATCH_VLD 0x600205b
++#define MASK_VLD  0xfff0707f
++#define MATCH_VLH 0x200205b
++#define MASK_VLH  0xfff0707f
++#define MATCH_VLHU 0xa00205b
++#define MASK_VLHU  0xfff0707f
++#define MATCH_VLSEGB 0x205b
++#define MASK_VLSEGB  0x1ff0707f
++#define MATCH_VLSEGBU 0x800205b
++#define MASK_VLSEGBU  0x1ff0707f
++#define MATCH_VLSEGD 0x600205b
++#define MASK_VLSEGD  0x1ff0707f
++#define MATCH_VLSEGH 0x200205b
++#define MASK_VLSEGH  0x1ff0707f
++#define MATCH_VLSEGHU 0xa00205b
++#define MASK_VLSEGHU  0x1ff0707f
++#define MATCH_VLSEGSTB 0x305b
++#define MASK_VLSEGSTB  0x1e00707f
++#define MATCH_VLSEGSTBU 0x800305b
++#define MASK_VLSEGSTBU  0x1e00707f
++#define MATCH_VLSEGSTD 0x600305b
++#define MASK_VLSEGSTD  0x1e00707f
++#define MATCH_VLSEGSTH 0x200305b
++#define MASK_VLSEGSTH  0x1e00707f
++#define MATCH_VLSEGSTHU 0xa00305b
++#define MASK_VLSEGSTHU  0x1e00707f
++#define MATCH_VLSEGSTW 0x400305b
++#define MASK_VLSEGSTW  0x1e00707f
++#define MATCH_VLSEGSTWU 0xc00305b
++#define MASK_VLSEGSTWU  0x1e00707f
++#define MATCH_VLSEGW 0x400205b
++#define MASK_VLSEGW  0x1ff0707f
++#define MATCH_VLSEGWU 0xc00205b
++#define MASK_VLSEGWU  0x1ff0707f
++#define MATCH_VLSTB 0x305b
++#define MASK_VLSTB  0xfe00707f
++#define MATCH_VLSTBU 0x800305b
++#define MASK_VLSTBU  0xfe00707f
++#define MATCH_VLSTD 0x600305b
++#define MASK_VLSTD  0xfe00707f
++#define MATCH_VLSTH 0x200305b
++#define MASK_VLSTH  0xfe00707f
++#define MATCH_VLSTHU 0xa00305b
++#define MASK_VLSTHU  0xfe00707f
++#define MATCH_VLSTW 0x400305b
++#define MASK_VLSTW  0xfe00707f
++#define MATCH_VLSTWU 0xc00305b
++#define MASK_VLSTWU  0xfe00707f
++#define MATCH_VLW 0x400205b
++#define MASK_VLW  0xfff0707f
++#define MATCH_VLWU 0xc00205b
++#define MASK_VLWU  0xfff0707f
++#define MATCH_VMSV 0x200202b
++#define MASK_VMSV  0xfff0707f
++#define MATCH_VMVV 0x200002b
++#define MASK_VMVV  0xfff0707f
++#define MATCH_VSB 0x207b
++#define MASK_VSB  0xfff0707f
++#define MATCH_VSD 0x600207b
++#define MASK_VSD  0xfff0707f
++#define MATCH_VSETCFG 0x200b
++#define MASK_VSETCFG  0x7fff
++#define MATCH_VSETVL 0x600b
++#define MASK_VSETVL  0xfff0707f
++#define MATCH_VSH 0x200207b
++#define MASK_VSH  0xfff0707f
++#define MATCH_VSSEGB 0x207b
++#define MASK_VSSEGB  0x1ff0707f
++#define MATCH_VSSEGD 0x600207b
++#define MASK_VSSEGD  0x1ff0707f
++#define MATCH_VSSEGH 0x200207b
++#define MASK_VSSEGH  0x1ff0707f
++#define MATCH_VSSEGSTB 0x307b
++#define MASK_VSSEGSTB  0x1e00707f
++#define MATCH_VSSEGSTD 0x600307b
++#define MASK_VSSEGSTD  0x1e00707f
++#define MATCH_VSSEGSTH 0x200307b
++#define MASK_VSSEGSTH  0x1e00707f
++#define MATCH_VSSEGSTW 0x400307b
++#define MASK_VSSEGSTW  0x1e00707f
++#define MATCH_VSSEGW 0x400207b
++#define MASK_VSSEGW  0x1ff0707f
++#define MATCH_VSSTB 0x307b
++#define MASK_VSSTB  0xfe00707f
++#define MATCH_VSSTD 0x600307b
++#define MASK_VSSTD  0xfe00707f
++#define MATCH_VSSTH 0x200307b
++#define MASK_VSSTH  0xfe00707f
++#define MATCH_VSSTW 0x400307b
++#define MASK_VSSTW  0xfe00707f
++#define MATCH_VSW 0x400207b
++#define MASK_VSW  0xfff0707f
++#define MATCH_VXCPTAUX 0x200402b
++#define MASK_VXCPTAUX  0xfffff07f
++#define MATCH_VXCPTCAUSE 0x402b
++#define MASK_VXCPTCAUSE  0xfffff07f
++#define MATCH_VXCPTEVAC 0x600302b
++#define MASK_VXCPTEVAC  0xfff07fff
++#define MATCH_VXCPTHOLD 0x800302b
++#define MASK_VXCPTHOLD  0xfff07fff
++#define MATCH_VXCPTKILL 0x400302b
++#define MASK_VXCPTKILL  0xffffffff
++#define MATCH_VXCPTRESTORE 0x200302b
++#define MASK_VXCPTRESTORE  0xfff07fff
++#define MATCH_VXCPTSAVE 0x302b
++#define MASK_VXCPTSAVE  0xfff07fff
++#define MATCH_WFI 0x10200073
++#define MASK_WFI  0xffffffff
++#define MATCH_XOR 0x4033
++#define MASK_XOR  0xfe00707f
++#define MATCH_XORI 0x4013
++#define MASK_XORI  0x707f
++#define CSR_FFLAGS 0x1
++#define CSR_FRM 0x2
++#define CSR_FCSR 0x3
++#define CSR_CYCLE 0xc00
++#define CSR_TIME 0xc01
++#define CSR_INSTRET 0xc02
++#define CSR_STATS 0xc0
++#define CSR_UARCH0 0xcc0
++#define CSR_UARCH1 0xcc1
++#define CSR_UARCH2 0xcc2
++#define CSR_UARCH3 0xcc3
++#define CSR_UARCH4 0xcc4
++#define CSR_UARCH5 0xcc5
++#define CSR_UARCH6 0xcc6
++#define CSR_UARCH7 0xcc7
++#define CSR_UARCH8 0xcc8
++#define CSR_UARCH9 0xcc9
++#define CSR_UARCH10 0xcca
++#define CSR_UARCH11 0xccb
++#define CSR_UARCH12 0xccc
++#define CSR_UARCH13 0xccd
++#define CSR_UARCH14 0xcce
++#define CSR_UARCH15 0xccf
++#define CSR_SSTATUS 0x100
++#define CSR_STVEC 0x101
++#define CSR_SIE 0x104
++#define CSR_SSCRATCH 0x140
++#define CSR_SEPC 0x141
++#define CSR_SIP 0x144
++#define CSR_SPTBR 0x180
++#define CSR_SASID 0x181
++#define CSR_CYCLEW 0x900
++#define CSR_TIMEW 0x901
++#define CSR_INSTRETW 0x902
++#define CSR_STIME 0xd01
++#define CSR_SCAUSE 0xd42
++#define CSR_SBADADDR 0xd43
++#define CSR_STIMEW 0xa01
++#define CSR_MSTATUS 0x300
++#define CSR_MTVEC 0x301
++#define CSR_MTDELEG 0x302
++#define CSR_MIE 0x304
++#define CSR_MTIMECMP 0x321
++#define CSR_MSCRATCH 0x340
++#define CSR_MEPC 0x341
++#define CSR_MCAUSE 0x342
++#define CSR_MBADADDR 0x343
++#define CSR_MIP 0x344
++#define CSR_MTIME 0x701
++#define CSR_MCPUID 0xf00
++#define CSR_MIMPID 0xf01
++#define CSR_MHARTID 0xf10
++#define CSR_MTOHOST 0x780
++#define CSR_MFROMHOST 0x781
++#define CSR_MRESET 0x782
++#define CSR_SEND_IPI 0x783
++#define CSR_CYCLEH 0xc80
++#define CSR_TIMEH 0xc81
++#define CSR_INSTRETH 0xc82
++#define CSR_CYCLEHW 0x980
++#define CSR_TIMEHW 0x981
++#define CSR_INSTRETHW 0x982
++#define CSR_STIMEH 0xd81
++#define CSR_STIMEHW 0xa81
++#define CSR_MTIMECMPH 0x361
++#define CSR_MTIMEH 0x741
++#define CAUSE_MISALIGNED_FETCH 0x0
++#define CAUSE_FAULT_FETCH 0x1
++#define CAUSE_ILLEGAL_INSTRUCTION 0x2
++#define CAUSE_BREAKPOINT 0x3
++#define CAUSE_MISALIGNED_LOAD 0x4
++#define CAUSE_FAULT_LOAD 0x5
++#define CAUSE_MISALIGNED_STORE 0x6
++#define CAUSE_FAULT_STORE 0x7
++#define CAUSE_USER_ECALL 0x8
++#define CAUSE_SUPERVISOR_ECALL 0x9
++#define CAUSE_HYPERVISOR_ECALL 0xa
++#define CAUSE_MACHINE_ECALL 0xb
++#endif
++#ifdef DECLARE_INSN
++DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
++DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
++DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
++DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
++DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
++DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
++DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
++DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
++DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
++DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
++DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
++DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
++DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
++DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
++DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
++DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
++DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
++DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
++DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
++DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
++DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
++DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
++DECLARE_INSN(and, MATCH_AND, MASK_AND)
++DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
++DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
++DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
++DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
++DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
++DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
++DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
++DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
++DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
++DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
++DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
++DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
++DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
++DECLARE_INSN(c_addin, MATCH_C_ADDIN, MASK_C_ADDIN)
++DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
++DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
++DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
++DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
++DECLARE_INSN(c_andin, MATCH_C_ANDIN, MASK_C_ANDIN)
++DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
++DECLARE_INSN(c_bgez, MATCH_C_BGEZ, MASK_C_BGEZ)
++DECLARE_INSN(c_bltz, MATCH_C_BLTZ, MASK_C_BLTZ)
++DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
++DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
++DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
++DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
++DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
++DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
++DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
++DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
++DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
++DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
++DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
++DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
++DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
++DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
++DECLARE_INSN(c_orin, MATCH_C_ORIN, MASK_C_ORIN)
++DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
++DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
++DECLARE_INSN(c_sll, MATCH_C_SLL, MASK_C_SLL)
++DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
++DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
++DECLARE_INSN(c_sllr, MATCH_C_SLLR, MASK_C_SLLR)
++DECLARE_INSN(c_slt, MATCH_C_SLT, MASK_C_SLT)
++DECLARE_INSN(c_sltr, MATCH_C_SLTR, MASK_C_SLTR)
++DECLARE_INSN(c_sltu, MATCH_C_SLTU, MASK_C_SLTU)
++DECLARE_INSN(c_sltur, MATCH_C_SLTUR, MASK_C_SLTUR)
++DECLARE_INSN(c_sra, MATCH_C_SRA, MASK_C_SRA)
++DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
++DECLARE_INSN(c_srl, MATCH_C_SRL, MASK_C_SRL)
++DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
++DECLARE_INSN(c_srlr, MATCH_C_SRLR, MASK_C_SRLR)
++DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
++DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
++DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
++DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
++DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
++DECLARE_INSN(c_xorin, MATCH_C_XORIN, MASK_C_XORIN)
++DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
++DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
++DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
++DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
++DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
++DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
++DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
++DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
++DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
++DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
++DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
++DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
++DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
++DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
++DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
++DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
++DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
++DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
++DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
++DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
++DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
++DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
++DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
++DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
++DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
++DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
++DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
++DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
++DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
++DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
++DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
++DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
++DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
++DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
++DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
++DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
++DECLARE_INSN(eret, MATCH_ERET, MASK_ERET)
++DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
++DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
++DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
++DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
++DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
++DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
++DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
++DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
++DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
++DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
++DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
++DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
++DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
++DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
++DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
++DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
++DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
++DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
++DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
++DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
++DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
++DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
++DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
++DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
++DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
++DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
++DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
++DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
++DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
++DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
++DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
++DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
++DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
++DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
++DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
++DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
++DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
++DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
++DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
++DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
++DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
++DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
++DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
++DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
++DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
++DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
++DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
++DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
++DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
++DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
++DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
++DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
++DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
++DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
++DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
++DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
++DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
++DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
++DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
++DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
++DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
++DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
++DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
++DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
++DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
++DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
++DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
++DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
++DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
++DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
++DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
++DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
++DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
++DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
++DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
++DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
++DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
++DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
++DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
++DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
++DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
++DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
++DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
++DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
++DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
++DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
++DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
++DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
++DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
++DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
++DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
++DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
++DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
++DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
++DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
++DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
++DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
++DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
++DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
++DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
++DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
++DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
++DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
++DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
++DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
++DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
++DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
++DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS)
++DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
++DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
++DECLARE_INSN(lb, MATCH_LB, MASK_LB)
++DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
++DECLARE_INSN(ld, MATCH_LD, MASK_LD)
++DECLARE_INSN(lh, MATCH_LH, MASK_LH)
++DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
++DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
++DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
++DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
++DECLARE_INSN(lw, MATCH_LW, MASK_LW)
++DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
++DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
++DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
++DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH)
++DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS)
++DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
++DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
++DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
++DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
++DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
++DECLARE_INSN(or, MATCH_OR, MASK_OR)
++DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
++DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
++DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
++DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
++DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
++DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
++DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
++DECLARE_INSN(rem, MATCH_REM, MASK_REM)
++DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
++DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
++DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
++DECLARE_INSN(sb, MATCH_SB, MASK_SB)
++DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
++DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
++DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
++DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
++DECLARE_INSN(sd, MATCH_SD, MASK_SD)
++DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
++DECLARE_INSN(sh, MATCH_SH, MASK_SH)
++DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
++DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
++DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
++DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
++DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
++DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
++DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
++DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
++DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
++DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
++DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
++DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
++DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
++DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
++DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
++DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
++DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
++DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
++DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
++DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
++DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
++DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
++DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
++DECLARE_INSN(sw, MATCH_SW, MASK_SW)
++DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
++DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
++DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
++DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
++DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
++DECLARE_INSN(vf, MATCH_VF, MASK_VF)
++DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
++DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
++DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
++DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
++DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
++DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
++DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
++DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
++DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
++DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
++DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
++DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
++DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
++DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
++DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
++DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
++DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
++DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
++DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
++DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
++DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
++DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
++DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
++DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
++DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
++DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
++DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
++DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
++DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
++DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
++DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
++DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
++DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
++DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
++DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
++DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
++DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
++DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
++DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
++DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
++DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
++DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
++DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
++DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
++DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
++DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
++DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
++DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
++DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
++DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
++DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
++DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
++DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
++DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
++DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
++DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
++DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
++DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
++DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
++DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
++DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
++DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
++DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
++DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
++DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
++DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
++DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
++DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
++DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
++DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
++DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
++DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
++DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
++DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
++DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
++DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
++DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
++DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
++DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
++#endif
++#ifdef DECLARE_CSR
++DECLARE_CSR(fflags, CSR_FFLAGS)
++DECLARE_CSR(frm, CSR_FRM)
++DECLARE_CSR(fcsr, CSR_FCSR)
++DECLARE_CSR(cycle, CSR_CYCLE)
++DECLARE_CSR(time, CSR_TIME)
++DECLARE_CSR(instret, CSR_INSTRET)
++DECLARE_CSR(stats, CSR_STATS)
++DECLARE_CSR(uarch0, CSR_UARCH0)
++DECLARE_CSR(uarch1, CSR_UARCH1)
++DECLARE_CSR(uarch2, CSR_UARCH2)
++DECLARE_CSR(uarch3, CSR_UARCH3)
++DECLARE_CSR(uarch4, CSR_UARCH4)
++DECLARE_CSR(uarch5, CSR_UARCH5)
++DECLARE_CSR(uarch6, CSR_UARCH6)
++DECLARE_CSR(uarch7, CSR_UARCH7)
++DECLARE_CSR(uarch8, CSR_UARCH8)
++DECLARE_CSR(uarch9, CSR_UARCH9)
++DECLARE_CSR(uarch10, CSR_UARCH10)
++DECLARE_CSR(uarch11, CSR_UARCH11)
++DECLARE_CSR(uarch12, CSR_UARCH12)
++DECLARE_CSR(uarch13, CSR_UARCH13)
++DECLARE_CSR(uarch14, CSR_UARCH14)
++DECLARE_CSR(uarch15, CSR_UARCH15)
++DECLARE_CSR(sstatus, CSR_SSTATUS)
++DECLARE_CSR(stvec, CSR_STVEC)
++DECLARE_CSR(sie, CSR_SIE)
++DECLARE_CSR(sscratch, CSR_SSCRATCH)
++DECLARE_CSR(sepc, CSR_SEPC)
++DECLARE_CSR(sip, CSR_SIP)
++DECLARE_CSR(sptbr, CSR_SPTBR)
++DECLARE_CSR(sasid, CSR_SASID)
++DECLARE_CSR(cyclew, CSR_CYCLEW)
++DECLARE_CSR(timew, CSR_TIMEW)
++DECLARE_CSR(instretw, CSR_INSTRETW)
++DECLARE_CSR(stime, CSR_STIME)
++DECLARE_CSR(scause, CSR_SCAUSE)
++DECLARE_CSR(sbadaddr, CSR_SBADADDR)
++DECLARE_CSR(stimew, CSR_STIMEW)
++DECLARE_CSR(mstatus, CSR_MSTATUS)
++DECLARE_CSR(mtvec, CSR_MTVEC)
++DECLARE_CSR(mtdeleg, CSR_MTDELEG)
++DECLARE_CSR(mie, CSR_MIE)
++DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
++DECLARE_CSR(mscratch, CSR_MSCRATCH)
++DECLARE_CSR(mepc, CSR_MEPC)
++DECLARE_CSR(mcause, CSR_MCAUSE)
++DECLARE_CSR(mbadaddr, CSR_MBADADDR)
++DECLARE_CSR(mip, CSR_MIP)
++DECLARE_CSR(mtime, CSR_MTIME)
++DECLARE_CSR(mcpuid, CSR_MCPUID)
++DECLARE_CSR(mimpid, CSR_MIMPID)
++DECLARE_CSR(mhartid, CSR_MHARTID)
++DECLARE_CSR(mtohost, CSR_MTOHOST)
++DECLARE_CSR(mfromhost, CSR_MFROMHOST)
++DECLARE_CSR(mreset, CSR_MRESET)
++DECLARE_CSR(send_ipi, CSR_SEND_IPI)
++DECLARE_CSR(cycleh, CSR_CYCLEH)
++DECLARE_CSR(timeh, CSR_TIMEH)
++DECLARE_CSR(instreth, CSR_INSTRETH)
++DECLARE_CSR(cyclehw, CSR_CYCLEHW)
++DECLARE_CSR(timehw, CSR_TIMEHW)
++DECLARE_CSR(instrethw, CSR_INSTRETHW)
++DECLARE_CSR(stimeh, CSR_STIMEH)
++DECLARE_CSR(stimehw, CSR_STIMEHW)
++DECLARE_CSR(mtimecmph, CSR_MTIMECMPH)
++DECLARE_CSR(mtimeh, CSR_MTIMEH)
++#endif
++#ifdef DECLARE_CAUSE
++DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
++DECLARE_CAUSE("frm", CAUSE_FRM)
++DECLARE_CAUSE("fcsr", CAUSE_FCSR)
++DECLARE_CAUSE("cycle", CAUSE_CYCLE)
++DECLARE_CAUSE("time", CAUSE_TIME)
++DECLARE_CAUSE("instret", CAUSE_INSTRET)
++DECLARE_CAUSE("stats", CAUSE_STATS)
++DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
++DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
++DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
++DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
++DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
++DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
++DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
++DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
++DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
++DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
++DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
++DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
++DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
++DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
++DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
++DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
++DECLARE_CAUSE("sstatus", CAUSE_SSTATUS)
++DECLARE_CAUSE("stvec", CAUSE_STVEC)
++DECLARE_CAUSE("sie", CAUSE_SIE)
++DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH)
++DECLARE_CAUSE("sepc", CAUSE_SEPC)
++DECLARE_CAUSE("sip", CAUSE_SIP)
++DECLARE_CAUSE("sptbr", CAUSE_SPTBR)
++DECLARE_CAUSE("sasid", CAUSE_SASID)
++DECLARE_CAUSE("cyclew", CAUSE_CYCLEW)
++DECLARE_CAUSE("timew", CAUSE_TIMEW)
++DECLARE_CAUSE("instretw", CAUSE_INSTRETW)
++DECLARE_CAUSE("stime", CAUSE_STIME)
++DECLARE_CAUSE("scause", CAUSE_SCAUSE)
++DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR)
++DECLARE_CAUSE("stimew", CAUSE_STIMEW)
++DECLARE_CAUSE("mstatus", CAUSE_MSTATUS)
++DECLARE_CAUSE("mtvec", CAUSE_MTVEC)
++DECLARE_CAUSE("mtdeleg", CAUSE_MTDELEG)
++DECLARE_CAUSE("mie", CAUSE_MIE)
++DECLARE_CAUSE("mtimecmp", CAUSE_MTIMECMP)
++DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH)
++DECLARE_CAUSE("mepc", CAUSE_MEPC)
++DECLARE_CAUSE("mcause", CAUSE_MCAUSE)
++DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR)
++DECLARE_CAUSE("mip", CAUSE_MIP)
++DECLARE_CAUSE("mtime", CAUSE_MTIME)
++DECLARE_CAUSE("mcpuid", CAUSE_MCPUID)
++DECLARE_CAUSE("mimpid", CAUSE_MIMPID)
++DECLARE_CAUSE("mhartid", CAUSE_MHARTID)
++DECLARE_CAUSE("mtohost", CAUSE_MTOHOST)
++DECLARE_CAUSE("mfromhost", CAUSE_MFROMHOST)
++DECLARE_CAUSE("mreset", CAUSE_MRESET)
++DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
++DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
++DECLARE_CAUSE("timeh", CAUSE_TIMEH)
++DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
++DECLARE_CAUSE("cyclehw", CAUSE_CYCLEHW)
++DECLARE_CAUSE("timehw", CAUSE_TIMEHW)
++DECLARE_CAUSE("instrethw", CAUSE_INSTRETHW)
++DECLARE_CAUSE("stimeh", CAUSE_STIMEH)
++DECLARE_CAUSE("stimehw", CAUSE_STIMEHW)
++DECLARE_CAUSE("mtimecmph", CAUSE_MTIMECMPH)
++DECLARE_CAUSE("mtimeh", CAUSE_MTIMEH)
++#endif
+diff -urN empty/gcc/config/riscv/riscv-protos.h gcc-5.2.0/gcc/config/riscv/riscv-protos.h
+--- empty/gcc/config/riscv/riscv-protos.h	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/riscv-protos.h	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,96 @@
++/* Definition of RISC-V target for GNU compiler.
++   Copyright (C) 2011-2014 Free Software Foundation, Inc.
++   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
++   Based on MIPS target for GNU compiler.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++#ifndef GCC_RISCV_PROTOS_H
++#define GCC_RISCV_PROTOS_H
++
++enum riscv_symbol_type {
++  SYMBOL_ABSOLUTE,
++  SYMBOL_GOT_DISP,
++  SYMBOL_TLS,
++  SYMBOL_TLS_LE,
++  SYMBOL_TLS_IE,
++  SYMBOL_TLS_GD
++};
++#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
++
++enum riscv_code_model {
++  CM_MEDLOW,
++  CM_MEDANY,
++  CM_PIC
++};
++extern enum riscv_code_model riscv_cmodel;
++
++extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
++extern int riscv_regno_mode_ok_for_base_p (int, enum machine_mode, bool);
++extern int riscv_address_insns (rtx, enum machine_mode, bool);
++extern int riscv_const_insns (rtx);
++extern int riscv_split_const_insns (rtx);
++extern int riscv_load_store_insns (rtx, rtx_insn *);
++extern rtx riscv_emit_move (rtx, rtx);
++extern bool riscv_split_symbol (rtx, rtx, enum machine_mode, rtx *);
++extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
++extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
++extern bool riscv_legitimize_move (enum machine_mode, rtx, rtx);
++extern bool riscv_legitimize_vector_move (enum machine_mode, rtx, rtx);
++
++extern rtx riscv_subword (rtx, bool);
++extern bool riscv_split_64bit_move_p (rtx, rtx);
++extern void riscv_split_doubleword_move (rtx, rtx);
++extern const char *riscv_output_move (rtx, rtx);
++extern const char *riscv_output_gpr_save (unsigned);
++#ifdef RTX_CODE
++extern void riscv_expand_scc (rtx *);
++extern void riscv_expand_conditional_branch (rtx *);
++#endif
++extern rtx riscv_expand_call (bool, rtx, rtx, rtx);
++extern void riscv_expand_fcc_reload (rtx, rtx, rtx);
++extern void riscv_set_return_address (rtx, rtx);
++extern bool riscv_expand_block_move (rtx, rtx, rtx);
++extern void riscv_expand_synci_loop (rtx, rtx);
++
++extern bool riscv_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT,
++					       HOST_WIDE_INT);
++extern bool riscv_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT,
++						HOST_WIDE_INT);
++extern void riscv_order_regs_for_local_alloc (void);
++
++extern rtx riscv_return_addr (int, rtx);
++extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
++extern void riscv_expand_prologue (void);
++extern void riscv_expand_epilogue (bool);
++extern bool riscv_can_use_return_insn (void);
++extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
++
++extern enum reg_class riscv_secondary_reload_class (enum reg_class,
++						   enum machine_mode,
++						   rtx, bool);
++extern int riscv_class_max_nregs (enum reg_class, enum machine_mode);
++
++extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode);
++
++extern void irix_asm_output_align (FILE *, unsigned);
++extern const char *current_section_name (void);
++extern unsigned int current_section_flags (void);
++
++extern void riscv_expand_vector_init (rtx, rtx);
++
++#endif /* ! GCC_RISCV_PROTOS_H */
+diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
+--- empty/gcc/config/riscv/riscv.c	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/riscv.c	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,4439 @@
 +/* Subroutines used for code generation for RISC-V.
 +   Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -994,29 +2830,76 @@
 +#include "insn-attr.h"
 +#include "recog.h"
 +#include "output.h"
++#include "hash-set.h"
++#include "machmode.h"
++#include "vec.h"
++#include "double-int.h"
++#include "input.h"
++#include "alias.h"
++#include "symtab.h"
++#include "wide-int.h"
++#include "inchash.h"
 +#include "tree.h"
++#include "fold-const.h"
 +#include "varasm.h"
++#include "stringpool.h"
 +#include "stor-layout.h"
 +#include "calls.h"
 +#include "function.h"
++#include "hashtab.h"
++#include "flags.h"
++#include "statistics.h"
++#include "real.h"
++#include "fixed-value.h"
++#include "expmed.h"
++#include "dojump.h"
++#include "explow.h"
++#include "emit-rtl.h"
++#include "stmt.h"
 +#include "expr.h"
++#include "insn-codes.h"
 +#include "optabs.h"
 +#include "libfuncs.h"
-+#include "flags.h"
 +#include "reload.h"
 +#include "tm_p.h"
 +#include "ggc.h"
 +#include "gstab.h"
-+#include "hashtab.h"
++#include "hash-table.h"
 +#include "debug.h"
 +#include "target.h"
 +#include "target-def.h"
++#include "common/common-target.h"
 +#include "langhooks.h"
++#include "dominance.h"
++#include "cfg.h"
++#include "cfgrtl.h"
++#include "cfganal.h"
++#include "lcm.h"
++#include "cfgbuild.h"
++#include "cfgcleanup.h"
++#include "predict.h"
++#include "basic-block.h"
 +#include "sched-int.h"
++#include "tree-ssa-alias.h"
++#include "internal-fn.h"
++#include "gimple-fold.h"
++#include "tree-eh.h"
++#include "gimple-expr.h"
++#include "is-a.h"
++#include "gimple.h"
++#include "gimplify.h"
 +#include "bitmap.h"
 +#include "diagnostic.h"
 +#include "target-globals.h"
-+#include "symcat.h"
++#include "opts.h"
++#include "tree-pass.h"
++#include "context.h"
++#include "hash-map.h"
++#include "plugin-api.h"
++#include "ipa-ref.h"
++#include "cgraph.h"
++#include "builtins.h"
++#include "rtl-iter.h"
 +#include <stdint.h>
 +
 +/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF.  */
@@ -1071,6 +2954,8 @@
 +  ADDRESS_SYMBOLIC
 +};
 +
++enum riscv_code_model riscv_cmodel = TARGET_DEFAULT_CMODEL;
++
 +/* Macros to create an enumeration identifier for a function prototype.  */
 +#define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
 +#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
@@ -1108,6 +2993,9 @@
 +  /* Likewise FPR X.  */
 +  unsigned int fmask;
 +
++  /* How much the GPR save/restore routines adjust sp (or 0 if unused).  */
++  unsigned save_libcall_adjustment;
++
 +  /* Offsets of fixed-point and floating-point save areas from frame bottom */
 +  HOST_WIDE_INT gp_sp_offset;
 +  HOST_WIDE_INT fp_sp_offset;
@@ -1127,6 +3015,9 @@
 +     This area is allocated by the callee at the very top of the frame.  */
 +  int varargs_size;
 +
++  /* Cached return value of leaf_function_p.  <0 if false, >0 if true.  */
++  int is_leaf;
++
 +  /* The current frame information, calculated by riscv_compute_frame_info.  */
 +  struct riscv_frame_info frame;
 +};
@@ -1543,15 +3434,6 @@
 +  }
 +}
 +
-+/* A for_each_rtx callback.  Stop the search if *X references a
-+   thread-local symbol.  */
-+
-+static int
-+riscv_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
-+{
-+  return riscv_tls_symbol_p (*x);
-+}
-+
 +/* Implement TARGET_LEGITIMATE_CONSTANT_P.  */
 +
 +static bool
@@ -1563,7 +3445,7 @@
 +/* Implement TARGET_CANNOT_FORCE_CONST_MEM.  */
 +
 +static bool
-+riscv_cannot_force_const_mem (enum machine_mode mode, rtx x)
++riscv_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
 +{
 +  enum riscv_symbol_type type;
 +  rtx base, offset;
@@ -1573,32 +3455,21 @@
 +  if (GET_CODE (x) == HIGH)
 +    return true;
 +
-+  /* As an optimization, reject constants that riscv_legitimize_move
-+     can expand inline.
-+
-+     Suppose we have a multi-instruction sequence that loads constant C
-+     into register R.  If R does not get allocated a hard register, and
-+     R is used in an operand that allows both registers and memory
-+     references, reload will consider forcing C into memory and using
-+     one of the instruction's memory alternatives.  Returning false
-+     here will force it to use an input reload instead.  */
-+  if (CONST_INT_P (x) && riscv_legitimate_constant_p (mode, x))
-+    return true;
-+
 +  split_const (x, &base, &offset);
 +  if (riscv_symbolic_constant_p (base, &type))
 +    {
-+      /* The same optimization as for CONST_INT.  */
++      /* As an optimization, don't spill symbolic constants that are as
++	 cheap to rematerialize as to access in the constant pool.  */
 +      if (SMALL_INT (offset) && riscv_symbol_insns (type) > 0)
 +	return true;
 +
-+      /* It's not worth creating additional dynamic relocations.  */
++      /* As an optimization, avoid needlessly generate dynamic relocations.  */
 +      if (flag_pic)
 +	return true;
 +    }
 +
 +  /* TLS symbols must be computed by riscv_legitimize_move.  */
-+  if (for_each_rtx (&x, &riscv_tls_symbol_ref_1, NULL))
++  if (tls_referenced_p (x))
 +    return true;
 +
 +  return false;
@@ -1860,7 +3731,7 @@
 +   given that it loads from or stores to MEM. */
 +
 +int
-+riscv_load_store_insns (rtx mem, rtx insn)
++riscv_load_store_insns (rtx mem, rtx_insn *insn)
 +{
 +  enum machine_mode mode;
 +  bool might_split_p;
@@ -2690,7 +4561,7 @@
 +      if (dest_code == REG)
 +	{
 +	  if (GP_REG_P (REGNO (dest)))
-+	    return "move\t%0,%z1";
++	    return "mv\t%0,%z1";
 +
 +	  if (FP_REG_P (REGNO (dest)))
 +	    {
@@ -3732,7 +5603,7 @@
 +  memset (riscv_hi_relocs, '\0', sizeof (riscv_hi_relocs));
 +  memset (riscv_lo_relocs, '\0', sizeof (riscv_lo_relocs));
 +
-+  if (!flag_pic)
++  if (!flag_pic && riscv_cmodel == CM_MEDLOW)
 +    {
 +      riscv_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
 +      riscv_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
@@ -3899,7 +5770,7 @@
 +
 +  if (TREE_CODE (x) == VAR_DECL && DECL_SECTION_NAME (x))
 +    {
-+      const char *sec = TREE_STRING_POINTER (DECL_SECTION_NAME (x));
++      const char *sec = DECL_SECTION_NAME (x);
 +      return strcmp (sec, ".sdata") == 0 || strcmp (sec, ".sbss") == 0;
 +    }
 +
@@ -3997,6 +5868,27 @@
 +	 || (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return);
 +}
 +
++/* Determine whether to call GPR save/restore routines.  */
++static bool
++riscv_use_save_libcall (const struct riscv_frame_info *frame)
++{
++  if (!TARGET_SAVE_RESTORE || crtl->calls_eh_return || frame_pointer_needed)
++    return false;
++
++  return frame->save_libcall_adjustment != 0;
++}
++
++/* Determine which GPR save/restore routine to call.  */
++
++static unsigned
++riscv_save_libcall_count (unsigned mask)
++{
++  for (unsigned n = GP_REG_LAST; n > GP_REG_FIRST; n--)
++    if (BITSET_P (mask, n))
++      return CALLEE_SAVED_REG_NUMBER (n) + 1;
++  abort ();
++}
++
 +/* Populate the current function's riscv_frame_info structure.
 +
 +   RISC-V stack frames grown downward.  High addresses are at the top.
@@ -4044,7 +5936,7 @@
 +{
 +  struct riscv_frame_info *frame;
 +  HOST_WIDE_INT offset;
-+  unsigned int regno, i;
++  unsigned int regno, i, num_x_saved = 0, num_f_saved = 0;
 +
 +  frame = &cfun->machine->frame;
 +  memset (frame, 0, sizeof (*frame));
@@ -4052,20 +5944,20 @@
 +  /* Find out which GPRs we need to save.  */
 +  for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
 +    if (riscv_save_reg_p (regno))
-+      frame->mask |= 1 << (regno - GP_REG_FIRST);
++      frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
 +
 +  /* If this function calls eh_return, we must also save and restore the
 +     EH data registers.  */
 +  if (crtl->calls_eh_return)
-+    for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
-+      frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
++    for (i = 0; (regno = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++)
++      frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
 +
 +  /* Find out which FPRs we need to save.  This loop must iterate over
 +     the same space as its companion in riscv_for_each_saved_gpr_and_fpr.  */
 +  if (TARGET_HARD_FLOAT)
 +    for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
 +      if (riscv_save_reg_p (regno))
-+        frame->fmask |= 1 << (regno - FP_REG_FIRST);
++        frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++;
 +
 +  /* At the bottom of the frame are any outgoing stack arguments. */
 +  offset = crtl->outgoing_args_size;
@@ -4076,15 +5968,20 @@
 +  /* Next are the callee-saved FPRs. */
 +  if (frame->fmask)
 +    {
-+      unsigned num_saved = __builtin_popcount(frame->fmask);
-+      offset += RISCV_STACK_ALIGN (num_saved * UNITS_PER_FPREG);
++      offset += RISCV_STACK_ALIGN (num_f_saved * UNITS_PER_FPREG);
 +      frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
 +    }
 +  /* Next are the callee-saved GPRs. */
 +  if (frame->mask)
 +    {
-+      unsigned num_saved = __builtin_popcount(frame->mask);
-+      offset += RISCV_STACK_ALIGN (num_saved * UNITS_PER_WORD);
++      unsigned x_save_size = RISCV_STACK_ALIGN (num_x_saved * UNITS_PER_WORD);
++      unsigned num_save_restore = 1 + riscv_save_libcall_count (frame->mask);
++
++      /* Only use save/restore routines if they don't alter the stack size.  */
++      if (RISCV_STACK_ALIGN (num_save_restore * UNITS_PER_WORD) == x_save_size)
++	frame->save_libcall_adjustment = x_save_size;
++
++      offset += x_save_size;
 +      frame->gp_sp_offset = offset - UNITS_PER_WORD;
 +    }
 +  /* The hard frame pointer points above the callee-saved GPRs. */
@@ -4096,6 +5993,10 @@
 +  offset += crtl->args.pretend_args_size;
 +  frame->total_size = offset;
 +  /* Next points the incoming stack pointer and any incoming arguments. */
++
++  /* Only use save/restore routines when the GPRs are atop the frame.  */
++  if (frame->hard_frame_pointer_offset != frame->total_size)
++    frame->save_libcall_adjustment = 0;
 +}
 +
 +/* Make sure that we're not trying to eliminate to the wrong hard frame
@@ -4256,22 +6157,55 @@
 +  riscv_emit_save_slot_move (mem, reg, RISCV_PROLOGUE_TEMP (GET_MODE (reg)));
 +}
 +
++/* Return the code to invoke the GPR save routine.  */
++
++const char *
++riscv_output_gpr_save (unsigned mask)
++{
++  static char buf[GP_REG_NUM * 32];
++  size_t len = 0;
++  unsigned n = riscv_save_libcall_count (mask), i;
++  unsigned frame_size = RISCV_STACK_ALIGN ((n + 1) * UNITS_PER_WORD);
++
++  len += sprintf (buf + len, "call\tt0,__riscv_save_%u", n);
++
++#ifdef DWARF2_UNWIND_INFO
++  /* Describe the effect of the call to __riscv_save_X.  */
++  if (dwarf2out_do_cfi_asm ())
++    {
++      len += sprintf (buf + len, "\n\t.cfi_def_cfa_offset %u", frame_size);
++
++      for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
++	if (BITSET_P (cfun->machine->frame.mask, i))
++	  len += sprintf (buf + len, "\n\t.cfi_offset %u,%d", i,
++			  (CALLEE_SAVED_REG_NUMBER (i) + 2) * -UNITS_PER_WORD);
++    }
++#endif
++
++  return buf;
++}
 +
 +/* Expand the "prologue" pattern.  */
 +
 +void
 +riscv_expand_prologue (void)
 +{
-+  const struct riscv_frame_info *frame;
-+  HOST_WIDE_INT size;
++  struct riscv_frame_info *frame = &cfun->machine->frame;
++  HOST_WIDE_INT size = frame->total_size;
++  unsigned mask = frame->mask;
 +  rtx insn;
 +
-+  frame = &cfun->machine->frame;
-+  size = frame->total_size;
-+
 +  if (flag_stack_usage_info)
 +    current_function_static_stack_size = size;
 +
++  /* When optimizing for size, call a subroutine to save the registers.  */
++  if (riscv_use_save_libcall (frame))
++    {
++      frame->mask = 0; /* Temporarily fib that we need not save GPRs.  */
++      size -= frame->save_libcall_adjustment;
++      emit_insn (gen_gpr_save (GEN_INT (mask)));
++    }
++
 +  /* Save the registers.  Allocate up to RISCV_MAX_FIRST_STACK_STEP
 +     bytes beforehand; this is enough to cover the register save area
 +     without going out of range.  */
@@ -4288,6 +6222,8 @@
 +      riscv_for_each_saved_gpr_and_fpr (size, riscv_save_reg);
 +    }
 +
++  frame->mask = mask; /* Undo the above fib.  */
++
 +  /* Set up the frame pointer, if we're using one.  */
 +  if (frame_pointer_needed)
 +    {
@@ -4300,22 +6236,24 @@
 +  if (size > 0)
 +    {
 +      if (SMALL_OPERAND (-size))
-+	RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
-+						       stack_pointer_rtx,
-+						       GEN_INT (-size)))) = 1;
++	emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
++				  GEN_INT (-size)));
 +      else
 +	{
-+	  riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (size));
-+	  emit_insn (gen_sub3_insn (stack_pointer_rtx,
++	  riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-size));
++	  emit_insn (gen_add3_insn (stack_pointer_rtx,
 +				    stack_pointer_rtx,
 +				    RISCV_PROLOGUE_TEMP (Pmode)));
-+
-+	  /* Describe the combined effect of the previous instructions.  */
-+	  riscv_set_frame_expr
-+	    (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
-+			  plus_constant (Pmode, stack_pointer_rtx, -size)));
 +	}
 +    }
++
++  if (frame->total_size > 0)
++    {
++      /* Describe the effect of the instructions that adjusted sp.  */
++      insn = plus_constant (Pmode, stack_pointer_rtx, -frame->total_size);
++      insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx, insn);
++      riscv_set_frame_expr (insn);
++    }
 +}
 +
 +/* Emit instructions to restore register REG from slot MEM.  */
@@ -4332,8 +6270,17 @@
 +void
 +riscv_expand_epilogue (bool sibcall_p)
 +{
-+  const struct riscv_frame_info *frame;
-+  HOST_WIDE_INT step1, step2;
++  /* Split the frame into two.  STEP1 is the amount of stack we should
++     deallocate before restoring the registers.  STEP2 is the amount we
++     should deallocate afterwards.
++
++     Start off by assuming that no registers need to be restored.  */
++  struct riscv_frame_info *frame = &cfun->machine->frame;
++  unsigned mask = frame->mask;
++  HOST_WIDE_INT step1 = frame->total_size;
++  HOST_WIDE_INT step2 = 0;
++  bool use_restore_libcall = !sibcall_p && riscv_use_save_libcall (frame);
++  rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
 +
 +  if (!sibcall_p && riscv_can_use_return_insn ())
 +    {
@@ -4341,16 +6288,7 @@
 +      return;
 +    }
 +
-+  /* Split the frame into two.  STEP1 is the amount of stack we should
-+     deallocate before restoring the registers.  STEP2 is the amount we
-+     should deallocate afterwards.
-+
-+     Start off by assuming that no registers need to be restored.  */
-+  frame = &cfun->machine->frame;
-+  step1 = frame->total_size;
-+  step2 = 0;
-+
-+  /* Move past any dynamic stack allocations. */
++  /* Move past any dynamic stack allocations.  */
 +  if (cfun->calls_alloca)
 +    {
 +      rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset);
@@ -4385,25 +6323,39 @@
 +      emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
 +    }
 +
++  if (use_restore_libcall)
++    frame->mask = 0; /* Temporarily fib that we need not save GPRs.  */
++
 +  /* Restore the registers.  */
 +  riscv_for_each_saved_gpr_and_fpr (frame->total_size - step2,
 +				    riscv_restore_reg);
 +
++  if (use_restore_libcall)
++    {
++      frame->mask = mask; /* Undo the above fib.  */
++      gcc_assert (step2 >= frame->save_libcall_adjustment);
++      step2 -= frame->save_libcall_adjustment;
++    }
++
 +  /* Deallocate the final bit of the frame.  */
 +  if (step2 > 0)
 +    emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
 +			      GEN_INT (step2)));
 +
++  if (use_restore_libcall)
++    {
++      emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask))));
++      emit_jump_insn (gen_gpr_restore_return (ra));
++      return;
++    }
++
 +  /* Add in the __builtin_eh_return stack adjustment. */
 +  if (crtl->calls_eh_return)
 +    emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
 +			      EH_RETURN_STACKADJ_RTX));
 +
 +  if (!sibcall_p)
-+    {
-+      rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
-+      emit_jump_insn (gen_simple_return_internal (ra));
-+    }
++    emit_jump_insn (gen_simple_return_internal (ra));
 +}
 +
 +/* Return nonzero if this function is known to have a null epilogue.
@@ -4606,8 +6558,8 @@
 +   dependencies have no cost. */
 +
 +static int
-+riscv_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
-+		  rtx dep ATTRIBUTE_UNUSED, int cost)
++riscv_adjust_cost (rtx_insn *insn ATTRIBUTE_UNUSED, rtx link,
++		   rtx_insn *dep ATTRIBUTE_UNUSED, int cost)
 +{
 +  if (REG_NOTE_KIND (link) != 0)
 +    return 0;
@@ -4911,7 +6863,8 @@
 +		      HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
 +		      tree function)
 +{
-+  rtx this_rtx, temp1, temp2, insn, fnaddr;
++  rtx this_rtx, temp1, temp2, fnaddr;
++  rtx_insn *insn;
 +  bool use_sibcall_p;
 +
 +  /* Pretend to be a post-reload pass while generating rtl.  */
@@ -4994,7 +6947,7 @@
 +static struct machine_function *
 +riscv_init_machine_status (void)
 +{
-+  return ggc_alloc_cleared_machine_function ();
++  return ggc_cleared_alloc<machine_function> ();
 +}
 +
 +/* Implement TARGET_OPTION_OVERRIDE.  */
@@ -5038,6 +6991,19 @@
 +  /* Function to allocate machine-dependent function status.  */
 +  init_machine_status = &riscv_init_machine_status;
 +
++  if (riscv_cmodel_string)
++    {
++      if (strcmp (riscv_cmodel_string, "medlow") == 0)
++	riscv_cmodel = CM_MEDLOW;
++      else if (strcmp (riscv_cmodel_string, "medany") == 0)
++	riscv_cmodel = CM_MEDANY;
++      else
++	error ("unsupported code model: %s", riscv_cmodel_string);
++    }
++
++  if (flag_pic)
++    riscv_cmodel = CM_PIC;
++
 +  riscv_init_relocs ();
 +}
 +
@@ -5114,6 +7080,23 @@
 +  emit_insn (gen_clear_cache (addr, end_addr));
 +}
 +
++/* Implement TARGET_FUNCTION_OK_FOR_SIBCALL.  */
++
++static bool
++riscv_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
++{
++  if (TARGET_SAVE_RESTORE)
++    {
++      /* When optimzing for size, don't use sibcalls in non-leaf routines */
++      if (cfun->machine->is_leaf == 0)
++	cfun->machine->is_leaf = leaf_function_p () ? 1 : -1;
++
++      return cfun->machine->is_leaf > 0;
++    }
++
++  return true;
++}
++
 +static bool
 +riscv_lra_p (void)
 +{
@@ -5140,7 +7123,7 @@
 +#define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
 +
 +#undef TARGET_FUNCTION_OK_FOR_SIBCALL
-+#define TARGET_FUNCTION_OK_FOR_SIBCALL hook_bool_tree_tree_true
++#define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
 +
 +#undef TARGET_REGISTER_MOVE_COST
 +#define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
@@ -5253,53 +7236,10 @@
 +struct gcc_target targetm = TARGET_INITIALIZER;
 +
 +#include "gt-riscv.h"
-diff -urN original-gcc/gcc/config/riscv/riscv-ftypes.def gcc/gcc/config/riscv/riscv-ftypes.def
---- original-gcc/gcc/config/riscv/riscv-ftypes.def	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/riscv-ftypes.def	2015-03-07 09:51:45.663139025 +0100
-@@ -0,0 +1,39 @@
-+/* Definitions of prototypes for RISC-V built-in functions.
-+   Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+   Based on MIPS target for GNU compiler.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3.  If not see
-+<http://www.gnu.org/licenses/>.  */
-+
-+/* Invoke DEF_RISCV_FTYPE (NARGS, LIST) for each prototype used by
-+   MIPS built-in functions, where:
-+
-+      NARGS is the number of arguments.
-+      LIST contains the return-type code followed by the codes for each
-+        argument type.
-+
-+   Argument- and return-type codes are either modes or one of the following:
-+
-+      VOID for void_type_node
-+      INT for integer_type_node
-+      POINTER for ptr_type_node
-+
-+   (we don't use PTR because that's a ANSI-compatibillity macro).
-+
-+   Please keep this list lexicographically sorted by the LIST argument.  */
-+
-+DEF_RISCV_FTYPE (1, (VOID, VOID))
-diff -urN original-gcc/gcc/config/riscv/riscv.h gcc/gcc/config/riscv/riscv.h
---- original-gcc/gcc/config/riscv/riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/riscv.h	2015-03-07 09:51:45.667139025 +0100
-@@ -0,0 +1,1127 @@
+diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
+--- empty/gcc/config/riscv/riscv.h	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/riscv.h	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,1109 @@
 +/* Definition of RISC-V target for GNU compiler.
 +   Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -5400,13 +7340,15 @@
 +	  builtin_define_std ("LANGUAGE_C");				\
 +	  builtin_define ("_LANGUAGE_C");				\
 +	}								\
++      if (riscv_cmodel == CM_MEDANY)					\
++	builtin_define ("_RISCV_CMODEL_MEDANY");			\
 +    }									\
 +  while (0)
 +
 +/* Default target_flags if no switches are specified  */
 +
 +#ifndef TARGET_DEFAULT
-+#define TARGET_DEFAULT (TARGET_ATOMIC | 
++#define TARGET_DEFAULT 0
 +#endif
 +
 +#ifndef RISCV_ARCH_STRING_DEFAULT
@@ -5442,6 +7384,7 @@
 +   --with-tune is ignored if -mtune is specified.
 +   --with-float is ignored if -mhard-float or -msoft-float are specified. */
 +#define OPTION_DEFAULT_SPECS \
++  {"arch", "%{!march=*:-march=%(VALUE)}"},			   \
 +  {"arch_32", "%{" OPT_ARCH32 ":%{m32}}" }, \
 +  {"arch_64", "%{" OPT_ARCH64 ":%{m64}}" }, \
 +  {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
@@ -5468,6 +7411,7 @@
 +#define ASM_SPEC "\
 +%(subtarget_asm_debugging_spec) \
 +%{m32} %{m64} %{!m32:%{!m64: %(asm_abi_default_spec)}} \
++%{mrvc} \
 +%{fPIC|fpic|fPIE|fpie:-fpic} \
 +%{march=*} \
 +%(subtarget_asm_spec)"
@@ -5500,6 +7444,8 @@
 +#define SUBTARGET_EXTRA_SPECS
 +#endif
 +
++#define TARGET_DEFAULT_CMODEL CM_MEDLOW
++
 +/* By default, turn on GDB extensions.  */
 +#define DEFAULT_GDB_EXTENSIONS 1
 +
@@ -5583,7 +7529,7 @@
 +#define PARM_BOUNDARY BITS_PER_WORD
 +
 +/* Allocation boundary (in *bits*) for the code of a function.  */
-+#define FUNCTION_BOUNDARY 32
++#define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
 +
 +/* There is no point aligning anything to a rounder boundary than this.  */
 +#define BIGGEST_ALIGNMENT 128
@@ -6023,6 +7969,10 @@
 +#define FP_ARG_FIRST (FP_REG_FIRST + 10)
 +#define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 +
++#define CALLEE_SAVED_REG_NUMBER(REGNO)			\
++  ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :		\
++   (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
++
 +#define LIBCALL_VALUE(MODE) \
 +  riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 +
@@ -6139,6 +8089,7 @@
 +
 +#define JUMP_TABLES_IN_TEXT_SECTION 0
 +#define CASE_VECTOR_MODE SImode
++#define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 +
 +/* Define this as 1 if `char' should by default be signed; else as 0.  */
 +#define DEFAULT_SIGNED_CHAR 0
@@ -6372,24 +8323,6 @@
 +   ? RISCV_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX		\
 +   : RISCV_CALL_RATIO / 2)
 +
-+/* movmemsi is meant to generate code that is at least as good as
-+   move_by_pieces.  However, movmemsi effectively uses a by-pieces
-+   implementation both for moves smaller than a word and for word-aligned
-+   moves of no more than RISCV_MAX_MOVE_BYTES_STRAIGHT bytes.  We should
-+   allow the tree-level optimisers to do such moves by pieces, as it
-+   often exposes other optimization opportunities.  We might as well
-+   continue to use movmemsi at the rtl level though, as it produces
-+   better code when scheduling is disabled (such as at -O).  */
-+
-+#define MOVE_BY_PIECES_P(SIZE, ALIGN)				\
-+  (HAVE_movmemsi						\
-+   ? (!currently_expanding_to_rtl				\
-+      && ((ALIGN) < BITS_PER_WORD				\
-+	  ? (SIZE) < UNITS_PER_WORD				\
-+	  : (SIZE) <= RISCV_MAX_MOVE_BYTES_STRAIGHT))		\
-+   : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1)	\
-+      < (unsigned int) MOVE_RATIO (false)))
-+
 +/* For CLEAR_RATIO, when optimizing for size, give a better estimate
 +   of the length of a memset call, but use the default otherwise.  */
 +
@@ -6403,17 +8336,6 @@
 +#define SET_RATIO(speed) \
 +  ((speed) ? 15 : RISCV_CALL_RATIO - 2)
 +
-+/* STORE_BY_PIECES_P can be used when copying a constant string, but
-+   in that case each word takes 3 insns (lui, ori, sw), or more in
-+   64-bit mode, instead of 2 (lw, sw).  For now we always fail this
-+   and let the move_by_pieces code copy the string from read-only
-+   memory.  In the future, this could be tuned further for multi-issue
-+   CPUs that can issue stores down one pipe and arithmetic instructions
-+   down another; in that case, the lui/ori/sw combination would be a
-+   win for long enough strings.  */
-+
-+#define STORE_BY_PIECES_P(SIZE, ALIGN) 0
-+
 +#ifndef HAVE_AS_TLS
 +#define HAVE_AS_TLS 0
 +#endif
@@ -6427,10 +8349,10 @@
 +
 +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 +  (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
-diff -urN original-gcc/gcc/config/riscv/riscv.md gcc/gcc/config/riscv/riscv.md
---- original-gcc/gcc/config/riscv/riscv.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/riscv.md	2015-03-07 09:51:45.667139025 +0100
-@@ -0,0 +1,2423 @@
+diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
+--- empty/gcc/config/riscv/riscv.md	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/riscv.md	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,2448 @@
 +;; Machine description for RISC-V for GNU compiler.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -6469,6 +8391,10 @@
 +  UNSPEC_TLS_IE
 +  UNSPEC_TLS_GD
 +
++  ;; Register save and restore.
++  UNSPEC_GPR_SAVE
++  UNSPEC_GPR_RESTORE
++
 +  ;; Blockage and synchronisation.
 +  UNSPEC_BLOCKAGE
 +  UNSPEC_FENCE
@@ -6477,6 +8403,8 @@
 +
 +(define_constants
 +  [(RETURN_ADDR_REGNUM		1)
++   (T0_REGNUM			5)
++   (T1_REGNUM			6)
 +])
 +
 +(include "predicates.md")
@@ -7960,9 +9888,6 @@
 +    DONE;
 +})
 +
-+;; The difference between these two is whether or not ints are allowed
-+;; in FP registers (off by default, use -mdebugh to enable).
-+
 +(define_insn "*mov<mode>_internal"
 +  [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,*r,*m")
 +	(match_operand:IMOVE32 1 "move_operand" "r,T,m,rJ,*r*J,*m,*f,*f"))]
@@ -8338,7 +10263,11 @@
 +	 (label_ref (match_operand 0 "" ""))
 +	 (pc)))]
 +  ""
-+  "b%C1\t%2,%z3,%0"
++{
++  if (GET_CODE (operands[3]) == CONST_INT)
++    return "b%C1z\t%2,%0";
++  return "b%C1\t%2,%3,%0";
++}
 +  [(set_attr "type" "branch")
 +   (set_attr "mode" "none")])
 +
@@ -8381,7 +10310,7 @@
 +	 (match_operator 0 "equality_operator"
 +	  [(zero_extract:GPR (match_operand:GPR 2 "register_operand" "r")
 +		 (const_int 1)
-+		 (match_operand 3 "const_int_operand"))
++		 (match_operand 3 "branch_on_bit_operand"))
 +		 (const_int 0)])
 +	 (label_ref (match_operand 1))
 +	 (pc)))
@@ -8411,7 +10340,7 @@
 +	(if_then_else
 +	 (match_operator 0 "equality_operator"
 +	  [(zero_extract:GPR (match_operand:GPR 2 "register_operand" "r")
-+		 (match_operand 3 "const_int_operand")
++		 (match_operand 3 "branch_on_bit_operand")
 +		 (const_int 0))
 +		 (const_int 0)])
 +	 (label_ref (match_operand 1))
@@ -8559,12 +10488,12 @@
 +	      (use (label_ref (match_operand 1 "" "")))]
 +  ""
 +{
-+  if (flag_pic)
++  if (CASE_VECTOR_PC_RELATIVE)
 +      operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
 +					 gen_rtx_LABEL_REF (Pmode, operands[1]),
 +					 NULL_RTX, 0, OPTAB_DIRECT);
 +
-+  if (flag_pic && Pmode == DImode)
++  if (CASE_VECTOR_PC_RELATIVE && Pmode == DImode)
 +    emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
 +  else
 +    emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
@@ -8750,8 +10679,7 @@
 +              (match_operand 2 "" "")))
 +   (set (match_operand 3 "register_operand" "")
 +	(call (mem:SI (match_dup 1))
-+	      (match_dup 2)))
-+   (clobber (match_scratch:SI 4 "=j,j"))]
++	      (match_dup 2)))]
 +  "SIBLING_CALL_P (insn)"
 +  { return REG_P (operands[1]) ? "jr\t%1"
 +	   : absolute_symbolic_operand (operands[1], VOIDmode) ? "tail\t%1"
@@ -8852,1262 +10780,31 @@
 +  ""
 +  "sbreak")
 +
++(define_insn "gpr_save"
++  [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPEC_GPR_SAVE)
++   (clobber (reg:SI T0_REGNUM))
++   (clobber (reg:SI T1_REGNUM))]
++  ""
++  { return riscv_output_gpr_save (INTVAL (operands[0])); })
++
++(define_insn "gpr_restore"
++  [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPEC_GPR_RESTORE)]
++  ""
++  "tail\t__riscv_restore_%0")
++
++(define_insn "gpr_restore_return"
++  [(return)
++   (use (match_operand 0 "pmode_register_operand" ""))
++   (const_int 0)]
++  ""
++  "")
++
 +(include "sync.md")
 +(include "peephole.md")
-diff -urN original-gcc/gcc/config/riscv/riscv-modes.def gcc/gcc/config/riscv/riscv-modes.def
---- original-gcc/gcc/config/riscv/riscv-modes.def	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/riscv-modes.def	2015-03-07 09:51:45.663139025 +0100
-@@ -0,0 +1,26 @@
-+/* Extra machine modes for RISC-V target.
-+   Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+   Based on MIPS target for GNU compiler.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3.  If not see
-+<http://www.gnu.org/licenses/>.  */
-+
-+FLOAT_MODE (TF, 16, ieee_quad_format);
-+
-+/* Vector modes.  */
-+VECTOR_MODES (INT, 4);        /*       V8QI V4HI V2SI */
-+VECTOR_MODES (FLOAT, 4);      /*            V4HF V2SF */
-diff -urN original-gcc/gcc/config/riscv/riscv-opc.h gcc/gcc/config/riscv/riscv-opc.h
---- original-gcc/gcc/config/riscv/riscv-opc.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/riscv-opc.h	2015-03-07 09:51:45.663139025 +0100
-@@ -0,0 +1,1216 @@
-+/* Automatically generated by parse-opcodes */
-+#ifndef RISCV_ENCODING_H
-+#define RISCV_ENCODING_H
-+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
-+#define MATCH_VLSEGSTWU 0xc00305b
-+#define MASK_VLSEGSTWU  0x1e00707f
-+#define MATCH_C_LW0 0x12
-+#define MASK_C_LW0  0x801f
-+#define MATCH_FMV_D_X 0xf2000053
-+#define MASK_FMV_D_X  0xfff0707f
-+#define MATCH_VLH 0x200205b
-+#define MASK_VLH  0xfff0707f
-+#define MATCH_C_LI 0x0
-+#define MASK_C_LI  0x1f
-+#define MATCH_FADD_D 0x2000053
-+#define MASK_FADD_D  0xfe00007f
-+#define MATCH_C_LD 0x9
-+#define MASK_C_LD  0x1f
-+#define MATCH_VLD 0x600205b
-+#define MASK_VLD  0xfff0707f
-+#define MATCH_FADD_S 0x53
-+#define MASK_FADD_S  0xfe00007f
-+#define MATCH_C_LW 0xa
-+#define MASK_C_LW  0x1f
-+#define MATCH_VLW 0x400205b
-+#define MASK_VLW  0xfff0707f
-+#define MATCH_VSSEGSTW 0x400307b
-+#define MASK_VSSEGSTW  0x1e00707f
-+#define MATCH_UTIDX 0x6077
-+#define MASK_UTIDX  0xfffff07f
-+#define MATCH_C_FLW 0x14
-+#define MASK_C_FLW  0x1f
-+#define MATCH_FSUB_D 0xa000053
-+#define MASK_FSUB_D  0xfe00007f
-+#define MATCH_VSSEGSTD 0x600307b
-+#define MASK_VSSEGSTD  0x1e00707f
-+#define MATCH_VSSEGSTB 0x307b
-+#define MASK_VSSEGSTB  0x1e00707f
-+#define MATCH_DIV 0x2004033
-+#define MASK_DIV  0xfe00707f
-+#define MATCH_FMV_H_X 0xf4000053
-+#define MASK_FMV_H_X  0xfff0707f
-+#define MATCH_C_FLD 0x15
-+#define MASK_C_FLD  0x1f
-+#define MATCH_FRRM 0x202073
-+#define MASK_FRRM  0xfffff07f
-+#define MATCH_VFMSV_S 0x1000202b
-+#define MASK_VFMSV_S  0xfff0707f
-+#define MATCH_C_LWSP 0x5
-+#define MASK_C_LWSP  0x1f
-+#define MATCH_FENCE 0xf
-+#define MASK_FENCE  0x707f
-+#define MATCH_FNMSUB_S 0x4b
-+#define MASK_FNMSUB_S  0x600007f
-+#define MATCH_FLE_S 0xa0000053
-+#define MASK_FLE_S  0xfe00707f
-+#define MATCH_FNMSUB_H 0x400004b
-+#define MASK_FNMSUB_H  0x600007f
-+#define MATCH_FLE_H 0xbc000053
-+#define MASK_FLE_H  0xfe00707f
-+#define MATCH_FLW 0x2007
-+#define MASK_FLW  0x707f
-+#define MATCH_VSETVL 0x600b
-+#define MASK_VSETVL  0xfff0707f
-+#define MATCH_VFMSV_D 0x1200202b
-+#define MASK_VFMSV_D  0xfff0707f
-+#define MATCH_FLE_D 0xa2000053
-+#define MASK_FLE_D  0xfe00707f
-+#define MATCH_FENCE_I 0x100f
-+#define MASK_FENCE_I  0x707f
-+#define MATCH_FNMSUB_D 0x200004b
-+#define MASK_FNMSUB_D  0x600007f
-+#define MATCH_ADDW 0x3b
-+#define MASK_ADDW  0xfe00707f
-+#define MATCH_XOR 0x4033
-+#define MASK_XOR  0xfe00707f
-+#define MATCH_SUB 0x40000033
-+#define MASK_SUB  0xfe00707f
-+#define MATCH_VSSTW 0x400307b
-+#define MASK_VSSTW  0xfe00707f
-+#define MATCH_VSSTH 0x200307b
-+#define MASK_VSSTH  0xfe00707f
-+#define MATCH_SC_W 0x1800202f
-+#define MASK_SC_W  0xf800707f
-+#define MATCH_VSSTB 0x307b
-+#define MASK_VSSTB  0xfe00707f
-+#define MATCH_VSSTD 0x600307b
-+#define MASK_VSSTD  0xfe00707f
-+#define MATCH_ADDI 0x13
-+#define MASK_ADDI  0x707f
-+#define MATCH_RDTIMEH 0xc8102073
-+#define MASK_RDTIMEH  0xfffff07f
-+#define MATCH_MULH 0x2001033
-+#define MASK_MULH  0xfe00707f
-+#define MATCH_CSRRSI 0x6073
-+#define MASK_CSRRSI  0x707f
-+#define MATCH_FCVT_D_WU 0xd2100053
-+#define MASK_FCVT_D_WU  0xfff0007f
-+#define MATCH_MULW 0x200003b
-+#define MASK_MULW  0xfe00707f
-+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
-+#define MATCH_VENQIMM1 0xc00302b
-+#define MASK_VENQIMM1  0xfe007fff
-+#define MATCH_VENQIMM2 0xe00302b
-+#define MASK_VENQIMM2  0xfe007fff
-+#define MATCH_RDINSTRET 0xc0202073
-+#define MASK_RDINSTRET  0xfffff07f
-+#define MATCH_C_SWSP 0x8
-+#define MASK_C_SWSP  0x1f
-+#define MATCH_VLSTW 0x400305b
-+#define MASK_VLSTW  0xfe00707f
-+#define MATCH_VLSTH 0x200305b
-+#define MASK_VLSTH  0xfe00707f
-+#define MATCH_VLSTB 0x305b
-+#define MASK_VLSTB  0xfe00707f
-+#define MATCH_VLSTD 0x600305b
-+#define MASK_VLSTD  0xfe00707f
-+#define MATCH_ANDI 0x7013
-+#define MASK_ANDI  0x707f
-+#define MATCH_FMV_X_S 0xe0000053
-+#define MASK_FMV_X_S  0xfff0707f
-+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
-+#define MATCH_FNMADD_S 0x4f
-+#define MASK_FNMADD_S  0x600007f
-+#define MATCH_LWU 0x6003
-+#define MASK_LWU  0x707f
-+#define MATCH_CUSTOM0_RS1 0x200b
-+#define MASK_CUSTOM0_RS1  0x707f
-+#define MATCH_VLSEGSTBU 0x800305b
-+#define MASK_VLSEGSTBU  0x1e00707f
-+#define MATCH_FNMADD_D 0x200004f
-+#define MASK_FNMADD_D  0x600007f
-+#define MATCH_FCVT_W_S 0xc0000053
-+#define MASK_FCVT_W_S  0xfff0007f
-+#define MATCH_C_SRAI 0x1019
-+#define MASK_C_SRAI  0x1c1f
-+#define MATCH_MULHSU 0x2002033
-+#define MASK_MULHSU  0xfe00707f
-+#define MATCH_FCVT_D_LU 0xd2300053
-+#define MASK_FCVT_D_LU  0xfff0007f
-+#define MATCH_FCVT_W_D 0xc2000053
-+#define MASK_FCVT_W_D  0xfff0007f
-+#define MATCH_FSUB_H 0xc000053
-+#define MASK_FSUB_H  0xfe00007f
-+#define MATCH_DIVUW 0x200503b
-+#define MASK_DIVUW  0xfe00707f
-+#define MATCH_SLTI 0x2013
-+#define MASK_SLTI  0x707f
-+#define MATCH_VLSTBU 0x800305b
-+#define MASK_VLSTBU  0xfe00707f
-+#define MATCH_SLTU 0x3033
-+#define MASK_SLTU  0xfe00707f
-+#define MATCH_FLH 0x1007
-+#define MASK_FLH  0x707f
-+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
-+#define MATCH_FLD 0x3007
-+#define MASK_FLD  0x707f
-+#define MATCH_FSUB_S 0x8000053
-+#define MASK_FSUB_S  0xfe00007f
-+#define MATCH_FCVT_H_LU 0x6c000053
-+#define MASK_FCVT_H_LU  0xfff0007f
-+#define MATCH_CUSTOM0 0xb
-+#define MASK_CUSTOM0  0x707f
-+#define MATCH_CUSTOM1 0x2b
-+#define MASK_CUSTOM1  0x707f
-+#define MATCH_CUSTOM2 0x5b
-+#define MASK_CUSTOM2  0x707f
-+#define MATCH_CUSTOM3 0x7b
-+#define MASK_CUSTOM3  0x707f
-+#define MATCH_VXCPTSAVE 0x302b
-+#define MASK_VXCPTSAVE  0xfff07fff
-+#define MATCH_VMSV 0x200202b
-+#define MASK_VMSV  0xfff0707f
-+#define MATCH_FCVT_LU_S 0xc0300053
-+#define MASK_FCVT_LU_S  0xfff0007f
-+#define MATCH_AUIPC 0x17
-+#define MASK_AUIPC  0x7f
-+#define MATCH_FRFLAGS 0x102073
-+#define MASK_FRFLAGS  0xfffff07f
-+#define MATCH_FCVT_LU_D 0xc2300053
-+#define MASK_FCVT_LU_D  0xfff0007f
-+#define MATCH_CSRRWI 0x5073
-+#define MASK_CSRRWI  0x707f
-+#define MATCH_FADD_H 0x4000053
-+#define MASK_FADD_H  0xfe00007f
-+#define MATCH_FSQRT_S 0x58000053
-+#define MASK_FSQRT_S  0xfff0007f
-+#define MATCH_VXCPTKILL 0x400302b
-+#define MASK_VXCPTKILL  0xffffffff
-+#define MATCH_STOP 0x5077
-+#define MASK_STOP  0xffffffff
-+#define MATCH_FSGNJN_S 0x20001053
-+#define MASK_FSGNJN_S  0xfe00707f
-+#define MATCH_FSGNJN_H 0x34000053
-+#define MASK_FSGNJN_H  0xfe00707f
-+#define MATCH_FSQRT_D 0x5a000053
-+#define MASK_FSQRT_D  0xfff0007f
-+#define MATCH_XORI 0x4013
-+#define MASK_XORI  0x707f
-+#define MATCH_DIVU 0x2005033
-+#define MASK_DIVU  0xfe00707f
-+#define MATCH_FSGNJN_D 0x22001053
-+#define MASK_FSGNJN_D  0xfe00707f
-+#define MATCH_FSQRT_H 0x24000053
-+#define MASK_FSQRT_H  0xfff0007f
-+#define MATCH_VSSEGSTH 0x200307b
-+#define MASK_VSSEGSTH  0x1e00707f
-+#define MATCH_SW 0x2023
-+#define MASK_SW  0x707f
-+#define MATCH_VLSTWU 0xc00305b
-+#define MASK_VLSTWU  0xfe00707f
-+#define MATCH_VFSSEGW 0x1400207b
-+#define MASK_VFSSEGW  0x1ff0707f
-+#define MATCH_LHU 0x5003
-+#define MASK_LHU  0x707f
-+#define MATCH_SH 0x1023
-+#define MASK_SH  0x707f
-+#define MATCH_FMSUB_H 0x4000047
-+#define MASK_FMSUB_H  0x600007f
-+#define MATCH_VXCPTAUX 0x200402b
-+#define MASK_VXCPTAUX  0xfffff07f
-+#define MATCH_FMSUB_D 0x2000047
-+#define MASK_FMSUB_D  0x600007f
-+#define MATCH_VFSSEGD 0x1600207b
-+#define MASK_VFSSEGD  0x1ff0707f
-+#define MATCH_VLSEGHU 0xa00205b
-+#define MASK_VLSEGHU  0x1ff0707f
-+#define MATCH_MOVN 0x2007077
-+#define MASK_MOVN  0xfe00707f
-+#define MATCH_CUSTOM1_RS1 0x202b
-+#define MASK_CUSTOM1_RS1  0x707f
-+#define MATCH_VLSTHU 0xa00305b
-+#define MASK_VLSTHU  0xfe00707f
-+#define MATCH_MOVZ 0x7077
-+#define MASK_MOVZ  0xfe00707f
-+#define MATCH_CSRRW 0x1073
-+#define MASK_CSRRW  0x707f
-+#define MATCH_LD 0x3003
-+#define MASK_LD  0x707f
-+#define MATCH_LB 0x3
-+#define MASK_LB  0x707f
-+#define MATCH_VLWU 0xc00205b
-+#define MASK_VLWU  0xfff0707f
-+#define MATCH_LH 0x1003
-+#define MASK_LH  0x707f
-+#define MATCH_LW 0x2003
-+#define MASK_LW  0x707f
-+#define MATCH_CSRRC 0x3073
-+#define MASK_CSRRC  0x707f
-+#define MATCH_FCVT_LU_H 0x4c000053
-+#define MASK_FCVT_LU_H  0xfff0007f
-+#define MATCH_FCVT_S_D 0x40100053
-+#define MASK_FCVT_S_D  0xfff0007f
-+#define MATCH_BGEU 0x7063
-+#define MASK_BGEU  0x707f
-+#define MATCH_VFLSTD 0x1600305b
-+#define MASK_VFLSTD  0xfe00707f
-+#define MATCH_FCVT_S_L 0xd0200053
-+#define MASK_FCVT_S_L  0xfff0007f
-+#define MATCH_FCVT_S_H 0x84000053
-+#define MASK_FCVT_S_H  0xfff0007f
-+#define MATCH_FSCSR 0x301073
-+#define MASK_FSCSR  0xfff0707f
-+#define MATCH_FCVT_S_W 0xd0000053
-+#define MASK_FCVT_S_W  0xfff0007f
-+#define MATCH_VFLSTW 0x1400305b
-+#define MASK_VFLSTW  0xfe00707f
-+#define MATCH_VXCPTEVAC 0x600302b
-+#define MASK_VXCPTEVAC  0xfff07fff
-+#define MATCH_AMOMINU_D 0xc000302f
-+#define MASK_AMOMINU_D  0xf800707f
-+#define MATCH_FSFLAGS 0x101073
-+#define MASK_FSFLAGS  0xfff0707f
-+#define MATCH_SRLI 0x5013
-+#define MASK_SRLI  0xfc00707f
-+#define MATCH_C_SRLI 0x819
-+#define MASK_C_SRLI  0x1c1f
-+#define MATCH_AMOMINU_W 0xc000202f
-+#define MASK_AMOMINU_W  0xf800707f
-+#define MATCH_SRLW 0x503b
-+#define MASK_SRLW  0xfe00707f
-+#define MATCH_VFLSEGW 0x1400205b
-+#define MASK_VFLSEGW  0x1ff0707f
-+#define MATCH_C_LD0 0x8012
-+#define MASK_C_LD0  0x801f
-+#define MATCH_VLSEGBU 0x800205b
-+#define MASK_VLSEGBU  0x1ff0707f
-+#define MATCH_JALR 0x67
-+#define MASK_JALR  0x707f
-+#define MATCH_BLT 0x4063
-+#define MASK_BLT  0x707f
-+#define MATCH_CUSTOM2_RD_RS1 0x605b
-+#define MASK_CUSTOM2_RD_RS1  0x707f
-+#define MATCH_FCLASS_S 0xe0001053
-+#define MASK_FCLASS_S  0xfff0707f
-+#define MATCH_REM 0x2006033
-+#define MASK_REM  0xfe00707f
-+#define MATCH_FCLASS_D 0xe2001053
-+#define MASK_FCLASS_D  0xfff0707f
-+#define MATCH_FMUL_S 0x10000053
-+#define MASK_FMUL_S  0xfe00007f
-+#define MATCH_RDCYCLEH 0xc8002073
-+#define MASK_RDCYCLEH  0xfffff07f
-+#define MATCH_VLSEGSTHU 0xa00305b
-+#define MASK_VLSEGSTHU  0x1e00707f
-+#define MATCH_FMUL_D 0x12000053
-+#define MASK_FMUL_D  0xfe00007f
-+#define MATCH_ORI 0x6013
-+#define MASK_ORI  0x707f
-+#define MATCH_FMUL_H 0x14000053
-+#define MASK_FMUL_H  0xfe00007f
-+#define MATCH_VFLSEGD 0x1600205b
-+#define MASK_VFLSEGD  0x1ff0707f
-+#define MATCH_FEQ_S 0xa0002053
-+#define MASK_FEQ_S  0xfe00707f
-+#define MATCH_FSGNJX_D 0x22002053
-+#define MASK_FSGNJX_D  0xfe00707f
-+#define MATCH_SRAIW 0x4000501b
-+#define MASK_SRAIW  0xfe00707f
-+#define MATCH_FSGNJX_H 0x3c000053
-+#define MASK_FSGNJX_H  0xfe00707f
-+#define MATCH_FSGNJX_S 0x20002053
-+#define MASK_FSGNJX_S  0xfe00707f
-+#define MATCH_FEQ_D 0xa2002053
-+#define MASK_FEQ_D  0xfe00707f
-+#define MATCH_CUSTOM1_RD_RS1 0x602b
-+#define MASK_CUSTOM1_RD_RS1  0x707f
-+#define MATCH_FEQ_H 0xac000053
-+#define MASK_FEQ_H  0xfe00707f
-+#define MATCH_AMOMAXU_D 0xe000302f
-+#define MASK_AMOMAXU_D  0xf800707f
-+#define MATCH_DIVW 0x200403b
-+#define MASK_DIVW  0xfe00707f
-+#define MATCH_AMOMAXU_W 0xe000202f
-+#define MASK_AMOMAXU_W  0xf800707f
-+#define MATCH_SRAI_RV32 0x40005013
-+#define MASK_SRAI_RV32  0xfe00707f
-+#define MATCH_C_SRLI32 0xc19
-+#define MASK_C_SRLI32  0x1c1f
-+#define MATCH_VFSSTW 0x1400307b
-+#define MASK_VFSSTW  0xfe00707f
-+#define MATCH_CUSTOM0_RD 0x400b
-+#define MASK_CUSTOM0_RD  0x707f
-+#define MATCH_C_BEQ 0x10
-+#define MASK_C_BEQ  0x1f
-+#define MATCH_VFSSTD 0x1600307b
-+#define MASK_VFSSTD  0xfe00707f
-+#define MATCH_CUSTOM3_RD_RS1 0x607b
-+#define MASK_CUSTOM3_RD_RS1  0x707f
-+#define MATCH_LR_D 0x1000302f
-+#define MASK_LR_D  0xf9f0707f
-+#define MATCH_LR_W 0x1000202f
-+#define MASK_LR_W  0xf9f0707f
-+#define MATCH_FCVT_H_WU 0x7c000053
-+#define MASK_FCVT_H_WU  0xfff0007f
-+#define MATCH_VMVV 0x200002b
-+#define MASK_VMVV  0xfff0707f
-+#define MATCH_SLLW 0x103b
-+#define MASK_SLLW  0xfe00707f
-+#define MATCH_SLLI 0x1013
-+#define MASK_SLLI  0xfc00707f
-+#define MATCH_BEQ 0x63
-+#define MASK_BEQ  0x707f
-+#define MATCH_AND 0x7033
-+#define MASK_AND  0xfe00707f
-+#define MATCH_LBU 0x4003
-+#define MASK_LBU  0x707f
-+#define MATCH_FSGNJ_S 0x20000053
-+#define MASK_FSGNJ_S  0xfe00707f
-+#define MATCH_FMSUB_S 0x47
-+#define MASK_FMSUB_S  0x600007f
-+#define MATCH_C_SUB3 0x11c
-+#define MASK_C_SUB3  0x31f
-+#define MATCH_FSGNJ_H 0x2c000053
-+#define MASK_FSGNJ_H  0xfe00707f
-+#define MATCH_VLB 0x205b
-+#define MASK_VLB  0xfff0707f
-+#define MATCH_C_ADDIW 0x1d
-+#define MASK_C_ADDIW  0x1f
-+#define MATCH_CUSTOM3_RS1_RS2 0x307b
-+#define MASK_CUSTOM3_RS1_RS2  0x707f
-+#define MATCH_FSGNJ_D 0x22000053
-+#define MASK_FSGNJ_D  0xfe00707f
-+#define MATCH_VLSEGWU 0xc00205b
-+#define MASK_VLSEGWU  0x1ff0707f
-+#define MATCH_FCVT_S_WU 0xd0100053
-+#define MASK_FCVT_S_WU  0xfff0007f
-+#define MATCH_CUSTOM3_RS1 0x207b
-+#define MASK_CUSTOM3_RS1  0x707f
-+#define MATCH_SC_D 0x1800302f
-+#define MASK_SC_D  0xf800707f
-+#define MATCH_VFSW 0x1400207b
-+#define MASK_VFSW  0xfff0707f
-+#define MATCH_AMOSWAP_D 0x800302f
-+#define MASK_AMOSWAP_D  0xf800707f
-+#define MATCH_SB 0x23
-+#define MASK_SB  0x707f
-+#define MATCH_AMOSWAP_W 0x800202f
-+#define MASK_AMOSWAP_W  0xf800707f
-+#define MATCH_VFSD 0x1600207b
-+#define MASK_VFSD  0xfff0707f
-+#define MATCH_CUSTOM2_RS1 0x205b
-+#define MASK_CUSTOM2_RS1  0x707f
-+#define MATCH_SD 0x3023
-+#define MASK_SD  0x707f
-+#define MATCH_FMV_S_X 0xf0000053
-+#define MASK_FMV_S_X  0xfff0707f
-+#define MATCH_REMUW 0x200703b
-+#define MASK_REMUW  0xfe00707f
-+#define MATCH_JAL 0x6f
-+#define MASK_JAL  0x7f
-+#define MATCH_C_FSD 0x18
-+#define MASK_C_FSD  0x1f
-+#define MATCH_RDCYCLE 0xc0002073
-+#define MASK_RDCYCLE  0xfffff07f
-+#define MATCH_C_BNE 0x11
-+#define MASK_C_BNE  0x1f
-+#define MATCH_C_ADD 0x1a
-+#define MASK_C_ADD  0x801f
-+#define MATCH_VXCPTCAUSE 0x402b
-+#define MASK_VXCPTCAUSE  0xfffff07f
-+#define MATCH_VGETCFG 0x400b
-+#define MASK_VGETCFG  0xfffff07f
-+#define MATCH_LUI 0x37
-+#define MASK_LUI  0x7f
-+#define MATCH_VSETCFG 0x200b
-+#define MASK_VSETCFG  0x7fff
-+#define MATCH_C_SDSP 0x6
-+#define MASK_C_SDSP  0x1f
-+#define MATCH_C_LDSP 0x4
-+#define MASK_C_LDSP  0x1f
-+#define MATCH_FNMADD_H 0x400004f
-+#define MASK_FNMADD_H  0x600007f
-+#define MATCH_CUSTOM0_RS1_RS2 0x300b
-+#define MASK_CUSTOM0_RS1_RS2  0x707f
-+#define MATCH_SLLI_RV32 0x1013
-+#define MASK_SLLI_RV32  0xfe00707f
-+#define MATCH_MUL 0x2000033
-+#define MASK_MUL  0xfe00707f
-+#define MATCH_CSRRCI 0x7073
-+#define MASK_CSRRCI  0x707f
-+#define MATCH_C_SRAI32 0x1419
-+#define MASK_C_SRAI32  0x1c1f
-+#define MATCH_FLT_H 0xb4000053
-+#define MASK_FLT_H  0xfe00707f
-+#define MATCH_SRAI 0x40005013
-+#define MASK_SRAI  0xfc00707f
-+#define MATCH_AMOAND_D 0x6000302f
-+#define MASK_AMOAND_D  0xf800707f
-+#define MATCH_FLT_D 0xa2001053
-+#define MASK_FLT_D  0xfe00707f
-+#define MATCH_SRAW 0x4000503b
-+#define MASK_SRAW  0xfe00707f
-+#define MATCH_CSRRS 0x2073
-+#define MASK_CSRRS  0x707f
-+#define MATCH_FLT_S 0xa0001053
-+#define MASK_FLT_S  0xfe00707f
-+#define MATCH_ADDIW 0x1b
-+#define MASK_ADDIW  0x707f
-+#define MATCH_AMOAND_W 0x6000202f
-+#define MASK_AMOAND_W  0xf800707f
-+#define MATCH_CUSTOM2_RD 0x405b
-+#define MASK_CUSTOM2_RD  0x707f
-+#define MATCH_FCVT_WU_D 0xc2100053
-+#define MASK_FCVT_WU_D  0xfff0007f
-+#define MATCH_AMOXOR_W 0x2000202f
-+#define MASK_AMOXOR_W  0xf800707f
-+#define MATCH_FCVT_D_L 0xd2200053
-+#define MASK_FCVT_D_L  0xfff0007f
-+#define MATCH_FCVT_WU_H 0x5c000053
-+#define MASK_FCVT_WU_H  0xfff0007f
-+#define MATCH_C_SLLI 0x19
-+#define MASK_C_SLLI  0x1c1f
-+#define MATCH_AMOXOR_D 0x2000302f
-+#define MASK_AMOXOR_D  0xf800707f
-+#define MATCH_FCVT_WU_S 0xc0100053
-+#define MASK_FCVT_WU_S  0xfff0007f
-+#define MATCH_CUSTOM3_RD 0x407b
-+#define MASK_CUSTOM3_RD  0x707f
-+#define MATCH_FMAX_H 0xcc000053
-+#define MASK_FMAX_H  0xfe00707f
-+#define MATCH_VENQCNT 0x1000302b
-+#define MASK_VENQCNT  0xfe007fff
-+#define MATCH_VLBU 0x800205b
-+#define MASK_VLBU  0xfff0707f
-+#define MATCH_VLHU 0xa00205b
-+#define MASK_VLHU  0xfff0707f
-+#define MATCH_C_SW 0xd
-+#define MASK_C_SW  0x1f
-+#define MATCH_C_SD 0xc
-+#define MASK_C_SD  0x1f
-+#define MATCH_C_OR3 0x21c
-+#define MASK_C_OR3  0x31f
-+#define MATCH_C_AND3 0x31c
-+#define MASK_C_AND3  0x31f
-+#define MATCH_VFSSEGSTW 0x1400307b
-+#define MASK_VFSSEGSTW  0x1e00707f
-+#define MATCH_SLT 0x2033
-+#define MASK_SLT  0xfe00707f
-+#define MATCH_AMOOR_D 0x4000302f
-+#define MASK_AMOOR_D  0xf800707f
-+#define MATCH_REMU 0x2007033
-+#define MASK_REMU  0xfe00707f
-+#define MATCH_REMW 0x200603b
-+#define MASK_REMW  0xfe00707f
-+#define MATCH_SLL 0x1033
-+#define MASK_SLL  0xfe00707f
-+#define MATCH_VFSSEGSTD 0x1600307b
-+#define MASK_VFSSEGSTD  0x1e00707f
-+#define MATCH_AMOOR_W 0x4000202f
-+#define MASK_AMOOR_W  0xf800707f
-+#define MATCH_CUSTOM2_RS1_RS2 0x305b
-+#define MASK_CUSTOM2_RS1_RS2  0x707f
-+#define MATCH_VF 0x10202b
-+#define MASK_VF  0x1f0707f
-+#define MATCH_VFMVV 0x1000002b
-+#define MASK_VFMVV  0xfff0707f
-+#define MATCH_VFLSEGSTW 0x1400305b
-+#define MASK_VFLSEGSTW  0x1e00707f
-+#define MATCH_VXCPTRESTORE 0x200302b
-+#define MASK_VXCPTRESTORE  0xfff07fff
-+#define MATCH_VXCPTHOLD 0x800302b
-+#define MASK_VXCPTHOLD  0xffffffff
-+#define MATCH_SLTIU 0x3013
-+#define MASK_SLTIU  0x707f
-+#define MATCH_VFLSEGSTD 0x1600305b
-+#define MASK_VFLSEGSTD  0x1e00707f
-+#define MATCH_VFLD 0x1600205b
-+#define MASK_VFLD  0xfff0707f
-+#define MATCH_FMADD_S 0x43
-+#define MASK_FMADD_S  0x600007f
-+#define MATCH_VFLW 0x1400205b
-+#define MASK_VFLW  0xfff0707f
-+#define MATCH_FMADD_D 0x2000043
-+#define MASK_FMADD_D  0x600007f
-+#define MATCH_FMADD_H 0x4000043
-+#define MASK_FMADD_H  0x600007f
-+#define MATCH_SRET 0x80000073
-+#define MASK_SRET  0xffffffff
-+#define MATCH_VSSEGW 0x400207b
-+#define MASK_VSSEGW  0x1ff0707f
-+#define MATCH_CUSTOM0_RD_RS1 0x600b
-+#define MASK_CUSTOM0_RD_RS1  0x707f
-+#define MATCH_VSSEGH 0x200207b
-+#define MASK_VSSEGH  0x1ff0707f
-+#define MATCH_FRCSR 0x302073
-+#define MASK_FRCSR  0xfffff07f
-+#define MATCH_VSSEGD 0x600207b
-+#define MASK_VSSEGD  0x1ff0707f
-+#define MATCH_VSSEGB 0x207b
-+#define MASK_VSSEGB  0x1ff0707f
-+#define MATCH_FMIN_H 0xc4000053
-+#define MASK_FMIN_H  0xfe00707f
-+#define MATCH_FMIN_D 0x2a000053
-+#define MASK_FMIN_D  0xfe00707f
-+#define MATCH_BLTU 0x6063
-+#define MASK_BLTU  0x707f
-+#define MATCH_FMIN_S 0x28000053
-+#define MASK_FMIN_S  0xfe00707f
-+#define MATCH_SRLI_RV32 0x5013
-+#define MASK_SRLI_RV32  0xfe00707f
-+#define MATCH_SLLIW 0x101b
-+#define MASK_SLLIW  0xfe00707f
-+#define MATCH_FMAX_S 0x28001053
-+#define MASK_FMAX_S  0xfe00707f
-+#define MATCH_FCVT_D_H 0x8c000053
-+#define MASK_FCVT_D_H  0xfff0007f
-+#define MATCH_FCVT_D_W 0xd2000053
-+#define MASK_FCVT_D_W  0xfff0007f
-+#define MATCH_ADD 0x33
-+#define MASK_ADD  0xfe00707f
-+#define MATCH_FCVT_D_S 0x42000053
-+#define MASK_FCVT_D_S  0xfff0007f
-+#define MATCH_FMAX_D 0x2a001053
-+#define MASK_FMAX_D  0xfe00707f
-+#define MATCH_BNE 0x1063
-+#define MASK_BNE  0x707f
-+#define MATCH_CUSTOM1_RD 0x402b
-+#define MASK_CUSTOM1_RD  0x707f
-+#define MATCH_FSRM 0x201073
-+#define MASK_FSRM  0xfff0707f
-+#define MATCH_FDIV_D 0x1a000053
-+#define MASK_FDIV_D  0xfe00007f
-+#define MATCH_VSW 0x400207b
-+#define MASK_VSW  0xfff0707f
-+#define MATCH_FCVT_L_S 0xc0200053
-+#define MASK_FCVT_L_S  0xfff0007f
-+#define MATCH_FDIV_H 0x1c000053
-+#define MASK_FDIV_H  0xfe00007f
-+#define MATCH_VSB 0x207b
-+#define MASK_VSB  0xfff0707f
-+#define MATCH_FDIV_S 0x18000053
-+#define MASK_FDIV_S  0xfe00007f
-+#define MATCH_FSRMI 0x205073
-+#define MASK_FSRMI  0xfff0707f
-+#define MATCH_FCVT_L_H 0x44000053
-+#define MASK_FCVT_L_H  0xfff0007f
-+#define MATCH_VSH 0x200207b
-+#define MASK_VSH  0xfff0707f
-+#define MATCH_FCVT_L_D 0xc2200053
-+#define MASK_FCVT_L_D  0xfff0007f
-+#define MATCH_FCVT_H_S 0x90000053
-+#define MASK_FCVT_H_S  0xfff0007f
-+#define MATCH_SCALL 0x73
-+#define MASK_SCALL  0xffffffff
-+#define MATCH_FSFLAGSI 0x105073
-+#define MASK_FSFLAGSI  0xfff0707f
-+#define MATCH_FCVT_H_W 0x74000053
-+#define MASK_FCVT_H_W  0xfff0007f
-+#define MATCH_FCVT_H_L 0x64000053
-+#define MASK_FCVT_H_L  0xfff0007f
-+#define MATCH_SRLIW 0x501b
-+#define MASK_SRLIW  0xfe00707f
-+#define MATCH_FCVT_S_LU 0xd0300053
-+#define MASK_FCVT_S_LU  0xfff0007f
-+#define MATCH_FCVT_H_D 0x92000053
-+#define MASK_FCVT_H_D  0xfff0007f
-+#define MATCH_SBREAK 0x100073
-+#define MASK_SBREAK  0xffffffff
-+#define MATCH_RDINSTRETH 0xc8202073
-+#define MASK_RDINSTRETH  0xfffff07f
-+#define MATCH_SRA 0x40005033
-+#define MASK_SRA  0xfe00707f
-+#define MATCH_BGE 0x5063
-+#define MASK_BGE  0x707f
-+#define MATCH_SRL 0x5033
-+#define MASK_SRL  0xfe00707f
-+#define MATCH_VENQCMD 0xa00302b
-+#define MASK_VENQCMD  0xfe007fff
-+#define MATCH_OR 0x6033
-+#define MASK_OR  0xfe00707f
-+#define MATCH_SUBW 0x4000003b
-+#define MASK_SUBW  0xfe00707f
-+#define MATCH_FMV_X_D 0xe2000053
-+#define MASK_FMV_X_D  0xfff0707f
-+#define MATCH_RDTIME 0xc0102073
-+#define MASK_RDTIME  0xfffff07f
-+#define MATCH_AMOADD_D 0x302f
-+#define MASK_AMOADD_D  0xf800707f
-+#define MATCH_AMOMAX_W 0xa000202f
-+#define MASK_AMOMAX_W  0xf800707f
-+#define MATCH_C_MOVE 0x2
-+#define MASK_C_MOVE  0x801f
-+#define MATCH_FMOVN 0x6007077
-+#define MASK_FMOVN  0xfe00707f
-+#define MATCH_C_FSW 0x16
-+#define MASK_C_FSW  0x1f
-+#define MATCH_AMOADD_W 0x202f
-+#define MASK_AMOADD_W  0xf800707f
-+#define MATCH_AMOMAX_D 0xa000302f
-+#define MASK_AMOMAX_D  0xf800707f
-+#define MATCH_FMOVZ 0x4007077
-+#define MASK_FMOVZ  0xfe00707f
-+#define MATCH_CUSTOM1_RS1_RS2 0x302b
-+#define MASK_CUSTOM1_RS1_RS2  0x707f
-+#define MATCH_FMV_X_H 0xe4000053
-+#define MASK_FMV_X_H  0xfff0707f
-+#define MATCH_VSD 0x600207b
-+#define MASK_VSD  0xfff0707f
-+#define MATCH_VLSEGSTW 0x400305b
-+#define MASK_VLSEGSTW  0x1e00707f
-+#define MATCH_C_ADDI 0x1
-+#define MASK_C_ADDI  0x1f
-+#define MATCH_C_SLLIW 0x1819
-+#define MASK_C_SLLIW  0x1c1f
-+#define MATCH_VLSEGSTB 0x305b
-+#define MASK_VLSEGSTB  0x1e00707f
-+#define MATCH_VLSEGSTD 0x600305b
-+#define MASK_VLSEGSTD  0x1e00707f
-+#define MATCH_VLSEGSTH 0x200305b
-+#define MASK_VLSEGSTH  0x1e00707f
-+#define MATCH_MULHU 0x2003033
-+#define MASK_MULHU  0xfe00707f
-+#define MATCH_AMOMIN_W 0x8000202f
-+#define MASK_AMOMIN_W  0xf800707f
-+#define MATCH_C_SLLI32 0x419
-+#define MASK_C_SLLI32  0x1c1f
-+#define MATCH_C_ADD3 0x1c
-+#define MASK_C_ADD3  0x31f
-+#define MATCH_VGETVL 0x200400b
-+#define MASK_VGETVL  0xfffff07f
-+#define MATCH_AMOMIN_D 0x8000302f
-+#define MASK_AMOMIN_D  0xf800707f
-+#define MATCH_FCVT_W_H 0x54000053
-+#define MASK_FCVT_W_H  0xfff0007f
-+#define MATCH_VLSEGB 0x205b
-+#define MASK_VLSEGB  0x1ff0707f
-+#define MATCH_FSD 0x3027
-+#define MASK_FSD  0x707f
-+#define MATCH_VLSEGD 0x600205b
-+#define MASK_VLSEGD  0x1ff0707f
-+#define MATCH_FSH 0x1027
-+#define MASK_FSH  0x707f
-+#define MATCH_VLSEGH 0x200205b
-+#define MASK_VLSEGH  0x1ff0707f
-+#define MATCH_C_SUB 0x801a
-+#define MASK_C_SUB  0x801f
-+#define MATCH_VLSEGW 0x400205b
-+#define MASK_VLSEGW  0x1ff0707f
-+#define MATCH_FSW 0x2027
-+#define MASK_FSW  0x707f
-+#define MATCH_C_J 0x8002
-+#define MASK_C_J  0x801f
-+#define CSR_FFLAGS 0x1
-+#define CSR_FRM 0x2
-+#define CSR_FCSR 0x3
-+#define CSR_STATS 0xc0
-+#define CSR_SUP0 0x500
-+#define CSR_SUP1 0x501
-+#define CSR_EPC 0x502
-+#define CSR_BADVADDR 0x503
-+#define CSR_PTBR 0x504
-+#define CSR_ASID 0x505
-+#define CSR_COUNT 0x506
-+#define CSR_COMPARE 0x507
-+#define CSR_EVEC 0x508
-+#define CSR_CAUSE 0x509
-+#define CSR_STATUS 0x50a
-+#define CSR_HARTID 0x50b
-+#define CSR_IMPL 0x50c
-+#define CSR_FATC 0x50d
-+#define CSR_SEND_IPI 0x50e
-+#define CSR_CLEAR_IPI 0x50f
-+#define CSR_RESET 0x51d
-+#define CSR_TOHOST 0x51e
-+#define CSR_FROMHOST 0x51f
-+#define CSR_CYCLE 0xc00
-+#define CSR_TIME 0xc01
-+#define CSR_INSTRET 0xc02
-+#define CSR_UARCH0 0xcc0
-+#define CSR_UARCH1 0xcc1
-+#define CSR_UARCH2 0xcc2
-+#define CSR_UARCH3 0xcc3
-+#define CSR_UARCH4 0xcc4
-+#define CSR_UARCH5 0xcc5
-+#define CSR_UARCH6 0xcc6
-+#define CSR_UARCH7 0xcc7
-+#define CSR_UARCH8 0xcc8
-+#define CSR_UARCH9 0xcc9
-+#define CSR_UARCH10 0xcca
-+#define CSR_UARCH11 0xccb
-+#define CSR_UARCH12 0xccc
-+#define CSR_UARCH13 0xccd
-+#define CSR_UARCH14 0xcce
-+#define CSR_UARCH15 0xccf
-+#define CSR_COUNTH 0x586
-+#define CSR_CYCLEH 0xc80
-+#define CSR_TIMEH 0xc81
-+#define CSR_INSTRETH 0xc82
-+#define CAUSE_MISALIGNED_FETCH 0x0
-+#define CAUSE_FAULT_FETCH 0x1
-+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
-+#define CAUSE_PRIVILEGED_INSTRUCTION 0x3
-+#define CAUSE_FP_DISABLED 0x4
-+#define CAUSE_SYSCALL 0x6
-+#define CAUSE_BREAKPOINT 0x7
-+#define CAUSE_MISALIGNED_LOAD 0x8
-+#define CAUSE_MISALIGNED_STORE 0x9
-+#define CAUSE_FAULT_LOAD 0xa
-+#define CAUSE_FAULT_STORE 0xb
-+#define CAUSE_ACCELERATOR_DISABLED 0xc
-+#endif
-+#ifdef DECLARE_INSN
-+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-+DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
-+DECLARE_INSN(c_lw0, MATCH_C_LW0, MASK_C_LW0)
-+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
-+DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
-+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
-+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
-+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
-+DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
-+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
-+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
-+DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
-+DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
-+DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
-+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
-+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
-+DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
-+DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
-+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
-+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
-+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
-+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
-+DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
-+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
-+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
-+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
-+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
-+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
-+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
-+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
-+DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
-+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
-+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
-+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
-+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
-+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
-+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
-+DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
-+DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
-+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
-+DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
-+DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
-+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
-+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
-+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
-+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
-+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
-+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
-+DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
-+DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
-+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
-+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
-+DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
-+DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
-+DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
-+DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
-+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
-+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
-+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
-+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
-+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
-+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
-+DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
-+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
-+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
-+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
-+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
-+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
-+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
-+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
-+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
-+DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
-+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
-+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
-+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
-+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
-+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
-+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
-+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
-+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
-+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
-+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
-+DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
-+DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
-+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
-+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
-+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
-+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
-+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
-+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
-+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
-+DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
-+DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
-+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
-+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
-+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
-+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
-+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
-+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
-+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
-+DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
-+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
-+DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
-+DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
-+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
-+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
-+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
-+DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
-+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
-+DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
-+DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
-+DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
-+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
-+DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
-+DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
-+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
-+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-+DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
-+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
-+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
-+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
-+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
-+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
-+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
-+DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
-+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
-+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
-+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
-+DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
-+DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
-+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
-+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
-+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
-+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
-+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
-+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
-+DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
-+DECLARE_INSN(c_ld0, MATCH_C_LD0, MASK_C_LD0)
-+DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
-+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
-+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
-+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
-+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
-+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
-+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
-+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
-+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
-+DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
-+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
-+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
-+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
-+DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
-+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
-+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
-+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
-+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
-+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
-+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
-+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
-+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
-+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
-+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
-+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
-+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
-+DECLARE_INSN(c_srli32, MATCH_C_SRLI32, MASK_C_SRLI32)
-+DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
-+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
-+DECLARE_INSN(c_beq, MATCH_C_BEQ, MASK_C_BEQ)
-+DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
-+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
-+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
-+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
-+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
-+DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
-+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
-+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
-+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
-+DECLARE_INSN(and, MATCH_AND, MASK_AND)
-+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
-+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
-+DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
-+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
-+DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
-+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
-+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
-+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
-+DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
-+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
-+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
-+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
-+DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
-+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
-+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
-+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
-+DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
-+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
-+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
-+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
-+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
-+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
-+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
-+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
-+DECLARE_INSN(c_bne, MATCH_C_BNE, MASK_C_BNE)
-+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
-+DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
-+DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
-+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
-+DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
-+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
-+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
-+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
-+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
-+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
-+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
-+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
-+DECLARE_INSN(c_srai32, MATCH_C_SRAI32, MASK_C_SRAI32)
-+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
-+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
-+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
-+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
-+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
-+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
-+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
-+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
-+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
-+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
-+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
-+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
-+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
-+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
-+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
-+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
-+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
-+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
-+DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
-+DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
-+DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
-+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
-+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
-+DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
-+DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
-+DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
-+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
-+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
-+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
-+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
-+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
-+DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
-+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
-+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
-+DECLARE_INSN(vf, MATCH_VF, MASK_VF)
-+DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
-+DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
-+DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
-+DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
-+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
-+DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
-+DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
-+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
-+DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
-+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
-+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
-+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
-+DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
-+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
-+DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
-+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
-+DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
-+DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
-+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
-+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
-+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
-+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
-+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
-+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
-+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
-+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
-+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
-+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
-+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
-+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
-+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
-+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
-+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
-+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
-+DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
-+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
-+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
-+DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
-+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
-+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
-+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
-+DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
-+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
-+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
-+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
-+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
-+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
-+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
-+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
-+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
-+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
-+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
-+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
-+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
-+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
-+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
-+DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
-+DECLARE_INSN(or, MATCH_OR, MASK_OR)
-+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
-+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
-+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
-+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
-+DECLARE_INSN(c_move, MATCH_C_MOVE, MASK_C_MOVE)
-+DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
-+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
-+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
-+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
-+DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
-+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
-+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
-+DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
-+DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
-+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
-+DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
-+DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
-+DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
-+DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
-+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
-+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
-+DECLARE_INSN(c_slli32, MATCH_C_SLLI32, MASK_C_SLLI32)
-+DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
-+DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
-+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
-+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
-+DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
-+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
-+DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
-+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
-+DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
-+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
-+DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
-+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
-+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
-+#endif
-+#ifdef DECLARE_CSR
-+DECLARE_CSR(fflags, CSR_FFLAGS)
-+DECLARE_CSR(frm, CSR_FRM)
-+DECLARE_CSR(fcsr, CSR_FCSR)
-+DECLARE_CSR(stats, CSR_STATS)
-+DECLARE_CSR(sup0, CSR_SUP0)
-+DECLARE_CSR(sup1, CSR_SUP1)
-+DECLARE_CSR(epc, CSR_EPC)
-+DECLARE_CSR(badvaddr, CSR_BADVADDR)
-+DECLARE_CSR(ptbr, CSR_PTBR)
-+DECLARE_CSR(asid, CSR_ASID)
-+DECLARE_CSR(count, CSR_COUNT)
-+DECLARE_CSR(compare, CSR_COMPARE)
-+DECLARE_CSR(evec, CSR_EVEC)
-+DECLARE_CSR(cause, CSR_CAUSE)
-+DECLARE_CSR(status, CSR_STATUS)
-+DECLARE_CSR(hartid, CSR_HARTID)
-+DECLARE_CSR(impl, CSR_IMPL)
-+DECLARE_CSR(fatc, CSR_FATC)
-+DECLARE_CSR(send_ipi, CSR_SEND_IPI)
-+DECLARE_CSR(clear_ipi, CSR_CLEAR_IPI)
-+DECLARE_CSR(reset, CSR_RESET)
-+DECLARE_CSR(tohost, CSR_TOHOST)
-+DECLARE_CSR(fromhost, CSR_FROMHOST)
-+DECLARE_CSR(cycle, CSR_CYCLE)
-+DECLARE_CSR(time, CSR_TIME)
-+DECLARE_CSR(instret, CSR_INSTRET)
-+DECLARE_CSR(uarch0, CSR_UARCH0)
-+DECLARE_CSR(uarch1, CSR_UARCH1)
-+DECLARE_CSR(uarch2, CSR_UARCH2)
-+DECLARE_CSR(uarch3, CSR_UARCH3)
-+DECLARE_CSR(uarch4, CSR_UARCH4)
-+DECLARE_CSR(uarch5, CSR_UARCH5)
-+DECLARE_CSR(uarch6, CSR_UARCH6)
-+DECLARE_CSR(uarch7, CSR_UARCH7)
-+DECLARE_CSR(uarch8, CSR_UARCH8)
-+DECLARE_CSR(uarch9, CSR_UARCH9)
-+DECLARE_CSR(uarch10, CSR_UARCH10)
-+DECLARE_CSR(uarch11, CSR_UARCH11)
-+DECLARE_CSR(uarch12, CSR_UARCH12)
-+DECLARE_CSR(uarch13, CSR_UARCH13)
-+DECLARE_CSR(uarch14, CSR_UARCH14)
-+DECLARE_CSR(uarch15, CSR_UARCH15)
-+DECLARE_CSR(counth, CSR_COUNTH)
-+DECLARE_CSR(cycleh, CSR_CYCLEH)
-+DECLARE_CSR(timeh, CSR_TIMEH)
-+DECLARE_CSR(instreth, CSR_INSTRETH)
-+#endif
-+#ifdef DECLARE_CAUSE
-+DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
-+DECLARE_CAUSE("frm", CAUSE_FRM)
-+DECLARE_CAUSE("fcsr", CAUSE_FCSR)
-+DECLARE_CAUSE("stats", CAUSE_STATS)
-+DECLARE_CAUSE("sup0", CAUSE_SUP0)
-+DECLARE_CAUSE("sup1", CAUSE_SUP1)
-+DECLARE_CAUSE("epc", CAUSE_EPC)
-+DECLARE_CAUSE("badvaddr", CAUSE_BADVADDR)
-+DECLARE_CAUSE("ptbr", CAUSE_PTBR)
-+DECLARE_CAUSE("asid", CAUSE_ASID)
-+DECLARE_CAUSE("count", CAUSE_COUNT)
-+DECLARE_CAUSE("compare", CAUSE_COMPARE)
-+DECLARE_CAUSE("evec", CAUSE_EVEC)
-+DECLARE_CAUSE("cause", CAUSE_CAUSE)
-+DECLARE_CAUSE("status", CAUSE_STATUS)
-+DECLARE_CAUSE("hartid", CAUSE_HARTID)
-+DECLARE_CAUSE("impl", CAUSE_IMPL)
-+DECLARE_CAUSE("fatc", CAUSE_FATC)
-+DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
-+DECLARE_CAUSE("clear_ipi", CAUSE_CLEAR_IPI)
-+DECLARE_CAUSE("reset", CAUSE_RESET)
-+DECLARE_CAUSE("tohost", CAUSE_TOHOST)
-+DECLARE_CAUSE("fromhost", CAUSE_FROMHOST)
-+DECLARE_CAUSE("cycle", CAUSE_CYCLE)
-+DECLARE_CAUSE("time", CAUSE_TIME)
-+DECLARE_CAUSE("instret", CAUSE_INSTRET)
-+DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
-+DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
-+DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
-+DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
-+DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
-+DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
-+DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
-+DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
-+DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
-+DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
-+DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
-+DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
-+DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
-+DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
-+DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
-+DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
-+DECLARE_CAUSE("counth", CAUSE_COUNTH)
-+DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
-+DECLARE_CAUSE("timeh", CAUSE_TIMEH)
-+DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
-+#endif
-diff -urN original-gcc/gcc/config/riscv/riscv.opt gcc/gcc/config/riscv/riscv.opt
---- original-gcc/gcc/config/riscv/riscv.opt	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/riscv.opt	2015-03-07 09:51:45.667139025 +0100
-@@ -0,0 +1,75 @@
+diff -urN empty/gcc/config/riscv/riscv.opt gcc-5.2.0/gcc/config/riscv/riscv.opt
+--- empty/gcc/config/riscv/riscv.opt	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/riscv.opt	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,87 @@
 +; Options for the MIPS port of the compiler
 +;
 +; Copyright (C) 2005, 2007, 2008, 2010, 2011 Free Software Foundation, Inc.
@@ -10180,105 +10877,24 @@
 +Target Report Mask(MULDIV)
 +Use hardware instructions for integer multiplication and division.
 +
++mrvc
++Target Report Mask(RVC)
++Use compressed instruction encoding
++
++msave-restore
++Target Report Mask(SAVE_RESTORE)
++Use smaller but slower prologue and epilogue code
++
 +mlra
 +Target Report Var(riscv_lra_flag) Init(0) Save
 +Use LRA instead of reload
-diff -urN original-gcc/gcc/config/riscv/riscv-protos.h gcc/gcc/config/riscv/riscv-protos.h
---- original-gcc/gcc/config/riscv/riscv-protos.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/riscv-protos.h	2015-03-07 09:51:45.663139025 +0100
-@@ -0,0 +1,89 @@
-+/* Definition of RISC-V target for GNU compiler.
-+   Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+   Based on MIPS target for GNU compiler.
 +
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3.  If not see
-+<http://www.gnu.org/licenses/>.  */
-+
-+#ifndef GCC_RISCV_PROTOS_H
-+#define GCC_RISCV_PROTOS_H
-+
-+enum riscv_symbol_type {
-+  SYMBOL_ABSOLUTE,
-+  SYMBOL_GOT_DISP,
-+  SYMBOL_TLS,
-+  SYMBOL_TLS_LE,
-+  SYMBOL_TLS_IE,
-+  SYMBOL_TLS_GD
-+};
-+#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
-+
-+extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
-+extern int riscv_regno_mode_ok_for_base_p (int, enum machine_mode, bool);
-+extern int riscv_address_insns (rtx, enum machine_mode, bool);
-+extern int riscv_const_insns (rtx);
-+extern int riscv_split_const_insns (rtx);
-+extern int riscv_load_store_insns (rtx, rtx);
-+extern rtx riscv_emit_move (rtx, rtx);
-+extern bool riscv_split_symbol (rtx, rtx, enum machine_mode, rtx *);
-+extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
-+extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
-+extern bool riscv_legitimize_move (enum machine_mode, rtx, rtx);
-+extern bool riscv_legitimize_vector_move (enum machine_mode, rtx, rtx);
-+
-+extern rtx riscv_subword (rtx, bool);
-+extern bool riscv_split_64bit_move_p (rtx, rtx);
-+extern void riscv_split_doubleword_move (rtx, rtx);
-+extern const char *riscv_output_move (rtx, rtx);
-+extern const char *riscv_riscv_output_vector_move (enum machine_mode, rtx, rtx);
-+#ifdef RTX_CODE
-+extern void riscv_expand_scc (rtx *);
-+extern void riscv_expand_conditional_branch (rtx *);
-+#endif
-+extern rtx riscv_expand_call (bool, rtx, rtx, rtx);
-+extern void riscv_expand_fcc_reload (rtx, rtx, rtx);
-+extern void riscv_set_return_address (rtx, rtx);
-+extern bool riscv_expand_block_move (rtx, rtx, rtx);
-+extern void riscv_expand_synci_loop (rtx, rtx);
-+
-+extern bool riscv_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT,
-+					       HOST_WIDE_INT);
-+extern bool riscv_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT,
-+						HOST_WIDE_INT);
-+extern void riscv_order_regs_for_local_alloc (void);
-+
-+extern rtx riscv_return_addr (int, rtx);
-+extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
-+extern void riscv_expand_prologue (void);
-+extern void riscv_expand_epilogue (bool);
-+extern bool riscv_can_use_return_insn (void);
-+extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
-+
-+extern enum reg_class riscv_secondary_reload_class (enum reg_class,
-+						   enum machine_mode,
-+						   rtx, bool);
-+extern int riscv_class_max_nregs (enum reg_class, enum machine_mode);
-+
-+extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode);
-+
-+extern void irix_asm_output_align (FILE *, unsigned);
-+extern const char *current_section_name (void);
-+extern unsigned int current_section_flags (void);
-+
-+extern void riscv_expand_vector_init (rtx, rtx);
-+
-+#endif /* ! GCC_RISCV_PROTOS_H */
-diff -urN original-gcc/gcc/config/riscv/sync.md gcc/gcc/config/riscv/sync.md
---- original-gcc/gcc/config/riscv/sync.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/sync.md	2015-03-07 09:51:45.667139025 +0100
++mcmodel=
++Target RejectNegative Joined Var(riscv_cmodel_string)
++Use given RISC-V code model (medlow or medany)
+diff -urN empty/gcc/config/riscv/sync.md gcc-5.2.0/gcc/config/riscv/sync.md
+--- empty/gcc/config/riscv/sync.md	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/sync.md	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,198 @@
 +;; Machine description for RISC-V atomic operations.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
@@ -10478,297 +11094,36 @@
 +				    gen_lowpart (SImode, shmt)));
 +  DONE;
 +})
-diff -urN original-gcc/gcc/config/riscv/t-elf gcc/gcc/config/riscv/t-elf
---- original-gcc/gcc/config/riscv/t-elf	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/t-elf	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/gcc/config/riscv/t-elf gcc-5.2.0/gcc/config/riscv/t-elf
+--- empty/gcc/config/riscv/t-elf	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/t-elf	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,4 @@
 +# Build the libraries for both hard and soft floating point
 +
 +MULTILIB_OPTIONS = msoft-float m64/m32 mno-atomic
 +MULTILIB_DIRNAMES = soft-float 64 32 no-atomic
-diff -urN original-gcc/gcc/config/riscv/t-linux64 gcc/gcc/config/riscv/t-linux64
---- original-gcc/gcc/config/riscv/t-linux64	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/gcc/config/riscv/t-linux64	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/gcc/config/riscv/t-linux64 gcc-5.2.0/gcc/config/riscv/t-linux64
+--- empty/gcc/config/riscv/t-linux64	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/gcc/config/riscv/t-linux64	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,5 @@
 +# Build the libraries for both hard and soft floating point
 +
 +MULTILIB_OPTIONS = m64/m32 msoft-float mno-atomic
 +MULTILIB_DIRNAMES = 64 32 soft-float no-atomic
 +MULTILIB_OSDIRNAMES = ../lib ../lib32
-diff -urN original-gcc/gcc/config.gcc gcc/gcc/config.gcc
---- original-gcc/gcc/config.gcc	2014-09-17 16:16:02.000000000 +0200
-+++ gcc-4.9.2/gcc/config.gcc	2015-03-07 09:57:54.195132741 +0100
-@@ -447,6 +447,10 @@
- 	esac
- 	extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
- 	;;
-+riscv*)
-+	cpu_type=riscv
-+	need_64bit_hwint=yes
-+	;;
- rs6000*-*-*)
- 	need_64bit_hwint=yes
- 	extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
-@@ -1949,6 +1953,27 @@
- 	cxx_target_objs="${cxx_target_objs} microblaze-c.o"
- 	tmake_file="${tmake_file} microblaze/t-microblaze"
-         ;;
-+riscv32*-*-linux*)				# Linux RISC-V
-+	tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h riscv/default-32.h ${tm_file} riscv/linux.h riscv/linux64.h"
-+	tmake_file="${tmake_file} riscv/t-linux64"
-+	gnu_ld=yes
-+	gas=yes
-+	gcc_cv_initfini_array=yes
-+	;;
-+riscv*-*-linux*)				# Linux RISC-V
-+	tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} riscv/linux.h riscv/linux64.h"
-+	tmake_file="${tmake_file} riscv/t-linux64"
-+	gnu_ld=yes
-+	gas=yes
-+	gcc_cv_initfini_array=yes
-+	;;
-+riscv*-*-elf*)				# Linux RISC-V
-+	tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
-+	tmake_file="${tmake_file} riscv/t-elf"
-+	gnu_ld=yes
-+	gas=yes
-+	gcc_cv_initfini_array=yes
-+	;;
- mips*-*-netbsd*)			# NetBSD/mips, either endian.
- 	target_cpu_default="MASK_ABICALLS"
- 	tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h"
-@@ -3756,6 +3781,31 @@
- 		done
- 		;;
- 
-+	riscv*-*-*)
-+		supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64"
-+
-+		case ${with_float} in
-+		"" | soft | hard)
-+			# OK
-+			;;
-+		*)
-+			echo "Unknown floating point type used in --with-float=$with_float" 1>&2
-+			exit 1
-+			;;
-+		esac
-+
-+		case ${with_abi} in
-+		"" | 32 | 64)
-+			# OK
-+			;;
-+		*)
-+			echo "Unknown ABI used in --with-abi=$with_abi" 1>&2
-+			exit 1
-+			;;
-+		esac
-+
-+    ;;
-+
- 	mips*-*-*)
- 		supported_defaults="abi arch arch_32 arch_64 float fpu nan tune tune_32 tune_64 divide llsc mips-plt synci"
- 
-diff -urN original-gcc/gcc/configure gcc/gcc/configure
---- original-gcc/gcc/configure	2014-10-10 14:51:28.000000000 +0200
-+++ gcc-4.9.2/gcc/configure	2015-03-07 09:57:54.211132741 +0100
-@@ -23515,6 +23515,25 @@
- 	tls_first_minor=14
- 	tls_as_opt="-a32 --fatal-warnings"
- 	;;
-+  riscv*-*-*)
-+    conftest_s='
-+	.section .tdata,"awT",@progbits
-+x:
-+	.word 2
-+	.text
-+	la.tls.gd a0,x
-+	la.tls.ie a1,x
-+	lui a0,%tls_ie_pcrel_hi(x)
-+	lw a0,%pcrel_lo(x)(a0)
-+	add a0,a0,tp
-+	lw a0,0(a0)
-+	lui a0,%tprel_hi(x)
-+	add a0,a0,tp,%tprel_add(x)
-+	lw a0,%tprel_lo(x)(a0)'
-+	tls_first_major=2
-+	tls_first_minor=21
-+	tls_as_opt='-m32 --fatal-warnings'
-+	;;
-   s390-*-*)
-     conftest_s='
- 	.section ".tdata","awT",@progbits
-diff -urN original-gcc/gcc/configure.ac gcc/gcc/configure.ac
---- original-gcc/gcc/configure.ac	2014-10-10 14:51:28.000000000 +0200
-+++ gcc-4.9.2/gcc/configure.ac	2015-03-07 09:57:54.219132741 +0100
-@@ -3178,6 +3178,25 @@
- 	tls_first_minor=14
- 	tls_as_opt="-a32 --fatal-warnings"
- 	;;
-+  riscv*-*-*)
-+    conftest_s='
-+	.section .tdata,"awT",@progbits
-+x:
-+	.word 2
-+	.text
-+	la.tls.gd a0,x
-+	la.tls.ie a1,x
-+	lui a0,%tls_ie_pcrel_hi(x)
-+	lw a0,%pcrel_lo(x)(a0)
-+	add a0,a0,tp
-+	lw a0,0(a0)
-+	lui a0,%tprel_hi(x)
-+	add a0,a0,tp,%tprel_add(x)
-+	lw a0,%tprel_lo(x)(a0)'
-+	tls_first_major=2
-+	tls_first_minor=21
-+	tls_as_opt='-m32 --fatal-warnings'
-+	;;
-   s390-*-*)
-     conftest_s='
- 	.section ".tdata","awT",@progbits
-diff -urN original-gcc/gcc/testsuite/gcc.c-torture/execute/20101011-1.c gcc/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
---- original-gcc/gcc/testsuite/gcc.c-torture/execute/20101011-1.c	2013-12-31 08:05:35.000000000 +0100
-+++ gcc-4.9.2/gcc/testsuite/gcc.c-torture/execute/20101011-1.c	2015-03-07 09:57:54.223132741 +0100
-@@ -6,6 +6,9 @@
- #elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) || defined (__POWERPC__) || defined (__ppc)
-   /* On PPC division by zero does not trap.  */
- # define DO_TEST 0
-+#elif defined (__riscv__)
-+  /* On RISC-V division by zero does not trap.  */
-+# define DO_TEST 0
- #elif defined (__SPU__)
-   /* On SPU division by zero does not trap.  */
- # define DO_TEST 0
-diff -urN original-gcc/gcc/testsuite/gcc.dg/20020312-2.c gcc/gcc/testsuite/gcc.dg/20020312-2.c
---- original-gcc/gcc/testsuite/gcc.dg/20020312-2.c	2013-12-31 08:05:35.000000000 +0100
-+++ gcc-4.9.2/gcc/testsuite/gcc.dg/20020312-2.c	2015-03-07 09:57:54.223132741 +0100
-@@ -66,6 +66,8 @@
- # else
- #  define PIC_REG  "30"
- # endif
-+#elif defined(__riscv__)
-+/* No pic register.  */
- #elif defined(__RX__)
- /* No pic register.  */
- #elif defined(__s390__)
-diff -urN original-gcc/gcc/testsuite/gcc.dg/20040813-1.c gcc/gcc/testsuite/gcc.dg/20040813-1.c
---- original-gcc/gcc/testsuite/gcc.dg/20040813-1.c	2013-12-31 08:05:35.000000000 +0100
-+++ gcc-4.9.2/gcc/testsuite/gcc.dg/20040813-1.c	2015-03-07 09:57:54.227132741 +0100
-@@ -2,7 +2,7 @@
- /* Contributed by Devang Patel  <dpatel@apple.com>  */
- 
- /* { dg-do compile } */
--/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* nios2-*-* *-*-vxworks* } { "*" } { "" } } */
-+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* riscv*-*-* tile*-*-* nios2-*-* *-*-vxworks* } { "*" } { "" } } */
- /* { dg-options "-gstabs" } */
- 
- int
-diff -urN original-gcc/gcc/testsuite/gcc.dg/stack-usage-1.c gcc/gcc/testsuite/gcc.dg/stack-usage-1.c
---- original-gcc/gcc/testsuite/gcc.dg/stack-usage-1.c	2013-12-31 08:05:35.000000000 +0100
-+++ gcc-4.9.2/gcc/testsuite/gcc.dg/stack-usage-1.c	2015-03-07 09:57:54.227132741 +0100
-@@ -61,6 +61,8 @@
- #  else
- #    define SIZE 240
- #  endif
-+#elif defined (__riscv__)
-+#  define SIZE 240
- #elif defined (__AVR__)
- #  define SIZE 254
- #elif defined (__s390x__)
-diff -urN original-gcc/libatomic/cas_n.c gcc/libatomic/cas_n.c
---- original-gcc/libatomic/cas_n.c	2014-02-20 18:43:53.000000000 +0100
-+++ gcc-4.9.2/libatomic/cas_n.c	2015-03-07 09:57:54.227132741 +0100
-@@ -70,7 +70,7 @@
-       mask = -1;
-     }
- 
--  weval = *eptr << shift;
-+  weval = (UWORD)*eptr << shift;
-   wnewval = (UWORD)newval << shift;
-   woldval = __atomic_load_n (wptr, __ATOMIC_RELAXED);
-   do
-diff -urN original-gcc/libatomic/configure.tgt gcc/libatomic/configure.tgt
---- original-gcc/libatomic/configure.tgt	2014-01-02 23:24:30.000000000 +0100
-+++ gcc-4.9.2/libatomic/configure.tgt	2015-03-07 09:57:54.227132741 +0100
-@@ -29,6 +29,7 @@
- case "${target_cpu}" in
-   alpha*)		ARCH=alpha ;;
-   rs6000 | powerpc*)	ARCH=powerpc ;;
-+  riscv*)		ARCH=riscv ;;
-   sh*)			ARCH=sh ;;
- 
-   arm*)
-diff -urN original-gcc/libatomic/fop_n.c gcc/libatomic/fop_n.c
---- original-gcc/libatomic/fop_n.c	2014-01-02 23:24:30.000000000 +0100
-+++ gcc-4.9.2/libatomic/fop_n.c	2015-03-07 09:57:54.231132741 +0100
-@@ -1,4 +1,4 @@
--/* Copyright (C) 2012-2014 Free Software Foundation, Inc.
-+/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
-    Contributed by Richard Henderson <rth@redhat.com>.
- 
-    This file is part of the GNU Atomic Library (libatomic).
-@@ -112,9 +112,9 @@
- 
-   pre_barrier (smodel);
- 
--  wptr = (UWORD *)mptr;
--  shift = 0;
--  mask = -1;
-+  wptr = (UWORD *)((uintptr_t)mptr & -WORDSIZE);
-+  shift = (((uintptr_t)mptr % WORDSIZE) * CHAR_BIT) ^ SIZE(INVERT_MASK);
-+  mask = SIZE(MASK) << shift;
- 
-   wopval = (UWORD)opval << shift;
-   woldval = __atomic_load_n (wptr, __ATOMIC_RELAXED);
-@@ -136,9 +136,9 @@
- 
-   pre_barrier (smodel);
- 
--  wptr = (UWORD *)mptr;
--  shift = 0;
--  mask = -1;
-+  wptr = (UWORD *)((uintptr_t)mptr & -WORDSIZE);
-+  shift = (((uintptr_t)mptr % WORDSIZE) * CHAR_BIT) ^ SIZE(INVERT_MASK);
-+  mask = SIZE(MASK) << shift;
- 
-   wopval = (UWORD)opval << shift;
-   woldval = __atomic_load_n (wptr, __ATOMIC_RELAXED);
-diff -urN original-gcc/libcpp/configure gcc/libcpp/configure
---- original-gcc/libcpp/configure	2014-10-30 09:28:58.000000000 +0100
-+++ gcc-4.9.2/libcpp/configure	2015-03-07 09:57:54.231132741 +0100
-@@ -7163,6 +7163,7 @@
- 	mips*-*-* | \
- 	mmix-*-* | \
- 	powerpc*-*-* | \
-+	riscv*-*-* | \
- 	rs6000*-*-* | \
- 	s390*-*-* | \
- 	sparc*-*-* | \
-diff -urN original-gcc/libcpp/configure.ac gcc/libcpp/configure.ac
---- original-gcc/libcpp/configure.ac	2014-02-24 16:08:00.000000000 +0100
-+++ gcc-4.9.2/libcpp/configure.ac	2015-03-07 09:57:54.235132741 +0100
-@@ -192,6 +192,7 @@
- 	mips*-*-* | \
- 	mmix-*-* | \
- 	powerpc*-*-* | \
-+	riscv*-*-* | \
- 	rs6000*-*-* | \
- 	s390*-*-* | \
- 	sparc*-*-* | \
-diff -urN original-gcc/libgcc/config/riscv/crti.S gcc/libgcc/config/riscv/crti.S
---- original-gcc/libgcc/config/riscv/crti.S	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/crti.S	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/libgcc/config/riscv/crti.S gcc-5.2.0/libgcc/config/riscv/crti.S
+--- empty/libgcc/config/riscv/crti.S	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/crti.S	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1 @@
 +/* crti.S is empty because .init_array/.fini_array are used exclusively. */
-diff -urN original-gcc/libgcc/config/riscv/crtn.S gcc/libgcc/config/riscv/crtn.S
---- original-gcc/libgcc/config/riscv/crtn.S	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/crtn.S	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/libgcc/config/riscv/crtn.S gcc-5.2.0/libgcc/config/riscv/crtn.S
+--- empty/libgcc/config/riscv/crtn.S	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/crtn.S	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1 @@
 +/* crtn.S is empty because .init_array/.fini_array are used exclusively. */
-diff -urN original-gcc/libgcc/config/riscv/div.S gcc/libgcc/config/riscv/div.S
---- original-gcc/libgcc/config/riscv/div.S	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/div.S	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/libgcc/config/riscv/div.S gcc-5.2.0/libgcc/config/riscv/div.S
+--- empty/libgcc/config/riscv/div.S	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/div.S	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,121 @@
 +  .text
 +  .align 2
@@ -10891,9 +11246,9 @@
 +  bne   a0, t0, __divdi3
 +  ret
 +#endif
-diff -urN original-gcc/libgcc/config/riscv/mul.S gcc/libgcc/config/riscv/mul.S
---- original-gcc/libgcc/config/riscv/mul.S	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/mul.S	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/libgcc/config/riscv/mul.S gcc-5.2.0/libgcc/config/riscv/mul.S
+--- empty/libgcc/config/riscv/mul.S	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/mul.S	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,21 @@
 +  .text
 +  .align 2
@@ -10916,9 +11271,9 @@
 +  slli   a2, a2, 1
 +  bnez   a1, .L1
 +  ret
-diff -urN original-gcc/libgcc/config/riscv/riscv-fp.c gcc/libgcc/config/riscv/riscv-fp.c
---- original-gcc/libgcc/config/riscv/riscv-fp.c	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/riscv-fp.c	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/libgcc/config/riscv/riscv-fp.c gcc-5.2.0/libgcc/config/riscv/riscv-fp.c
+--- empty/libgcc/config/riscv/riscv-fp.c	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/riscv-fp.c	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,178 @@
 +/* Functions needed for soft-float on riscv-linux.  Based on
 +   rs6000/ppc64-fp.c with TF types removed.
@@ -11098,46 +11453,264 @@
 +}
 +
 +#endif
-diff -urN original-gcc/libgcc/config/riscv/t-dpbit gcc/libgcc/config/riscv/t-dpbit
---- original-gcc/libgcc/config/riscv/t-dpbit	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/t-dpbit	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/libgcc/config/riscv/save-restore.S gcc-5.2.0/libgcc/config/riscv/save-restore.S
+--- empty/libgcc/config/riscv/save-restore.S	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/save-restore.S	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,220 @@
++  .text
++
++  .globl __riscv_save_12
++  .globl __riscv_save_11
++  .globl __riscv_save_10
++  .globl __riscv_save_9
++  .globl __riscv_save_8
++  .globl __riscv_save_7
++  .globl __riscv_save_6
++  .globl __riscv_save_5
++  .globl __riscv_save_4
++  .globl __riscv_save_3
++  .globl __riscv_save_2
++  .globl __riscv_save_1
++  .globl __riscv_save_0
++
++  .globl __riscv_restore_12
++  .globl __riscv_restore_11
++  .globl __riscv_restore_10
++  .globl __riscv_restore_9
++  .globl __riscv_restore_8
++  .globl __riscv_restore_7
++  .globl __riscv_restore_6
++  .globl __riscv_restore_5
++  .globl __riscv_restore_4
++  .globl __riscv_restore_3
++  .globl __riscv_restore_2
++  .globl __riscv_restore_1
++  .globl __riscv_restore_0
++
++#ifdef __riscv64
++
++__riscv_save_12:
++  addi sp, sp, -112
++  li t1, 0
++  sd s11, 8(sp)
++  j .Ls10
++
++__riscv_save_11:
++__riscv_save_10:
++  addi sp, sp, -112
++  li t1, -16
++.Ls10:
++  sd s10, 16(sp)
++  sd s9, 24(sp)
++  j .Ls8
++
++__riscv_save_9:
++__riscv_save_8:
++  addi sp, sp, -112
++  li t1, -32
++.Ls8:
++  sd s8, 32(sp)
++  sd s7, 40(sp)
++  j .Ls6
++
++__riscv_save_7:
++__riscv_save_6:
++  addi sp, sp, -112
++  li t1, -48
++.Ls6:
++  sd s6, 48(sp)
++  sd s5, 56(sp)
++  j .Ls4
++
++__riscv_save_5:
++__riscv_save_4:
++  addi sp, sp, -112
++  li t1, -64
++.Ls4:
++  sd s4, 64(sp)
++  sd s3, 72(sp)
++  j .Ls2
++
++__riscv_save_3:
++__riscv_save_2:
++  addi sp, sp, -112
++  li t1, -80
++.Ls2:
++  sd s2, 80(sp)
++  sd s1, 88(sp)
++  sd s0, 96(sp)
++  sd ra, 104(sp)
++  sub sp, sp, t1
++  jr t0
++
++__riscv_save_1:
++__riscv_save_0:
++  addi sp, sp, -16
++  sd s0, 0(sp)
++  sd ra, 8(sp)
++  jr t0
++
++__riscv_restore_12:
++  ld s11, 8(sp)
++  addi sp, sp, 16
++
++__riscv_restore_11:
++__riscv_restore_10:
++  ld s10, 0(sp)
++  ld s9, 8(sp)
++  addi sp, sp, 16
++
++__riscv_restore_9:
++__riscv_restore_8:
++  ld s8, 0(sp)
++  ld s7, 8(sp)
++  addi sp, sp, 16
++
++__riscv_restore_7:
++__riscv_restore_6:
++  ld s6, 0(sp)
++  ld s5, 8(sp)
++  addi sp, sp, 16
++
++__riscv_restore_5:
++__riscv_restore_4:
++  ld s4, 0(sp)
++  ld s3, 8(sp)
++  addi sp, sp, 16
++
++__riscv_restore_3:
++__riscv_restore_2:
++  ld s2, 0(sp)
++  ld s1, 8(sp)
++  addi sp, sp, 16
++
++__riscv_restore_1:
++__riscv_restore_0:
++  ld s0, 0(sp)
++  ld ra, 8(sp)
++  addi sp, sp, 16
++  ret
++
++#else
++
++__riscv_save_12:
++  addi sp, sp, -64
++  li t1, 0
++  sw s11, 12(sp)
++  j .Ls10
++
++__riscv_save_11:
++__riscv_save_10:
++__riscv_save_9:
++__riscv_save_8:
++  addi sp, sp, -64
++  li t1, -16
++.Ls10:
++  sw s10, 16(sp)
++  sw s9, 20(sp)
++  sw s8, 24(sp)
++  sw s7, 28(sp)
++  j .Ls6
++
++__riscv_save_7:
++__riscv_save_6:
++__riscv_save_5:
++__riscv_save_4:
++  addi sp, sp, -64
++  li t1, -32
++.Ls6:
++  sw s6, 32(sp)
++  sw s5, 36(sp)
++  sw s4, 40(sp)
++  sw s3, 44(sp)
++  sw s2, 48(sp)
++  sw s1, 52(sp)
++  sw s0, 56(sp)
++  sw ra, 60(sp)
++  sub sp, sp, t1
++  jr t0
++
++__riscv_save_3:
++__riscv_save_2:
++__riscv_save_1:
++__riscv_save_0:
++  addi sp, sp, -16
++  sw s2, 0(sp)
++  sw s1, 4(sp)
++  sw s0, 8(sp)
++  sw ra, 12(sp)
++  jr t0
++
++__riscv_restore_12:
++  lw s11, 12(sp)
++  addi sp, sp, 16
++
++__riscv_restore_11:
++__riscv_restore_10:
++__riscv_restore_9:
++__riscv_restore_8:
++  lw s10, 0(sp)
++  lw s9, 4(sp)
++  lw s8, 8(sp)
++  lw s7, 12(sp)
++  addi sp, sp, 16
++
++__riscv_restore_7:
++__riscv_restore_6:
++__riscv_restore_5:
++__riscv_restore_4:
++  lw s6, 0(sp)
++  lw s5, 4(sp)
++  lw s4, 8(sp)
++  lw s3, 12(sp)
++  addi sp, sp, 16
++
++__riscv_restore_3:
++__riscv_restore_2:
++__riscv_restore_1:
++__riscv_restore_0:
++  lw s2, 0(sp)
++  lw s1, 4(sp)
++  lw s0, 8(sp)
++  lw ra, 12(sp)
++  addi sp, sp, 16
++  ret
++
++#endif
+diff -urN empty/libgcc/config/riscv/t-dpbit gcc-5.2.0/libgcc/config/riscv/t-dpbit
+--- empty/libgcc/config/riscv/t-dpbit	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/t-dpbit	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,4 @@
 +LIB2ADD += dp-bit.c
 +
 +dp-bit.c: $(srcdir)/fp-bit.c
 +	cat $(srcdir)/fp-bit.c > dp-bit.c
-diff -urN original-gcc/libgcc/config/riscv/t-elf gcc/libgcc/config/riscv/t-elf
---- original-gcc/libgcc/config/riscv/t-elf	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/t-elf	2015-03-07 09:51:45.667139025 +0100
-@@ -0,0 +1,3 @@
+diff -urN empty/libgcc/config/riscv/t-elf gcc-5.2.0/libgcc/config/riscv/t-elf
+--- empty/libgcc/config/riscv/t-elf	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/t-elf	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,4 @@
 +LIB2ADD += $(srcdir)/config/riscv/riscv-fp.c \
++	   $(srcdir)/config/riscv/save-restore.S \
 +	   $(srcdir)/config/riscv/mul.S \
 +	   $(srcdir)/config/riscv/div.S
-diff -urN original-gcc/libgcc/config/riscv/t-fpbit gcc/libgcc/config/riscv/t-fpbit
---- original-gcc/libgcc/config/riscv/t-fpbit	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/t-fpbit	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/libgcc/config/riscv/t-elf32 gcc-5.2.0/libgcc/config/riscv/t-elf32
+--- empty/libgcc/config/riscv/t-elf32	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/t-elf32	2015-07-17 22:36:52.319705931 +0200
+@@ -0,0 +1,2 @@
++HOST_LIBGCC2_CFLAGS += -m32
++CRTSTUFF_CFLAGS += -m32
+diff -urN empty/libgcc/config/riscv/t-fpbit gcc-5.2.0/libgcc/config/riscv/t-fpbit
+--- empty/libgcc/config/riscv/t-fpbit	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/t-fpbit	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,5 @@
 +LIB2ADD += fp-bit.c
 +
 +fp-bit.c: $(srcdir)/fp-bit.c
 +	echo '#define FLOAT' > fp-bit.c
 +	cat $(srcdir)/fp-bit.c >> fp-bit.c
-diff -urN original-gcc/libgcc/config/riscv/t-linux gcc/libgcc/config/riscv/t-linux
---- original-gcc/libgcc/config/riscv/t-linux	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/t-linux	2015-03-07 09:51:45.667139025 +0100
-@@ -0,0 +1,3 @@
-+LIB2ADD += $(srcdir)/config/riscv/riscv-fp.c \
-+	   $(srcdir)/config/riscv/mul.S \
-+	   $(srcdir)/config/riscv/div.S
-diff -urN original-gcc/libgcc/config/riscv/t-linux32 gcc/libgcc/config/riscv/t-linux32
---- original-gcc/libgcc/config/riscv/t-linux32	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/t-linux32	2015-03-07 09:51:45.667139025 +0100
-@@ -0,0 +1,2 @@
-+HOST_LIBGCC2_CFLAGS += -m32
-+CRTSTUFF_CFLAGS += -m32
-diff -urN original-gcc/libgcc/config/riscv/t-tpbit gcc/libgcc/config/riscv/t-tpbit
---- original-gcc/libgcc/config/riscv/t-tpbit	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-4.9.2/libgcc/config/riscv/t-tpbit	2015-03-07 09:51:45.667139025 +0100
+diff -urN empty/libgcc/config/riscv/t-tpbit gcc-5.2.0/libgcc/config/riscv/t-tpbit
+--- empty/libgcc/config/riscv/t-tpbit	1970-01-01 01:00:00.000000000 +0100
++++ gcc-5.2.0/libgcc/config/riscv/t-tpbit	2015-07-17 22:36:52.319705931 +0200
 @@ -0,0 +1,10 @@
 +LIB2ADD += tp-bit.c
 +
@@ -11149,148 +11722,3 @@
 +	echo '# define TFLOAT' >> tp-bit.c
 +	cat $(srcdir)/fp-bit.c >> tp-bit.c
 +	echo '#endif' >> tp-bit.c
-diff -urN original-gcc/libgcc/config.host gcc/libgcc/config.host
---- original-gcc/libgcc/config.host	2014-03-27 16:40:31.000000000 +0100
-+++ gcc-4.9.2/libgcc/config.host	2015-03-07 09:57:54.235132741 +0100
-@@ -167,6 +167,9 @@
- 	;;
- rs6000*-*-*)
- 	;;
-+riscv*)
-+	cpu_type=riscv
-+	;;
- score*-*-*)
- 	cpu_type=score
- 	;;
-@@ -1002,6 +1005,18 @@
- 	tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-crtstuff t-crtstuff-pic t-fdpbit"
- 	extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o"
- 	;;
-+riscv32*-*-linux*)
-+	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-tpbit riscv/t-linux riscv/t-linux32"
-+	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o crtendS.o crtbeginT.o"
-+	;;
-+riscv*-*-linux*)
-+	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-tpbit riscv/t-linux"
-+	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o crtendS.o crtbeginT.o"
-+	;;
-+riscv*-*-*)
-+	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-elf"
-+	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
-+	;;
- rs6000-ibm-aix4.[3456789]* | powerpc-ibm-aix4.[3456789]*)
- 	md_unwind_header=rs6000/aix-unwind.h
- 	tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-slibgcc-aix rs6000/t-ibm-ldouble"
-diff -urN original-gcc/libsanitizer/asan/asan_linux.cc gcc/libsanitizer/asan/asan_linux.cc
---- original-gcc/libsanitizer/asan/asan_linux.cc	2013-12-05 10:18:38.000000000 +0100
-+++ gcc-4.9.2/libsanitizer/asan/asan_linux.cc	2015-03-07 09:57:54.235132741 +0100
-@@ -98,6 +98,11 @@
-   *pc = ucontext->uc_mcontext.gregs[31];
-   *bp = ucontext->uc_mcontext.gregs[30];
-   *sp = ucontext->uc_mcontext.gregs[29];
-+# elif defined(__riscv__)
-+  ucontext_t *ucontext = (ucontext_t*)context;
-+  *pc = ucontext->uc_mcontext.gregs[REG_PC];
-+  *bp = ucontext->uc_mcontext.gregs[REG_S0];
-+  *sp = ucontext->uc_mcontext.gregs[REG_SP];
- #else
- # error "Unsupported arch"
- #endif
-diff -urN original-gcc/libsanitizer/sanitizer_common/sanitizer_linux.cc gcc/libsanitizer/sanitizer_common/sanitizer_linux.cc
---- original-gcc/libsanitizer/sanitizer_common/sanitizer_linux.cc	2013-12-05 10:18:38.000000000 +0100
-+++ gcc-4.9.2/libsanitizer/sanitizer_common/sanitizer_linux.cc	2015-03-07 09:57:54.239132741 +0100
-@@ -93,11 +93,11 @@
- }
- 
- uptr internal_open(const char *filename, int flags) {
--  return internal_syscall(__NR_open, (uptr)filename, flags);
-+  return internal_syscall(__NR_openat, AT_FDCWD, (uptr)filename, flags);
- }
- 
- uptr internal_open(const char *filename, int flags, u32 mode) {
--  return internal_syscall(__NR_open, (uptr)filename, flags, mode);
-+  return internal_syscall(__NR_openat, AT_FDCWD, (uptr)filename, flags, mode);
- }
- 
- uptr OpenFile(const char *filename, bool write) {
-@@ -139,7 +139,7 @@
- 
- uptr internal_stat(const char *path, void *buf) {
- #if SANITIZER_LINUX_USES_64BIT_SYSCALLS
--  return internal_syscall(__NR_stat, (uptr)path, (uptr)buf);
-+  return internal_syscall(__NR_newfstatat, AT_FDCWD, (uptr)path, (uptr)buf, 0);
- #else
-   struct stat64 buf64;
-   int res = internal_syscall(__NR_stat64, path, &buf64);
-@@ -150,7 +150,7 @@
- 
- uptr internal_lstat(const char *path, void *buf) {
- #if SANITIZER_LINUX_USES_64BIT_SYSCALLS
--  return internal_syscall(__NR_lstat, (uptr)path, (uptr)buf);
-+  return internal_syscall(__NR_newfstatat, AT_FDCWD, (uptr)path, (uptr)buf, AT_SYMLINK_NOFOLLOW);
- #else
-   struct stat64 buf64;
-   int res = internal_syscall(__NR_lstat64, path, &buf64);
-@@ -178,15 +178,15 @@
- }
- 
- uptr internal_dup2(int oldfd, int newfd) {
--  return internal_syscall(__NR_dup2, oldfd, newfd);
-+  return internal_syscall(__NR_dup3, oldfd, newfd, 0);
- }
- 
- uptr internal_readlink(const char *path, char *buf, uptr bufsize) {
--  return internal_syscall(__NR_readlink, (uptr)path, (uptr)buf, bufsize);
-+  return internal_syscall(__NR_readlinkat, AT_FDCWD, (uptr)path, (uptr)buf, bufsize);
- }
- 
- uptr internal_unlink(const char *path) {
--  return internal_syscall(__NR_unlink, (uptr)path);
-+  return internal_syscall(__NR_unlinkat, AT_FDCWD, (uptr)path);
- }
- 
- uptr internal_sched_yield() {
-@@ -588,7 +588,7 @@
- }
- 
- uptr internal_getdents(fd_t fd, struct linux_dirent *dirp, unsigned int count) {
--  return internal_syscall(__NR_getdents, fd, (uptr)dirp, count);
-+  return internal_syscall(__NR_getdents64, fd, (uptr)dirp, count);
- }
- 
- uptr internal_lseek(fd_t fd, OFF_T offset, int whence) {
-diff -urN original-gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
---- original-gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc	2014-10-14 21:26:42.000000000 +0200
-+++ gcc-4.9.2/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc	2015-03-07 09:57:54.235132741 +0100
-@@ -63,7 +63,7 @@
-   unsigned struct_statfs64_sz = sizeof(struct statfs64);
- }  // namespace __sanitizer
- 
--#if !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__sparc__)
-+#if !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__sparc__) && !defined(__riscv__)
- COMPILER_CHECK(struct___old_kernel_stat_sz == sizeof(struct __old_kernel_stat));
- #endif
- 
-diff -urN original-gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
---- original-gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	2014-10-14 21:26:42.000000000 +0200
-+++ gcc-4.9.2/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	2015-03-07 09:57:54.239132741 +0100
-@@ -67,6 +67,10 @@
-   const unsigned struct___old_kernel_stat_sz = 0;
-   const unsigned struct_kernel_stat_sz = 144;
-   const unsigned struct_kernel_stat64_sz = 104;
-+#elif defined(__riscv__)
-+  const unsigned struct___old_kernel_stat_sz = 0;
-+  const unsigned struct_kernel_stat_sz = 128;
-+  const unsigned struct_kernel_stat64_sz = 128;
- #elif defined(__sparc__) && defined(__arch64__)
-   const unsigned struct___old_kernel_stat_sz = 0;
-   const unsigned struct_kernel_stat_sz = 104;
-@@ -367,7 +371,7 @@
-   typedef long __sanitizer___kernel_off_t;
- #endif
- 
--#if defined(__powerpc__)
-+#if defined(__powerpc__) || defined(__riscv__)
-   typedef unsigned int __sanitizer___kernel_old_uid_t;
-   typedef unsigned int __sanitizer___kernel_old_gid_t;
- #else
diff --git a/util/crossgcc/sum/gcc-4.9.2.tar.bz2.cksum b/util/crossgcc/sum/gcc-4.9.2.tar.bz2.cksum
deleted file mode 100644
index b1d8c46..0000000
--- a/util/crossgcc/sum/gcc-4.9.2.tar.bz2.cksum
+++ /dev/null
@@ -1 +0,0 @@
-79dbcb09f44232822460d80b033c962c0237c6d8  tarballs/gcc-4.9.2.tar.bz2
diff --git a/util/crossgcc/sum/gcc-5.2.0.tar.bz2.cksum b/util/crossgcc/sum/gcc-5.2.0.tar.bz2.cksum
new file mode 100644
index 0000000..2bc4f22
--- /dev/null
+++ b/util/crossgcc/sum/gcc-5.2.0.tar.bz2.cksum
@@ -0,0 +1 @@
+fe3f5390949d47054b613edc36c557eb1d51c18e  tarballs/gcc-5.2.0.tar.bz2