commit af27ac26b34216f4a188ee1738825177d469cf48
author Subrata Banik <subratabanik@google.com> Fri Feb 18 00:44:15 2022 +0530
committer Felix Held <felix-coreboot@felixheld.de> Tue Mar 29 13:56:04 2022 +0000
tree cf6f519b0f7379aaa6b6b058d400d951496b9c1e
parent d58580e0032f855b290815ed412a9d77c66f759e

soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code

This patch moves `pmc_clear_pmcon_sts` function into common code and
remove SoC specific instances.

Accessing PMC GEN_PMCON_A register differs between different Intel
chipsets. Typically, there are two possible ways to perform GEN_PMCON_A
register programming (like `pmc_clear_pmcon_sts()`) as:
1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration
   register.
2. Using MMIO access when GEN_PMCON_A is a memory mapped register.

SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to
perform GEN_PMCON_A register programming using PMC MMIO.

BUG=b:211954778
TEST=Able to build brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeff Daly <jeffd@silicom-usa.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/cannonlake/Kconfig

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 9517cee..0a61381 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -105,6 +105,7 @@
 	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_PCH_BASE
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER

src/soc/intel/cannonlake/include/soc/pm.h

diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h
index 59b2ba0..d345e07 100644
--- a/src/soc/intel/cannonlake/include/soc/pm.h
+++ b/src/soc/intel/cannonlake/include/soc/pm.h
@@ -155,9 +155,6 @@
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 /* STM Support */
 uint16_t get_pmbase(void);
 

src/soc/intel/cannonlake/pmutil.c

diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index a79d262..38a0ce7 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -127,20 +127,6 @@
 	write8(addr, disb_val);
 }
 
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	uint8_t *addr;
-	addr = pmc_mmio_regs();
-
-	reg_val = read32(addr + GEN_PMCON_A);
-	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit */
-	reg_val &= ~(MS4V);
-
-	write32((addr + GEN_PMCON_A), reg_val);
-}
-
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE