soc/amd/*/northbridge,root_complex: add comment about PCI BARs
Add a comment to point out that the read_resources functions aren't
missing a pci_dev_read_resources call that would add the resources for
the BARs of the PC device.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index dabfa78..9cb668e 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -114,6 +114,9 @@
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
+ /* The root complex has no PCI BARs implemented, so there's no need to call
+ pci_dev_read_resources for it */
+
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c
index a3a3d4b..d5fd10d 100644
--- a/src/soc/amd/picasso/root_complex.c
+++ b/src/soc/amd/picasso/root_complex.c
@@ -114,6 +114,9 @@
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
+ /* The root complex has no PCI BARs implemented, so there's no need to call
+ pci_dev_read_resources for it */
+
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c
index 2a3ed6f..ae1b3b9 100644
--- a/src/soc/amd/sabrina/root_complex.c
+++ b/src/soc/amd/sabrina/root_complex.c
@@ -116,6 +116,9 @@
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
+ /* The root complex has no PCI BARs implemented, so there's no need to call
+ pci_dev_read_resources for it */
+
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 0384e00..85ef19e 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -60,6 +60,9 @@
unsigned int idx = 0;
struct resource *res;
+ /* The northbridge has no PCI BARs implemented, so there's no need to call
+ pci_dev_read_resources for it */
+
/*
* This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in