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review.coreboot.org / coreboot / aea60bcd43d0b57313ed4ec20ff28f6877095e98
commitaea60bcd43d0b57313ed4ec20ff28f6877095e98[log] [tgz]
authorKarthikeyan Ramasubramanian <kramasub@google.com>Tue Oct 04 10:08:15 2022 -0600
committerKarthik Ramasubramanian <kramasub@google.com>Fri Oct 07 19:17:28 2022 +0000
tree920903f0ff91a895d071af78283af3374b32d1ee
parent93781523a5291bed1faf9f2d9cc5965f22f6c605 [diff]
mb/google/skyrim: Override SPI flash bus speed

Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz starting the board version where required schematics update is done.

BUG=b:245949155
TEST=Build and boot to OS in Skyrim with 100 MHz SPI bus speed. Perform
warm and cold reboot cycles for 100 iterations each. Observe that the
boot time improved by ~115 ms compared to 66 MHz SPI flash bus speed.
At 66 MHz:
 508:finished loading body                        538,319 (83,806)
  11:start of bootblock                         1,196,809 (624,777)
  14:finished loading romstage                  1,236,905 (39,163)
 970:loading FSP-M                              1,237,056 (37)
  15:starting LZMA decompress (ignore for x86)  1,237,073 (17)
  16:finished LZMA decompress (ignore for x86)  1,358,937 (121,864)
   8:starting to load ramstage                  2,010,304 (0)
  15:starting LZMA decompress (ignore for x86)  2,010,312 (8)
  16:finished LZMA decompress (ignore for x86)  2,067,181 (56,869)
 971:loading FSP-S                              2,078,232 (7,999)
  17:starting LZ4 decompress (ignore for x86)   2,078,253 (21)
  18:finished LZ4 decompress (ignore for x86)   2,084,297 (6,044)
  90:starting to load payload                   2,316,933 (5)
  15:starting LZMA decompress (ignore for x86)  2,316,947 (14)
  16:finished LZMA decompress (ignore for x86)  2,339,819 (22,872)
Total Time: 2,464,338

At 100 MHz:
 508:finished loading body                        515,118 (59,364)
  11:start of bootblock                         1,115,043 (566,110)
  14:finished loading romstage                  1,146,713 (29,697)
 970:loading FSP-M                              1,146,865 (38)
  15:starting LZMA decompress (ignore for x86)  1,146,881 (16)
  16:finished LZMA decompress (ignore for x86)  1,249,351 (102,470)
   8:starting to load ramstage                  1,900,568 (1)
  15:starting LZMA decompress (ignore for x86)  1,900,576 (8)
  16:finished LZMA decompress (ignore for x86)  1,956,337 (55,761)
 971:loading FSP-S                              1,967,357 (7,930)
  17:starting LZ4 decompress (ignore for x86)   1,967,377 (20)
  18:finished LZ4 decompress (ignore for x86)   1,972,925 (5,548)
  90:starting to load payload                   2,205,300 (6)
  15:starting LZMA decompress (ignore for x86)  2,205,313 (13)
  16:finished LZMA decompress (ignore for x86)  2,227,087 (21,774)
Total Time: 2,349,804

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5e8db22151fbc2db1f9e81b3644338348160736d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
3 files changed
tree: 920903f0ff91a895d071af78283af3374b32d1ee
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. spd/
  7. src/
  8. tests/
  9. util/
  10. .checkpatch.conf
  11. .clang-format
  12. .editorconfig
  13. .gitignore
  14. .gitmodules
  15. .gitreview
  16. .mailmap
  17. AUTHORS
  18. COPYING
  19. gnat.adc
  20. MAINTAINERS
  21. Makefile
  22. Makefile.inc
  23. README.md
  24. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.