mb/intel/shadowmountain: Add the ramstage code
This patch includes the ramstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
index 29e6184..80a4264 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
@@ -21,15 +21,16 @@
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
/* B11 : PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
-
/* C0 : EN_PP3300_WLAN */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C3 : H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
-
/* D10 : EN_PP3300_WWAN */
PAD_CFG_GPO(GPP_D10, 1, DEEP),
-
+ /* D15 : MEM_STRAP_3 */
+ PAD_NC(GPP_D15, NONE),
+ /* D16 : EN_PP3300_SD */
+ PAD_NC(GPP_D16, UP_20K),
/* E10 : PCH_GSPI0_H1_TPM_CS_L */
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
/* E11 : PCH_GSPI0_H1_TPM_CLK */
@@ -38,7 +39,6 @@
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
/* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
-
/* F14 : WLAN_PERST_L */
PAD_CFG_GPO(GPP_F14, 1, DEEP),
/* F20 : WWAN_RST_ODL