soc/intel/meteorlake: Disable L1 substates for PCIe compliance test mode
Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.
This patch is backported from
commit 8c46232005767ecbdebb7290f15cacf2756c9586 (soc/intel/alderlake:
Disable L1 substates for PCIe compliance test mode).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I490a3e8158472fdd3bbc1aec74b2658b0fab56e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71169
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index a624025..ad6db10 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -86,7 +86,9 @@
*/
static int get_l1_substate_control(enum L1_substates_control ctl)
{
- if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
+ if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
+ ctl = L1_SS_DISABLED;
+ else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
ctl = L1_SS_L1_2;
return ctl - 1;
}