timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 9e863c3..9628571 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -12,7 +12,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
post_code(0x40);
diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c
index b932458..f203377 100644
--- a/src/soc/amd/common/block/apob/apob_cache.c
+++ b/src/soc/amd/common/block/apob/apob_cache.c
@@ -171,7 +171,7 @@
printk(BIOS_DEBUG, "APOB valid copy is already in flash\n");
if (!update_needed) {
- timestamp_add_now(TS_AMD_APOB_DONE);
+ timestamp_add_now(TS_AMD_APOB_END);
return;
}
@@ -199,7 +199,7 @@
return;
}
- timestamp_add_now(TS_AMD_APOB_DONE);
+ timestamp_add_now(TS_AMD_APOB_END);
printk(BIOS_INFO, "Updated APOB in flash\n");
}
diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c
index 8ee962b..c5e6cac 100644
--- a/src/soc/amd/common/pi/agesawrapper.c
+++ b/src/soc/amd/common/pi/agesawrapper.c
@@ -102,7 +102,7 @@
timestamp_add_now(TS_AGESA_INIT_RESET_START);
status = amd_dispatch(ResetParams);
- timestamp_add_now(TS_AGESA_INIT_RESET_DONE);
+ timestamp_add_now(TS_AGESA_INIT_RESET_END);
return status;
}
@@ -116,7 +116,7 @@
timestamp_add_now(TS_AGESA_INIT_EARLY_START);
status = amd_dispatch(EarlyParams);
- timestamp_add_now(TS_AGESA_INIT_EARLY_DONE);
+ timestamp_add_now(TS_AGESA_INIT_EARLY_END);
return status;
}
@@ -173,7 +173,7 @@
timestamp_add_now(TS_AGESA_INIT_POST_START);
status = amd_dispatch(PostParams);
- timestamp_add_now(TS_AGESA_INIT_POST_DONE);
+ timestamp_add_now(TS_AGESA_INIT_POST_END);
/*
* AGESA passes back the base and size of UMA. This is the only
@@ -208,7 +208,7 @@
timestamp_add_now(TS_AGESA_INIT_ENV_START);
status = amd_dispatch(EnvParams);
- timestamp_add_now(TS_AGESA_INIT_ENV_DONE);
+ timestamp_add_now(TS_AGESA_INIT_ENV_END);
return status;
}
@@ -251,7 +251,7 @@
timestamp_add_now(TS_AGESA_INIT_MID_START);
status = amd_dispatch(MidParams);
- timestamp_add_now(TS_AGESA_INIT_MID_DONE);
+ timestamp_add_now(TS_AGESA_INIT_MID_END);
return status;
}
@@ -268,7 +268,7 @@
timestamp_add_now(TS_AGESA_INIT_LATE_START);
Status = amd_dispatch(LateParams);
- timestamp_add_now(TS_AGESA_INIT_LATE_DONE);
+ timestamp_add_now(TS_AGESA_INIT_LATE_END);
DmiTable = LateParams->DmiTable;
AcpiPstate = LateParams->AcpiPState;
@@ -295,7 +295,7 @@
timestamp_add_now(TS_AGESA_INIT_RTB_START);
Status = amd_dispatch(RtbParams);
- timestamp_add_now(TS_AGESA_INIT_RTB_DONE);
+ timestamp_add_now(TS_AGESA_INIT_RTB_END);
if (Status != AGESA_SUCCESS)
return Status;
@@ -314,7 +314,7 @@
timestamp_add_now(TS_AGESA_INIT_RESUME_START);
status = amd_dispatch(InitResumeParams);
- timestamp_add_now(TS_AGESA_INIT_RESUME_DONE);
+ timestamp_add_now(TS_AGESA_INIT_RESUME_END);
return status;
}
@@ -329,7 +329,7 @@
timestamp_add_now(TS_AGESA_S3_LATE_START);
Status = amd_dispatch(S3LateParams);
- timestamp_add_now(TS_AGESA_S3_LATE_DONE);
+ timestamp_add_now(TS_AGESA_S3_LATE_END);
return Status;
}
@@ -342,7 +342,7 @@
timestamp_add_now(TS_AGESA_S3_FINAL_START);
Status = amd_dispatch(S3FinalParams);
- timestamp_add_now(TS_AGESA_S3_FINAL_DONE);
+ timestamp_add_now(TS_AGESA_S3_FINAL_END);
return Status;
}
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 1972410..359eacf 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -13,7 +13,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
post_code(0x40);
diff --git a/src/soc/amd/sabrina/romstage.c b/src/soc/amd/sabrina/romstage.c
index 91f80ef..49ca223 100644
--- a/src/soc/amd/sabrina/romstage.c
+++ b/src/soc/amd/sabrina/romstage.c
@@ -14,7 +14,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
post_code(0x40);
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index ae83d49..9720d9e 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -137,9 +137,9 @@
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) {
- timestamp_add_now(TS_START_CSE_FW_SYNC);
+ timestamp_add_now(TS_CSE_FW_SYNC_START);
cse_fw_sync();
- timestamp_add_now(TS_END_CSE_FW_SYNC);
+ timestamp_add_now(TS_CSE_FW_SYNC_END);
}
/*
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index dbf4afc..74238e2 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -101,7 +101,7 @@
memset(&mp, 0, sizeof(mp));
mainboard_fill_mrc_params(&mp);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
ps = fill_power_state();
prev_sleep_state = chipset_prev_sleep_state(ps);
@@ -115,7 +115,7 @@
/* Initialize RAM */
raminit(&mp, prev_sleep_state);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
romstage_handoff_init(s3resume);
}
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index 28b3f37..95073d3 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -188,14 +188,14 @@
post_code(0x32);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
pei_data.boot_mode = power_state->prev_sleep_state;
/* Initialize RAM */
sdram_initialize(&pei_data);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
int cbmem_was_initted = !cbmem_recovery(s3resume);
if (s3resume && !cbmem_was_initted) {
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c
index 3a08a73..af6abb8 100644
--- a/src/soc/intel/common/block/cse/cse_eop.c
+++ b/src/soc/intel/common/block/cse/cse_eop.c
@@ -192,9 +192,9 @@
set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
- timestamp_add_now(TS_ME_BEFORE_END_OF_POST);
+ timestamp_add_now(TS_ME_END_OF_POST_START);
handle_cse_eop_result(cse_send_eop());
- timestamp_add_now(TS_ME_AFTER_END_OF_POST);
+ timestamp_add_now(TS_ME_END_OF_POST_END);
set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE);