timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/arch/arm64/romstage.c b/src/arch/arm64/romstage.c
index f4b4544..b144f93 100644
--- a/src/arch/arm64/romstage.c
+++ b/src/arch/arm64/romstage.c
@@ -12,7 +12,7 @@
void main(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
console_init();
exception_init();
diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c
index 1df8c44..b07b512 100644
--- a/src/arch/x86/postcar.c
+++ b/src/arch/x86/postcar.c
@@ -30,7 +30,7 @@
if (!cbmem_online())
cbmem_initialize();
- timestamp_add_now(TS_START_POSTCAR);
+ timestamp_add_now(TS_POSTCAR_START);
display_mtrrs();
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 8a5f902..2609fd6 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -192,7 +192,7 @@
load_postcar_cbfs(&prog, pcf);
/* As postcar exist, it's end of romstage here */
- timestamp_add_now(TS_END_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_END);
console_time_report();
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index 492508e..a51b68f 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -19,23 +19,23 @@
} __packed;
enum timestamp_id {
- TS_START_ROMSTAGE = 1,
- TS_BEFORE_INITRAM = 2,
- TS_AFTER_INITRAM = 3,
- TS_END_ROMSTAGE = 4,
- TS_START_VBOOT = 5,
- TS_END_VBOOT = 6,
- TS_START_COPYRAM = 8,
- TS_END_COPYRAM = 9,
- TS_START_RAMSTAGE = 10,
- TS_START_BOOTBLOCK = 11,
- TS_END_BOOTBLOCK = 12,
- TS_START_COPYROM = 13,
- TS_END_COPYROM = 14,
- TS_START_ULZMA = 15,
- TS_END_ULZMA = 16,
- TS_START_ULZ4F = 17,
- TS_END_ULZ4F = 18,
+ TS_ROMSTAGE_START = 1,
+ TS_INITRAM_START = 2,
+ TS_INITRAM_END = 3,
+ TS_ROMSTAGE_END = 4,
+ TS_VBOOT_START = 5,
+ TS_VBOOT_END = 6,
+ TS_COPYRAM_START = 8,
+ TS_COPYRAM_END = 9,
+ TS_RAMSTAGE_START = 10,
+ TS_BOOTBLOCK_START = 11,
+ TS_BOOTBLOCK_END = 12,
+ TS_COPYROM_START = 13,
+ TS_COPYROM_END = 14,
+ TS_ULZMA_START = 15,
+ TS_ULZMA_END = 16,
+ TS_ULZ4F_START = 17,
+ TS_ULZ4F_END = 18,
TS_DEVICE_ENUMERATE = 30,
TS_DEVICE_CONFIGURE = 40,
TS_DEVICE_ENABLE = 50,
@@ -50,8 +50,8 @@
TS_LOAD_PAYLOAD = 90,
TS_ACPI_WAKE_JUMP = 98,
TS_SELFBOOT_JUMP = 99,
- TS_START_POSTCAR = 100,
- TS_END_POSTCAR = 101,
+ TS_POSTCAR_START = 100,
+ TS_POSTCAR_END = 101,
TS_DELAY_START = 110,
TS_DELAY_END = 111,
TS_READ_UCODE_START = 112,
@@ -60,67 +60,67 @@
TS_ELOG_INIT_END = 115,
/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
- TS_START_COPYVER = 501,
- TS_END_COPYVER = 502,
- TS_START_TPMINIT = 503,
- TS_END_TPMINIT = 504,
- TS_START_VERIFY_SLOT = 505,
- TS_END_VERIFY_SLOT = 506,
- TS_START_HASH_BODY = 507,
- TS_DONE_LOADING = 508,
- TS_DONE_HASHING = 509,
- TS_END_HASH_BODY = 510,
- TS_START_TPMPCR = 511,
- TS_END_TPMPCR = 512,
- TS_START_TPMLOCK = 513,
- TS_END_TPMLOCK = 514,
- TS_START_EC_SYNC = 515,
+ TS_COPYVER_START = 501,
+ TS_COPYVER_END = 502,
+ TS_TPMINIT_START = 503,
+ TS_TPMINIT_END = 504,
+ TS_VERIFY_SLOT_START = 505,
+ TS_VERIFY_SLOT_END = 506,
+ TS_HASH_BODY_START = 507,
+ TS_LOADING_END = 508,
+ TS_HASHING_END = 509,
+ TS_HASH_BODY_END = 510,
+ TS_TPMPCR_START = 511,
+ TS_TPMPCR_END = 512,
+ TS_TPMLOCK_START = 513,
+ TS_TPMLOCK_END = 514,
+ TS_EC_SYNC_START = 515,
TS_EC_HASH_READY = 516,
TS_EC_POWER_LIMIT_WAIT = 517,
- TS_END_EC_SYNC = 518,
- TS_START_COPYVPD = 550,
- TS_END_COPYVPD_RO = 551,
- TS_END_COPYVPD_RW = 552,
- TS_START_TPM_ENABLE_UPDATE = 553,
- TS_END_TPM_ENABLE_UPDATE = 554,
+ TS_EC_SYNC_END = 518,
+ TS_COPYVPD_START = 550,
+ TS_COPYVPD_RO_END = 551,
+ TS_COPYVPD_RW_END = 552,
+ TS_TPM_ENABLE_UPDATE_START = 553,
+ TS_TPM_ENABLE_UPDATE_END = 554,
/* 900-940 reserved for vendorcode extensions (900-940: AMD) */
TS_AGESA_INIT_RESET_START = 900,
- TS_AGESA_INIT_RESET_DONE = 901,
+ TS_AGESA_INIT_RESET_END = 901,
TS_AGESA_INIT_EARLY_START = 902,
- TS_AGESA_INIT_EARLY_DONE = 903,
+ TS_AGESA_INIT_EARLY_END = 903,
TS_AGESA_INIT_POST_START = 904,
- TS_AGESA_INIT_POST_DONE = 905,
+ TS_AGESA_INIT_POST_END = 905,
TS_AGESA_INIT_ENV_START = 906,
- TS_AGESA_INIT_ENV_DONE = 907,
+ TS_AGESA_INIT_ENV_END = 907,
TS_AGESA_INIT_MID_START = 908,
- TS_AGESA_INIT_MID_DONE = 909,
+ TS_AGESA_INIT_MID_END = 909,
TS_AGESA_INIT_LATE_START = 910,
- TS_AGESA_INIT_LATE_DONE = 911,
+ TS_AGESA_INIT_LATE_END = 911,
TS_AGESA_INIT_RTB_START = 912,
- TS_AGESA_INIT_RTB_DONE = 913,
+ TS_AGESA_INIT_RTB_END = 913,
TS_AGESA_INIT_RESUME_START = 914,
- TS_AGESA_INIT_RESUME_DONE = 915,
+ TS_AGESA_INIT_RESUME_END = 915,
TS_AGESA_S3_LATE_START = 916,
- TS_AGESA_S3_LATE_DONE = 917,
+ TS_AGESA_S3_LATE_END = 917,
TS_AGESA_S3_FINAL_START = 918,
- TS_AGESA_S3_FINAL_DONE = 919,
+ TS_AGESA_S3_FINAL_END = 919,
TS_AMD_APOB_READ_START = 920,
TS_AMD_APOB_ERASE_START = 921,
TS_AMD_APOB_WRITE_START = 922,
- TS_AMD_APOB_DONE = 923,
+ TS_AMD_APOB_END = 923,
/* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */
- TS_ME_INFORM_DRAM_WAIT = 940,
- TS_ME_INFORM_DRAM_DONE = 941,
- TS_ME_BEFORE_END_OF_POST = 942,
- TS_ME_AFTER_END_OF_POST = 943,
- TS_ME_BOOT_STALL_DONE = 944,
+ TS_ME_INFORM_DRAM_START = 940,
+ TS_ME_INFORM_DRAM_END = 941,
+ TS_ME_END_OF_POST_START = 942,
+ TS_ME_END_OF_POST_END = 943,
+ TS_ME_BOOT_STALL_END = 944,
TS_ME_ICC_CONFIG_START = 945,
- TS_ME_HOST_BOOT_PREP_DONE = 946,
+ TS_ME_HOST_BOOT_PREP_END = 946,
TS_ME_RECEIVED_CRDA_FROM_PMC = 947,
- TS_START_CSE_FW_SYNC = 948,
- TS_END_CSE_FW_SYNC = 949,
+ TS_CSE_FW_SYNC_START = 948,
+ TS_CSE_FW_SYNC_END = 949,
/* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */
TS_FSP_MEMORY_INIT_START = 950,
@@ -129,12 +129,12 @@
TS_FSP_TEMP_RAM_EXIT_END = 953,
TS_FSP_SILICON_INIT_START = 954,
TS_FSP_SILICON_INIT_END = 955,
- TS_FSP_BEFORE_ENUMERATE = 956,
- TS_FSP_AFTER_ENUMERATE = 957,
- TS_FSP_BEFORE_FINALIZE = 958,
- TS_FSP_AFTER_FINALIZE = 959,
- TS_FSP_BEFORE_END_OF_FIRMWARE = 960,
- TS_FSP_AFTER_END_OF_FIRMWARE = 961,
+ TS_FSP_ENUMERATE_START = 956,
+ TS_FSP_ENUMERATE_END = 957,
+ TS_FSP_FINALIZE_START = 958,
+ TS_FSP_FINALIZE_END = 959,
+ TS_FSP_END_OF_FIRMWARE_START = 960,
+ TS_FSP_END_OF_FIRMWARE_END = 961,
TS_FSP_MULTI_PHASE_SI_INIT_START = 962,
TS_FSP_MULTI_PHASE_SI_INIT_END = 963,
TS_FSP_MEMORY_INIT_LOAD = 970,
@@ -161,7 +161,7 @@
TS_VB_READ_KERNEL_DONE = 1050,
TS_VB_VBOOT_DONE = 1100,
- TS_START_KERNEL = 1101,
+ TS_KERNEL_START = 1101,
TS_KERNEL_DECOMPRESSION = 1102,
};
@@ -171,23 +171,23 @@
} timestamp_ids[] = {
/* Marker to report base_time. */
{ 0, "1st timestamp" },
- { TS_START_ROMSTAGE, "start of romstage" },
- { TS_BEFORE_INITRAM, "before RAM initialization" },
- { TS_AFTER_INITRAM, "after RAM initialization" },
- { TS_END_ROMSTAGE, "end of romstage" },
- { TS_START_VBOOT, "start of verified boot" },
- { TS_END_VBOOT, "end of verified boot" },
- { TS_START_COPYRAM, "starting to load ramstage" },
- { TS_END_COPYRAM, "finished loading ramstage" },
- { TS_START_RAMSTAGE, "start of ramstage" },
- { TS_START_BOOTBLOCK, "start of bootblock" },
- { TS_END_BOOTBLOCK, "end of bootblock" },
- { TS_START_COPYROM, "starting to load romstage" },
- { TS_END_COPYROM, "finished loading romstage" },
- { TS_START_ULZMA, "starting LZMA decompress (ignore for x86)" },
- { TS_END_ULZMA, "finished LZMA decompress (ignore for x86)" },
- { TS_START_ULZ4F, "starting LZ4 decompress (ignore for x86)" },
- { TS_END_ULZ4F, "finished LZ4 decompress (ignore for x86)" },
+ { TS_ROMSTAGE_START, "start of romstage" },
+ { TS_INITRAM_START, "before RAM initialization" },
+ { TS_INITRAM_END, "after RAM initialization" },
+ { TS_ROMSTAGE_END, "end of romstage" },
+ { TS_VBOOT_START, "start of verified boot" },
+ { TS_VBOOT_END, "end of verified boot" },
+ { TS_COPYRAM_START, "starting to load ramstage" },
+ { TS_COPYRAM_END, "finished loading ramstage" },
+ { TS_RAMSTAGE_START, "start of ramstage" },
+ { TS_BOOTBLOCK_START, "start of bootblock" },
+ { TS_BOOTBLOCK_END, "end of bootblock" },
+ { TS_COPYROM_START, "starting to load romstage" },
+ { TS_COPYROM_END, "finished loading romstage" },
+ { TS_ULZMA_START, "starting LZMA decompress (ignore for x86)" },
+ { TS_ULZMA_END, "finished LZMA decompress (ignore for x86)" },
+ { TS_ULZ4F_START, "starting LZ4 decompress (ignore for x86)" },
+ { TS_ULZ4F_END, "finished LZ4 decompress (ignore for x86)" },
{ TS_DEVICE_ENUMERATE, "device enumeration" },
{ TS_DEVICE_CONFIGURE, "device configuration" },
{ TS_DEVICE_ENABLE, "device enable" },
@@ -209,31 +209,31 @@
{ TS_ELOG_INIT_START, "started elog init" },
{ TS_ELOG_INIT_END, "finished elog init" },
- { TS_START_COPYVER, "starting to load verstage" },
- { TS_END_COPYVER, "finished loading verstage" },
- { TS_START_TPMINIT, "starting to initialize TPM" },
- { TS_END_TPMINIT, "finished TPM initialization" },
- { TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" },
- { TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" },
- { TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " },
- { TS_DONE_LOADING, "finished loading body" },
- { TS_DONE_HASHING, "finished calculating body hash (SHA2)" },
- { TS_END_HASH_BODY, "finished verifying body signature (RSA)" },
- { TS_START_TPMPCR, "starting TPM PCR extend" },
- { TS_END_TPMPCR, "finished TPM PCR extend" },
- { TS_START_TPMLOCK, "starting locking TPM" },
- { TS_END_TPMLOCK, "finished locking TPM" },
- { TS_START_TPM_ENABLE_UPDATE, "started TPM enable update" },
- { TS_END_TPM_ENABLE_UPDATE, "finished TPM enable update" },
+ { TS_COPYVER_START, "starting to load verstage" },
+ { TS_COPYVER_END, "finished loading verstage" },
+ { TS_TPMINIT_START, "starting to initialize TPM" },
+ { TS_TPMINIT_END, "finished TPM initialization" },
+ { TS_VERIFY_SLOT_START, "starting to verify keyblock/preamble (RSA)" },
+ { TS_VERIFY_SLOT_END, "finished verifying keyblock/preamble (RSA)" },
+ { TS_HASH_BODY_START, "starting to verify body (load+SHA2+RSA) " },
+ { TS_LOADING_END, "finished loading body" },
+ { TS_HASHING_END, "finished calculating body hash (SHA2)" },
+ { TS_HASH_BODY_END, "finished verifying body signature (RSA)" },
+ { TS_TPMPCR_START, "starting TPM PCR extend" },
+ { TS_TPMPCR_END, "finished TPM PCR extend" },
+ { TS_TPMLOCK_START, "starting locking TPM" },
+ { TS_TPMLOCK_END, "finished locking TPM" },
+ { TS_TPM_ENABLE_UPDATE_START, "started TPM enable update" },
+ { TS_TPM_ENABLE_UPDATE_END, "finished TPM enable update" },
- { TS_START_COPYVPD, "starting to load Chrome OS VPD" },
- { TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" },
- { TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" },
+ { TS_COPYVPD_START, "starting to load Chrome OS VPD" },
+ { TS_COPYVPD_RO_END, "finished loading Chrome OS VPD (RO)" },
+ { TS_COPYVPD_RW_END, "finished loading Chrome OS VPD (RW)" },
- { TS_START_EC_SYNC, "starting EC software sync" },
+ { TS_EC_SYNC_START, "starting EC software sync" },
{ TS_EC_HASH_READY, "EC vboot hash ready" },
{ TS_EC_POWER_LIMIT_WAIT, "waiting for EC to allow higher power draw" },
- { TS_END_EC_SYNC, "finished EC software sync" },
+ { TS_EC_SYNC_END, "finished EC software sync" },
{ TS_DC_START, "depthcharge start" },
{ TS_RO_PARAMS_INIT, "RO parameter init" },
@@ -247,45 +247,45 @@
{ TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" },
{ TS_VB_VBOOT_DONE, "finished vboot kernel verification" },
{ TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" },
- { TS_START_KERNEL, "jumping to kernel" },
+ { TS_KERNEL_START, "jumping to kernel" },
/* AMD related timestamps */
{ TS_AGESA_INIT_RESET_START, "calling AmdInitReset" },
- { TS_AGESA_INIT_RESET_DONE, "back from AmdInitReset" },
+ { TS_AGESA_INIT_RESET_END, "back from AmdInitReset" },
{ TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" },
- { TS_AGESA_INIT_EARLY_DONE, "back from AmdInitEarly" },
+ { TS_AGESA_INIT_EARLY_END, "back from AmdInitEarly" },
{ TS_AGESA_INIT_POST_START, "calling AmdInitPost" },
- { TS_AGESA_INIT_POST_DONE, "back from AmdInitPost" },
+ { TS_AGESA_INIT_POST_END, "back from AmdInitPost" },
{ TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" },
- { TS_AGESA_INIT_ENV_DONE, "back from AmdInitEnv" },
+ { TS_AGESA_INIT_ENV_END, "back from AmdInitEnv" },
{ TS_AGESA_INIT_MID_START, "calling AmdInitMid" },
- { TS_AGESA_INIT_MID_DONE, "back from AmdInitMid" },
+ { TS_AGESA_INIT_MID_END, "back from AmdInitMid" },
{ TS_AGESA_INIT_LATE_START, "calling AmdInitLate" },
- { TS_AGESA_INIT_LATE_DONE, "back from AmdInitLate" },
+ { TS_AGESA_INIT_LATE_END, "back from AmdInitLate" },
{ TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" },
- { TS_AGESA_INIT_RTB_DONE, "back from AmdInitRtb/AmdS3Save" },
+ { TS_AGESA_INIT_RTB_END, "back from AmdInitRtb/AmdS3Save" },
{ TS_AGESA_INIT_RESUME_START, "calling AmdInitResume" },
- { TS_AGESA_INIT_RESUME_DONE, "back from AmdInitResume" },
+ { TS_AGESA_INIT_RESUME_END, "back from AmdInitResume" },
{ TS_AGESA_S3_LATE_START, "calling AmdS3LateRestore" },
- { TS_AGESA_S3_LATE_DONE, "back from AmdS3LateRestore" },
+ { TS_AGESA_S3_LATE_END, "back from AmdS3LateRestore" },
{ TS_AGESA_S3_FINAL_START, "calling AmdS3FinalRestore" },
- { TS_AGESA_S3_FINAL_DONE, "back from AmdS3FinalRestore" },
+ { TS_AGESA_S3_FINAL_END, "back from AmdS3FinalRestore" },
{ TS_AMD_APOB_READ_START, "starting APOB read" },
{ TS_AMD_APOB_ERASE_START, "starting APOB erase" },
{ TS_AMD_APOB_WRITE_START, "starting APOB write" },
- { TS_AMD_APOB_DONE, "finished APOB" },
+ { TS_AMD_APOB_END, "finished APOB" },
/* Intel ME related timestamps */
- { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"},
- { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"},
- { TS_ME_BEFORE_END_OF_POST, "before sending EOP to ME"},
- { TS_ME_AFTER_END_OF_POST, "after sending EOP to ME"},
- { TS_ME_BOOT_STALL_DONE, "CSE sent 'Boot Stall Done' to PMC"},
+ { TS_ME_INFORM_DRAM_START, "waiting for ME acknowledgement of raminit"},
+ { TS_ME_INFORM_DRAM_END, "finished waiting for ME response"},
+ { TS_ME_END_OF_POST_START, "before sending EOP to ME"},
+ { TS_ME_END_OF_POST_END, "after sending EOP to ME"},
+ { TS_ME_BOOT_STALL_END, "CSE sent 'Boot Stall Done' to PMC"},
{ TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"},
- { TS_ME_HOST_BOOT_PREP_DONE, "CSE sent 'Host BIOS Prep Done' to PMC"},
+ { TS_ME_HOST_BOOT_PREP_END, "CSE sent 'Host BIOS Prep Done' to PMC"},
{ TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"},
- { TS_START_CSE_FW_SYNC, "starting CSE firmware sync"},
- { TS_END_CSE_FW_SYNC, "finished CSE firmware sync"},
+ { TS_CSE_FW_SYNC_START, "starting CSE firmware sync"},
+ { TS_CSE_FW_SYNC_END, "finished CSE firmware sync"},
{ TS_ME_ROM_START, "CSME ROM started execution"},
/* FSP related timestamps */
@@ -297,20 +297,20 @@
{ TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" },
{ TS_FSP_MULTI_PHASE_SI_INIT_START, "calling FspMultiPhaseSiInit" },
{ TS_FSP_MULTI_PHASE_SI_INIT_END, "returning from FspMultiPhaseSiInit" },
- { TS_FSP_BEFORE_ENUMERATE, "calling FspNotify(AfterPciEnumeration)" },
- { TS_FSP_AFTER_ENUMERATE,
+ { TS_FSP_ENUMERATE_START, "calling FspNotify(AfterPciEnumeration)" },
+ { TS_FSP_ENUMERATE_END,
"returning from FspNotify(AfterPciEnumeration)" },
- { TS_FSP_BEFORE_FINALIZE, "calling FspNotify(ReadyToBoot)" },
- { TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" },
- { TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" },
- { TS_FSP_AFTER_END_OF_FIRMWARE,
+ { TS_FSP_FINALIZE_START, "calling FspNotify(ReadyToBoot)" },
+ { TS_FSP_FINALIZE_END, "returning from FspNotify(ReadyToBoot)" },
+ { TS_FSP_END_OF_FIRMWARE_START, "calling FspNotify(EndOfFirmware)" },
+ { TS_FSP_END_OF_FIRMWARE_END,
"returning from FspNotify(EndOfFirmware)" },
{ TS_FSP_MEMORY_INIT_LOAD, "loading FSP-M" },
{ TS_FSP_SILICON_INIT_LOAD, "loading FSP-S" },
- { TS_START_POSTCAR, "start of postcar" },
- { TS_END_POSTCAR, "end of postcar" },
+ { TS_POSTCAR_START, "start of postcar" },
+ { TS_POSTCAR_END, "end of postcar" },
};
#endif
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 63ddd74..85bc894 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -60,7 +60,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
/* Assumes the hardware was set up during the bootblock */
console_init();
diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c
index 126a2ee..7154c95 100644
--- a/src/drivers/amd/agesa/eventlog.c
+++ b/src/drivers/amd/agesa/eventlog.c
@@ -28,69 +28,69 @@
.func = AMD_INIT_RESET,
.name = "AmdInitReset",
.entry_id = TS_AGESA_INIT_RESET_START,
- .exit_id = TS_AGESA_INIT_RESET_DONE,
+ .exit_id = TS_AGESA_INIT_RESET_END,
},
{
.func = AMD_INIT_EARLY,
.name = "AmdInitEarly",
.entry_id = TS_AGESA_INIT_EARLY_START,
- .exit_id = TS_AGESA_INIT_EARLY_DONE,
+ .exit_id = TS_AGESA_INIT_EARLY_END,
},
{
.func = AMD_INIT_POST,
.name = "AmdInitPost",
.entry_id = TS_AGESA_INIT_POST_START,
- .exit_id = TS_AGESA_INIT_POST_DONE,
+ .exit_id = TS_AGESA_INIT_POST_END,
},
{
.func = AMD_INIT_RESUME,
.name = "AmdInitResume",
.entry_id = TS_AGESA_INIT_RESUME_START,
- .exit_id = TS_AGESA_INIT_RESUME_DONE,
+ .exit_id = TS_AGESA_INIT_RESUME_END,
},
{
.func = AMD_INIT_ENV,
.name = "AmdInitEnv",
.entry_id = TS_AGESA_INIT_ENV_START,
- .exit_id = TS_AGESA_INIT_ENV_DONE,
+ .exit_id = TS_AGESA_INIT_ENV_END,
},
{
.func = AMD_INIT_MID,
.name = "AmdInitMid",
.entry_id = TS_AGESA_INIT_MID_START,
- .exit_id = TS_AGESA_INIT_MID_DONE,
+ .exit_id = TS_AGESA_INIT_MID_END,
},
{
.func = AMD_INIT_LATE,
.name = "AmdInitLate",
.entry_id = TS_AGESA_INIT_LATE_START,
- .exit_id = TS_AGESA_INIT_LATE_DONE,
+ .exit_id = TS_AGESA_INIT_LATE_END,
},
{
.func = AMD_S3LATE_RESTORE,
.name = "AmdS3LateRestore",
.entry_id = TS_AGESA_S3_LATE_START,
- .exit_id = TS_AGESA_S3_LATE_DONE,
+ .exit_id = TS_AGESA_S3_LATE_END,
},
#if !defined(AMD_S3_SAVE_REMOVED)
{
.func = AMD_S3_SAVE,
.name = "AmdS3Save",
.entry_id = TS_AGESA_INIT_RTB_START,
- .exit_id = TS_AGESA_INIT_RTB_DONE,
+ .exit_id = TS_AGESA_INIT_RTB_END,
},
#endif
{
.func = AMD_S3FINAL_RESTORE,
.name = "AmdS3FinalRestore",
.entry_id = TS_AGESA_S3_FINAL_START,
- .exit_id = TS_AGESA_S3_FINAL_DONE,
+ .exit_id = TS_AGESA_S3_FINAL_END,
},
{
.func = AMD_INIT_RTB,
.name = "AmdInitRtb",
.entry_id = TS_AGESA_INIT_RTB_START,
- .exit_id = TS_AGESA_INIT_RTB_DONE,
+ .exit_id = TS_AGESA_INIT_RTB_END,
},
};
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 871054b..5968f73 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -40,7 +40,7 @@
fill_sysinfo(cb);
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
board_BeforeAgesa(cb);
@@ -55,14 +55,14 @@
agesa_execute_state(cb, AMD_INIT_EARLY);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
if (!cb->s3resume)
agesa_execute_state(cb, AMD_INIT_POST);
else
agesa_execute_state(cb, AMD_INIT_RESUME);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
/* Work around AGESA setting all memory as WB on normal
* boot path.
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 570648c..7dc16c3 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -134,17 +134,17 @@
notify_phase_params.Phase = phase;
if (phase == EnumInitPhaseReadyToBoot) {
- timestamp_add_now(TS_FSP_BEFORE_FINALIZE);
+ timestamp_add_now(TS_FSP_FINALIZE_START);
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
} else {
- timestamp_add_now(TS_FSP_BEFORE_ENUMERATE);
+ timestamp_add_now(TS_FSP_ENUMERATE_START);
post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
}
status = notify_phase_proc(¬ify_phase_params);
timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
- TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
+ TS_FSP_FINALIZE_END : TS_FSP_ENUMERATE_END);
if (status != 0)
printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n",
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 3ed73d3..7fd1cf5 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -26,7 +26,7 @@
post_code(0x32);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
s3wake = params->power_state->prev_sleep_state == ACPI_S3;
@@ -66,7 +66,7 @@
/* Initialize RAM */
raminit(params);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
/* Save MRC output */
if (CONFIG(CACHE_MRC_SETTINGS)) {
@@ -100,7 +100,7 @@
post_code(0x30);
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
/* Display parameters */
if (!CONFIG(NO_ECAM_MMCONF_SUPPORT))
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index b7e81f0..1612089 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -380,9 +380,9 @@
die("FSPM XIP base does not match: %p vs %p\n",
(void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog));
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
do_fsp_memory_init(&context, s3wake);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
}
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index 30d61c9..5cd63d8 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -23,24 +23,24 @@
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM),
.post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
.post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE,
- .timestamp_before = TS_FSP_BEFORE_ENUMERATE,
- .timestamp_after = TS_FSP_AFTER_ENUMERATE,
+ .timestamp_before = TS_FSP_ENUMERATE_START,
+ .timestamp_after = TS_FSP_ENUMERATE_END,
},
{
.notify_phase = READY_TO_BOOT,
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT),
.post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
.post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE,
- .timestamp_before = TS_FSP_BEFORE_FINALIZE,
- .timestamp_after = TS_FSP_AFTER_FINALIZE,
+ .timestamp_before = TS_FSP_FINALIZE_START,
+ .timestamp_after = TS_FSP_FINALIZE_END,
},
{
.notify_phase = END_OF_FIRMWARE,
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
.post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
.post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
- .timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE,
- .timestamp_after = TS_FSP_AFTER_END_OF_FIRMWARE,
+ .timestamp_before = TS_FSP_END_OF_FIRMWARE_START,
+ .timestamp_after = TS_FSP_END_OF_FIRMWARE_END,
},
};
diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c
index 396097c..32ec0a0 100644
--- a/src/drivers/vpd/vpd.c
+++ b/src/drivers/vpd/vpd.c
@@ -126,7 +126,7 @@
{
struct vpd_cbmem *cbmem;
- timestamp_add_now(TS_START_COPYVPD);
+ timestamp_add_now(TS_COPYVPD_START);
init_vpd_rdevs();
@@ -154,7 +154,7 @@
printk(BIOS_ERR, "Couldn't read RO VPD\n");
cbmem->ro_size = ro_size = 0;
}
- timestamp_add_now(TS_END_COPYVPD_RO);
+ timestamp_add_now(TS_COPYVPD_RO_END);
}
if (rw_size) {
@@ -163,7 +163,7 @@
printk(BIOS_ERR, "Couldn't read RW VPD\n");
cbmem->rw_size = rw_size = 0;
}
- timestamp_add_now(TS_END_COPYVPD_RW);
+ timestamp_add_now(TS_COPYVPD_RW_END);
}
init_vpd_rdevs_from_cbmem();
diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c
index 5989964..5c202ba 100644
--- a/src/lib/bootblock.c
+++ b/src/lib/bootblock.c
@@ -39,7 +39,7 @@
timestamps[i].entry_stamp);
}
- timestamp_add_now(TS_START_BOOTBLOCK);
+ timestamp_add_now(TS_BOOTBLOCK_START);
bootblock_soc_early_init();
bootblock_mainboard_early_init();
@@ -63,7 +63,7 @@
tpm_setup(s3resume);
}
- timestamp_add_now(TS_END_BOOTBLOCK);
+ timestamp_add_now(TS_BOOTBLOCK_END);
run_romstage();
}
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 2d98c44..0f07a32 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -215,9 +215,9 @@
return 0;
if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) {
- timestamp_add_now(TS_START_ULZ4F);
+ timestamp_add_now(TS_ULZ4F_START);
out_size = ulz4fn(map, in_size, buffer, buffer_size);
- timestamp_add_now(TS_END_ULZ4F);
+ timestamp_add_now(TS_ULZ4F_END);
}
rdev_munmap(rdev, map);
@@ -233,9 +233,9 @@
if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) {
/* Note: timestamp not useful for memory-mapped media (x86) */
- timestamp_add_now(TS_START_ULZMA);
+ timestamp_add_now(TS_ULZMA_START);
out_size = ulzman(map, in_size, buffer, buffer_size);
- timestamp_add_now(TS_END_ULZMA);
+ timestamp_add_now(TS_ULZMA_END);
}
rdev_munmap(rdev, map);
diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c
index 1d160e0..22d31df 100644
--- a/src/lib/decompressor.c
+++ b/src/lib/decompressor.c
@@ -23,8 +23,8 @@
.base_timestamp = 0,
.num_timestamps = 2,
.timestamps = {
- { .entry_id = TS_START_ULZ4F },
- { .entry_id = TS_END_ULZ4F },
+ { .entry_id = TS_ULZ4F_START },
+ { .entry_id = TS_ULZ4F_END },
},
};
diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c
index d61bfd5..21bc4e8 100644
--- a/src/lib/fit_payload.c
+++ b/src/lib/fit_payload.c
@@ -62,14 +62,14 @@
true_size = node->size;
break;
case CBFS_COMPRESS_LZMA:
- timestamp_add_now(TS_START_ULZMA);
+ timestamp_add_now(TS_ULZMA_START);
true_size = ulzman(node->data, node->size, dst, region->size);
- timestamp_add_now(TS_END_ULZMA);
+ timestamp_add_now(TS_ULZMA_END);
break;
case CBFS_COMPRESS_LZ4:
- timestamp_add_now(TS_START_ULZ4F);
+ timestamp_add_now(TS_ULZ4F_START);
true_size = ulz4fn(node->data, node->size, dst, region->size);
- timestamp_add_now(TS_END_ULZ4F);
+ timestamp_add_now(TS_ULZ4F_END);
break;
default:
return true;
@@ -240,5 +240,5 @@
return;
}
- timestamp_add_now(TS_START_KERNEL);
+ timestamp_add_now(TS_KERNEL_START);
}
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index b646e0c..b5ed6e0 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -457,7 +457,7 @@
*/
cbmem_initialize();
- timestamp_add_now(TS_START_RAMSTAGE);
+ timestamp_add_now(TS_RAMSTAGE_START);
post_code(POST_ENTRY_HARDWAREMAIN);
/* Handoff sleep type from romstage. */
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 25a8836..a296bd6 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -24,7 +24,7 @@
vboot_run_logic();
- timestamp_add_now(TS_START_COPYROM);
+ timestamp_add_now(TS_COPYROM_START);
if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) {
if (legacy_romstage_select_and_load(&romstage))
@@ -34,7 +34,7 @@
goto fail;
}
- timestamp_add_now(TS_END_COPYROM);
+ timestamp_add_now(TS_COPYROM_END);
console_time_report();
@@ -90,11 +90,11 @@
PROG_INIT(PROG_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage");
if (ENV_POSTCAR)
- timestamp_add_now(TS_END_POSTCAR);
+ timestamp_add_now(TS_POSTCAR_END);
/* Call "end of romstage" here if postcar stage doesn't exist */
if (ENV_ROMSTAGE)
- timestamp_add_now(TS_END_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_END);
/*
* Only x86 systems using ramstage stage cache currently take the same
@@ -105,7 +105,7 @@
vboot_run_logic();
- timestamp_add_now(TS_START_COPYRAM);
+ timestamp_add_now(TS_COPYRAM_START);
if (ENV_X86) {
if (load_relocatable_ramstage(&ramstage))
@@ -117,7 +117,7 @@
stage_cache_add(STAGE_RAMSTAGE, &ramstage);
- timestamp_add_now(TS_END_COPYRAM);
+ timestamp_add_now(TS_COPYRAM_END);
console_time_report();
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index f1c0b97..70ab719 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -72,18 +72,18 @@
switch (compression) {
case CBFS_COMPRESS_LZMA: {
printk(BIOS_DEBUG, "using LZMA\n");
- timestamp_add_now(TS_START_ULZMA);
+ timestamp_add_now(TS_ULZMA_START);
len = ulzman(src, len, dest, memsz);
- timestamp_add_now(TS_END_ULZMA);
+ timestamp_add_now(TS_ULZMA_END);
if (!len) /* Decompression Error. */
return 0;
break;
}
case CBFS_COMPRESS_LZ4: {
printk(BIOS_DEBUG, "using LZ4\n");
- timestamp_add_now(TS_START_ULZ4F);
+ timestamp_add_now(TS_ULZ4F_START);
len = ulz4fn(src, len, dest, memsz);
- timestamp_add_now(TS_END_ULZ4F);
+ timestamp_add_now(TS_ULZ4F_END);
if (!len) /* Decompression Error. */
return 0;
break;
diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c
index b8105fd..dd3bc72 100644
--- a/src/mainboard/google/daisy/romstage.c
+++ b/src/mainboard/google/daisy/romstage.c
@@ -123,7 +123,7 @@
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
@@ -134,11 +134,11 @@
setup_power(is_resume);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
setup_memory(mem, is_resume);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
/* This needs to happen on normal boots and on resume. */
trustzone_init();
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 9579047..4ae7ef0 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -24,7 +24,7 @@
static void __attribute__((noinline)) romstage(void)
{
timestamp_init(0);
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
console_init();
exception_init();
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 9579047..4ae7ef0 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -24,7 +24,7 @@
static void __attribute__((noinline)) romstage(void)
{
timestamp_init(0);
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
console_init();
exception_init();
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index f1087d0..229e236 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -25,7 +25,7 @@
static void __attribute__((noinline)) romstage(void)
{
timestamp_init(0);
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
console_init();
exception_init();
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 83d38fa..3509a45 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -212,7 +212,7 @@
power_init_failed = setup_power(is_resume);
timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
@@ -228,11 +228,11 @@
/* re-initialize PMIC I2C channel after (re-)setting system clocks */
i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
setup_memory(&mem_timings, is_resume);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
primitive_mem_test();
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
index 35ddf85..de4617c 100644
--- a/src/mainboard/google/veyron/romstage.c
+++ b/src/mainboard/google/veyron/romstage.c
@@ -64,7 +64,7 @@
void main(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
console_init();
exception_init();
@@ -77,11 +77,11 @@
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
sdram_init(get_sdram_config());
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c
index bac2acb..fb0230a 100644
--- a/src/mainboard/google/veyron_mickey/romstage.c
+++ b/src/mainboard/google/veyron_mickey/romstage.c
@@ -58,7 +58,7 @@
void main(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
console_init();
exception_init();
@@ -68,11 +68,11 @@
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
sdram_init(get_sdram_config());
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c
index acea7a0..db2e343 100644
--- a/src/mainboard/google/veyron_rialto/romstage.c
+++ b/src/mainboard/google/veyron_rialto/romstage.c
@@ -64,7 +64,7 @@
void main(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
console_init();
exception_init();
@@ -77,11 +77,11 @@
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
sdram_init(get_sdram_config());
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 4a8cf90..22a14ae 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -1704,7 +1704,7 @@
if (!e7505_mch_is_ready()) {
/* The real MCH initialisation. */
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
sdram_set_registers(memctrl);
sdram_set_spd_registers(memctrl);
@@ -1713,7 +1713,7 @@
/* Hook for post ECC scrub settings and debug. */
sdram_post_ecc(memctrl);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
}
printk(BIOS_DEBUG, "SDRAM is up.\n");
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 6e505da..35d71c0 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1695,7 +1695,7 @@
int ch;
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
/* Wait for some bit, maybe TXT clear. */
if (sysinfo->txt_enabled) {
@@ -1803,5 +1803,5 @@
raminit_thermal(sysinfo);
init_igd(sysinfo);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
}
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index e1a9337..5336769 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -405,13 +405,13 @@
pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
copy_spd(&pei_data, &spdi);
sdram_initialize(&pei_data);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
post_code(0x3b);
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index e5d377e..93cbeb9 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -1004,7 +1004,7 @@
void sdram_initialize(int s3resume)
{
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
enable_spd();
dump_spd_registers();
@@ -1013,5 +1013,5 @@
sdram_enable();
disable_spd();
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index e168f7c..982099e 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2683,7 +2683,7 @@
{
struct sys_info sysinfo;
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
memset(&sysinfo, 0, sizeof(sysinfo));
@@ -2783,5 +2783,5 @@
printk(BIOS_DEBUG, "RAM initialization finished.\n");
sdram_setup_processor_side();
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
}
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c
index 242100b..f717782 100644
--- a/src/northbridge/intel/ironlake/romstage.c
+++ b/src/northbridge/intel/ironlake/romstage.c
@@ -42,7 +42,7 @@
early_thermal_init();
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
chipset_init(s3resume);
@@ -52,7 +52,7 @@
raminit(s3resume, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
intel_early_me_status();
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index a98ae99..03058ec 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -50,9 +50,9 @@
get_mb_spd_addrmap(&spd_addrmap[0]);
printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
printk(BIOS_DEBUG, "Memory initialized\n");
post_code(0x31);
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index a3e7016..9082f8a 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -298,7 +298,7 @@
size_t mrc_size;
ramctr_timing *ctrl_cached = NULL;
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
mchbar_setbits32(SAPMCTL, 1 << 0);
@@ -460,7 +460,7 @@
report_memory_config();
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
cbmem_was_inited = !cbmem_recovery(s3resume);
if (!fast_boot)
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index c52203a..fbb2b6e 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -364,9 +364,9 @@
disable_p2p();
pei_data.boot_mode = s3resume ? 2 : 0;
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
sdram_initialize(&pei_data);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
/* Sanity check mrc_var location by verifying a known field */
mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE;
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 460916b..2f844a5 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -566,7 +566,7 @@
int fast_boot, cbmem_was_inited;
size_t mrc_size;
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
pci_write_config8(HOST_BRIDGE, 0xdf, 0xff);
@@ -638,7 +638,7 @@
pci_or_config8(HOST_BRIDGE, 0xf4, 1);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
printk(BIOS_DEBUG, "RAM initialization finished.\n");
diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c
index f31b783..56e6c44 100644
--- a/src/security/vboot/ec_sync.c
+++ b/src/security/vboot/ec_sync.c
@@ -42,7 +42,7 @@
vb2_error_t retval = VB2_SUCCESS;
struct vb2_context *ctx;
- timestamp_add_now(TS_START_EC_SYNC);
+ timestamp_add_now(TS_EC_SYNC_START);
ctx = vboot_get_context();
ctx->flags |= VB2_CONTEXT_EC_SYNC_SUPPORTED;
@@ -84,7 +84,7 @@
break;
}
- timestamp_add_now(TS_END_EC_SYNC);
+ timestamp_add_now(TS_EC_SYNC_END);
}
/* Convert firmware image type into a flash offset */
diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c
index 482c6fb..1c4343b 100644
--- a/src/security/vboot/vboot_loader.c
+++ b/src/security/vboot/vboot_loader.c
@@ -52,10 +52,10 @@
printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n");
- timestamp_add_now(TS_START_COPYVER);
+ timestamp_add_now(TS_COPYVER_START);
if (cbfs_prog_stage_load(&verstage))
die("failed to load verstage");
- timestamp_add_now(TS_END_COPYVER);
+ timestamp_add_now(TS_COPYVER_END);
/* verify and select a slot */
prog_run(&verstage);
diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c
index 91d42b2..509169f 100644
--- a/src/security/vboot/vboot_logic.c
+++ b/src/security/vboot/vboot_logic.c
@@ -140,7 +140,7 @@
* (This split won't make sense with memory-mapped media like on x86.)
*/
load_ts = timestamp_get();
- timestamp_add(TS_START_HASH_BODY, load_ts);
+ timestamp_add(TS_HASH_BODY_START, load_ts);
remaining = region_device_sz(fw_body);
offset = 0;
@@ -169,15 +169,15 @@
offset += block_size;
}
- timestamp_add(TS_DONE_LOADING, load_ts);
- timestamp_add_now(TS_DONE_HASHING);
+ timestamp_add(TS_LOADING_END, load_ts);
+ timestamp_add_now(TS_HASHING_END);
/* Check the result (with RSA signature verification) */
rv = vb2api_check_hash_get_digest(ctx, hash_digest, hash_digest_sz);
if (rv)
return rv;
- timestamp_add_now(TS_END_HASH_BODY);
+ timestamp_add_now(TS_HASH_BODY_END);
if (handle_digest_result(hash_digest, hash_digest_sz))
return VB2_ERROR_UNKNOWN;
@@ -248,7 +248,7 @@
struct region_device fw_body;
vb2_error_t rv;
- timestamp_add_now(TS_START_VBOOT);
+ timestamp_add_now(TS_VBOOT_START);
/* Lockdown SPI flash controller if required */
if (CONFIG(BOOTMEDIA_LOCK_IN_VERSTAGE))
@@ -271,12 +271,12 @@
/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
* check the return value here because vb2api_fw_phase1 will catch
* invalid secdata and tell us what to do (=reboot). */
- timestamp_add_now(TS_START_TPMINIT);
+ timestamp_add_now(TS_TPMINIT_START);
if (vboot_setup_tpm(ctx) == TPM_SUCCESS) {
antirollback_read_space_firmware(ctx);
antirollback_read_space_kernel(ctx);
}
- timestamp_add_now(TS_END_TPMINIT);
+ timestamp_add_now(TS_TPMINIT_END);
if (get_recovery_mode_switch()) {
ctx->flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
@@ -343,9 +343,9 @@
/* Try that slot (verify its keyblock and preamble) */
printk(BIOS_INFO, "Phase 3\n");
- timestamp_add_now(TS_START_VERIFY_SLOT);
+ timestamp_add_now(TS_VERIFY_SLOT_START);
rv = vb2api_fw_phase3(ctx);
- timestamp_add_now(TS_END_VERIFY_SLOT);
+ timestamp_add_now(TS_VERIFY_SLOT_END);
if (rv) {
printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
vboot_save_data(ctx);
@@ -367,7 +367,7 @@
/* Only extend PCRs once on boot. */
if (!(ctx->flags & VB2_CONTEXT_S3_RESUME)) {
- timestamp_add_now(TS_START_TPMPCR);
+ timestamp_add_now(TS_TPMPCR_START);
rv = extend_pcrs(ctx);
if (rv) {
printk(BIOS_WARNING,
@@ -376,12 +376,12 @@
vboot_save_data(ctx);
vboot_reboot();
}
- timestamp_add_now(TS_END_TPMPCR);
+ timestamp_add_now(TS_TPMPCR_END);
}
/* Lock TPM */
- timestamp_add_now(TS_START_TPMLOCK);
+ timestamp_add_now(TS_TPMLOCK_START);
rv = antirollback_lock_space_firmware();
if (rv) {
printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
@@ -389,7 +389,7 @@
vboot_save_data(ctx);
vboot_reboot();
}
- timestamp_add_now(TS_END_TPMLOCK);
+ timestamp_add_now(TS_TPMLOCK_END);
/* Lock rec hash space if available. */
if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) {
@@ -408,5 +408,5 @@
vboot_is_firmware_slot_a(ctx) ? 'A' : 'B');
verstage_main_exit:
- timestamp_add_now(TS_END_VBOOT);
+ timestamp_add_now(TS_VBOOT_END);
}
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 9e863c3..9628571 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -12,7 +12,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
post_code(0x40);
diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c
index b932458..f203377 100644
--- a/src/soc/amd/common/block/apob/apob_cache.c
+++ b/src/soc/amd/common/block/apob/apob_cache.c
@@ -171,7 +171,7 @@
printk(BIOS_DEBUG, "APOB valid copy is already in flash\n");
if (!update_needed) {
- timestamp_add_now(TS_AMD_APOB_DONE);
+ timestamp_add_now(TS_AMD_APOB_END);
return;
}
@@ -199,7 +199,7 @@
return;
}
- timestamp_add_now(TS_AMD_APOB_DONE);
+ timestamp_add_now(TS_AMD_APOB_END);
printk(BIOS_INFO, "Updated APOB in flash\n");
}
diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c
index 8ee962b..c5e6cac 100644
--- a/src/soc/amd/common/pi/agesawrapper.c
+++ b/src/soc/amd/common/pi/agesawrapper.c
@@ -102,7 +102,7 @@
timestamp_add_now(TS_AGESA_INIT_RESET_START);
status = amd_dispatch(ResetParams);
- timestamp_add_now(TS_AGESA_INIT_RESET_DONE);
+ timestamp_add_now(TS_AGESA_INIT_RESET_END);
return status;
}
@@ -116,7 +116,7 @@
timestamp_add_now(TS_AGESA_INIT_EARLY_START);
status = amd_dispatch(EarlyParams);
- timestamp_add_now(TS_AGESA_INIT_EARLY_DONE);
+ timestamp_add_now(TS_AGESA_INIT_EARLY_END);
return status;
}
@@ -173,7 +173,7 @@
timestamp_add_now(TS_AGESA_INIT_POST_START);
status = amd_dispatch(PostParams);
- timestamp_add_now(TS_AGESA_INIT_POST_DONE);
+ timestamp_add_now(TS_AGESA_INIT_POST_END);
/*
* AGESA passes back the base and size of UMA. This is the only
@@ -208,7 +208,7 @@
timestamp_add_now(TS_AGESA_INIT_ENV_START);
status = amd_dispatch(EnvParams);
- timestamp_add_now(TS_AGESA_INIT_ENV_DONE);
+ timestamp_add_now(TS_AGESA_INIT_ENV_END);
return status;
}
@@ -251,7 +251,7 @@
timestamp_add_now(TS_AGESA_INIT_MID_START);
status = amd_dispatch(MidParams);
- timestamp_add_now(TS_AGESA_INIT_MID_DONE);
+ timestamp_add_now(TS_AGESA_INIT_MID_END);
return status;
}
@@ -268,7 +268,7 @@
timestamp_add_now(TS_AGESA_INIT_LATE_START);
Status = amd_dispatch(LateParams);
- timestamp_add_now(TS_AGESA_INIT_LATE_DONE);
+ timestamp_add_now(TS_AGESA_INIT_LATE_END);
DmiTable = LateParams->DmiTable;
AcpiPstate = LateParams->AcpiPState;
@@ -295,7 +295,7 @@
timestamp_add_now(TS_AGESA_INIT_RTB_START);
Status = amd_dispatch(RtbParams);
- timestamp_add_now(TS_AGESA_INIT_RTB_DONE);
+ timestamp_add_now(TS_AGESA_INIT_RTB_END);
if (Status != AGESA_SUCCESS)
return Status;
@@ -314,7 +314,7 @@
timestamp_add_now(TS_AGESA_INIT_RESUME_START);
status = amd_dispatch(InitResumeParams);
- timestamp_add_now(TS_AGESA_INIT_RESUME_DONE);
+ timestamp_add_now(TS_AGESA_INIT_RESUME_END);
return status;
}
@@ -329,7 +329,7 @@
timestamp_add_now(TS_AGESA_S3_LATE_START);
Status = amd_dispatch(S3LateParams);
- timestamp_add_now(TS_AGESA_S3_LATE_DONE);
+ timestamp_add_now(TS_AGESA_S3_LATE_END);
return Status;
}
@@ -342,7 +342,7 @@
timestamp_add_now(TS_AGESA_S3_FINAL_START);
Status = amd_dispatch(S3FinalParams);
- timestamp_add_now(TS_AGESA_S3_FINAL_DONE);
+ timestamp_add_now(TS_AGESA_S3_FINAL_END);
return Status;
}
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 1972410..359eacf 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -13,7 +13,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
post_code(0x40);
diff --git a/src/soc/amd/sabrina/romstage.c b/src/soc/amd/sabrina/romstage.c
index 91f80ef..49ca223 100644
--- a/src/soc/amd/sabrina/romstage.c
+++ b/src/soc/amd/sabrina/romstage.c
@@ -14,7 +14,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
post_code(0x40);
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index ae83d49..9720d9e 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -137,9 +137,9 @@
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) {
- timestamp_add_now(TS_START_CSE_FW_SYNC);
+ timestamp_add_now(TS_CSE_FW_SYNC_START);
cse_fw_sync();
- timestamp_add_now(TS_END_CSE_FW_SYNC);
+ timestamp_add_now(TS_CSE_FW_SYNC_END);
}
/*
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index dbf4afc..74238e2 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -101,7 +101,7 @@
memset(&mp, 0, sizeof(mp));
mainboard_fill_mrc_params(&mp);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
ps = fill_power_state();
prev_sleep_state = chipset_prev_sleep_state(ps);
@@ -115,7 +115,7 @@
/* Initialize RAM */
raminit(&mp, prev_sleep_state);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
romstage_handoff_init(s3resume);
}
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index 28b3f37..95073d3 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -188,14 +188,14 @@
post_code(0x32);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
pei_data.boot_mode = power_state->prev_sleep_state;
/* Initialize RAM */
sdram_initialize(&pei_data);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
int cbmem_was_initted = !cbmem_recovery(s3resume);
if (s3resume && !cbmem_was_initted) {
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c
index 3a08a73..af6abb8 100644
--- a/src/soc/intel/common/block/cse/cse_eop.c
+++ b/src/soc/intel/common/block/cse/cse_eop.c
@@ -192,9 +192,9 @@
set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
- timestamp_add_now(TS_ME_BEFORE_END_OF_POST);
+ timestamp_add_now(TS_ME_END_OF_POST_START);
handle_cse_eop_result(cse_send_eop());
- timestamp_add_now(TS_ME_AFTER_END_OF_POST);
+ timestamp_add_now(TS_ME_END_OF_POST_END);
set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE);
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 561bed9..866996f 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -166,7 +166,7 @@
"ME: ME is reporting as disabled, "
"so not waiting for a response.\n");
} else {
- timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
+ timestamp_add_now(TS_ME_INFORM_DRAM_START);
udelay(100);
millisec = 0;
do {
@@ -177,7 +177,7 @@
millisec++;
} while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK)
&& (millisec <= 5000));
- timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
+ timestamp_add_now(TS_ME_INFORM_DRAM_END);
}
me_fws2 = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c
index 0a24d0f..9ac33a5 100644
--- a/src/vendorcode/google/chromeos/cr50_enable_update.c
+++ b/src/vendorcode/google/chromeos/cr50_enable_update.c
@@ -89,7 +89,7 @@
return;
}
- timestamp_add_now(TS_START_TPM_ENABLE_UPDATE);
+ timestamp_add_now(TS_TPM_ENABLE_UPDATE_START);
/* Reboot in 1000 ms if necessary. */
ret = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS,
@@ -117,7 +117,7 @@
*/
cr50_reset_reqd = cr50_is_reset_needed();
if (!cr50_reset_reqd) {
- timestamp_add_now(TS_END_TPM_ENABLE_UPDATE);
+ timestamp_add_now(TS_TPM_ENABLE_UPDATE_END);
return;
}
diff --git a/tests/lib/timestamp-test.c b/tests/lib/timestamp-test.c
index 06a5a00..a3f50db 100644
--- a/tests/lib/timestamp-test.c
+++ b/tests/lib/timestamp-test.c
@@ -25,7 +25,7 @@
timestamp_init(timestamp_base);
- timestamp_add(TS_START_ROMSTAGE, base_multipler);
+ timestamp_add(TS_ROMSTAGE_START, base_multipler);
assert_int_equal(1, glob_ts_table->num_entries);
@@ -61,7 +61,7 @@
dummy_timestamp_set(base_multipler);
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
assert_int_equal(1, glob_ts_table->num_entries);