commit ad0f4853619b1c239b8ace7554958c6b4932c04f
author Martin Roth <martin@coreboot.org> Wed Oct 23 21:41:43 2019 -0600
committer Martin Roth <martinroth@google.com> Sun Oct 27 21:08:49 2019 +0000
tree 30aab33490fa6d6dacc17a0f1bac99f0554c8ea5
parent 38ddbfb325866716c9c65a460e388f33d1a773dd

src/mainboard: change "unsigned" to "unsigned int"

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I46d131f76ec930d2ef0f74e6eaabae067df10754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

src/mainboard/google/daisy/mainboard.c

diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c
index 46939b7..30f8805 100644
--- a/src/mainboard/google/daisy/mainboard.c
+++ b/src/mainboard/google/daisy/mainboard.c
@@ -330,9 +330,9 @@
 	mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
 	dcache_mmu_enable();
 
-	const unsigned epll_hz = 192000000;
-	const unsigned sample_rate = 48000;
-	const unsigned lr_frame_size = 256;
+	const unsigned int epll_hz = 192000000;
+	const unsigned int sample_rate = 48000;
+	const unsigned int lr_frame_size = 256;
 	clock_epll_set_rate(epll_hz);
 	clock_select_i2s_clk_source();
 	clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);