diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
index c7e9690..f09a27f 100644
--- a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
+++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
@@ -16,3 +16,4 @@
 H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex
 H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex
 MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex
+MT53D512M64D4NW-046 WT:F,lp4x-spd-1.hex
diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
index 91062d0..ffb08c7 100644
--- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
@@ -217,6 +217,18 @@
                 "ranksPerChannel": 1,
                 "speedMbps": 4267
             }
+        },
+        {
+            "name": "MT53D512M64D4NW-046 WT:F",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
         }
     ]
 }