src: use mca_clear_status function instead of open coding
Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56259
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 76c8521..9539c3d 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -15,9 +15,7 @@
static void model_14_init(struct device *dev)
{
- u8 i;
msr_t msr;
- unsigned int num_banks;
int msrno;
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
@@ -59,11 +57,7 @@
x86_enable_cache();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 883bd59..9d4da76 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -18,9 +18,7 @@
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
- u8 i;
msr_t msr;
- unsigned int num_banks;
int msrno;
unsigned int cpu_idx;
#if CONFIG(LOGICAL_CPUS)
@@ -58,11 +56,7 @@
x86_enable_cache();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index f945f80..9fadc7e 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -17,9 +17,7 @@
{
printk(BIOS_DEBUG, "Model 16 Init.\n");
- u8 i;
msr_t msr;
- unsigned int num_banks;
int msrno;
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
@@ -56,11 +54,7 @@
x86_enable_cache();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 3c78c09..a5a8064 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -20,9 +20,7 @@
{
printk(BIOS_DEBUG, "Model 16 Init.\n");
- u8 i;
msr_t msr;
- unsigned int num_banks;
u32 siblings;
/*
@@ -41,11 +39,7 @@
x86_mtrr_check();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 29c663e..2c6384c 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -527,12 +527,10 @@
for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC_CTL(i), msr);
- msr.lo = msr.hi = 0;
/* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears
* every bank. */
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
}
/* All CPUs including BSP will run the following function. */
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index fe5ac56..f70d7b2 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -73,24 +73,13 @@
((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK);
}
-static void configure_mca(void)
-{
- msr_t msr;
- int i;
- const unsigned int num_banks = mca_get_bank_count();
-
- msr.lo = msr.hi = 0;
- /* This should only be done on a cold boot */
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
-}
-
static void model_2065x_init(struct device *cpu)
{
char processor_name[49];
/* Clear out pending MCEs */
- configure_mca();
+ /* This should only be done on a cold boot */
+ mca_clear_status();
/* Print processor name */
fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 541cb3b..09cad24 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -297,18 +297,6 @@
return SANDYBRIDGE_BCLK;
}
-static void configure_mca(void)
-{
- msr_t msr;
- int i;
- const unsigned int num_banks = mca_get_bank_count();
-
- msr.lo = msr.hi = 0;
- /* This should only be done on a cold boot */
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
-}
-
static void model_206ax_report(void)
{
static const char *const mode[] = {"NOT ", ""};
@@ -340,7 +328,8 @@
{
/* Clear out pending MCEs */
- configure_mca();
+ /* This should only be done on a cold boot */
+ mca_clear_status();
/* Print infos */
model_206ax_report();