diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
index 0ff7585..1944b32 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
@@ -78,7 +78,7 @@
   IN OUT   UINT8                HtcCapable;                  ///< Htc capable
   IN OUT   UINT8                LocalApicId;                 ///< Local Apic Id
   IN OUT   UINT8                NumberOfBoostedStates;       ///< Number of boost P-states
-  IN OUT   S_PSTATE_VALUES      PStateStruct[1];             ///< P state struc
+  IN OUT   S_PSTATE_VALUES      PStateStruct[];              ///< P state struc
 } S_PSTATE;
 
 /// P-state structure for each node
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c
index d11ee6d..444ef2c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c
@@ -248,9 +248,10 @@
   //Calculate next node buffer address
   //
   PStateBufferPtr->SocketNumber = (UINT8) BscSocket;
-  PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
-  PStateStrucPtr->SizeOfBytes += (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES));
-  PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  MaxState = PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue;
+  PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (MaxState + 1) * sizeof (S_PSTATE_VALUES));
+  PStateStrucPtr->SizeOfBytes += (MaxState + 1) * sizeof (S_PSTATE_VALUES);
+  PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + PStateBufferPtr->PStateLevelingSizeOfBytes);
   CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader);
   //
   //Get CPU P-States and fill the PStateBufferPtr for each node(BSC)
@@ -266,9 +267,10 @@
         //
         //Calculate next node buffer address
         //
-        PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+        MaxState = PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue;
+        PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (MaxState + 1) * sizeof (S_PSTATE_VALUES));
         PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes;
-        PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+        PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + PStateBufferPtr->PStateLevelingSizeOfBytes);
       }
     }
   }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
index 81af491..59b02d5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
@@ -79,7 +79,7 @@
   IN OUT   UINT8                HtcPstateLimit;              ///< Htc limit
   IN OUT   UINT8                HtcCapable;                  ///< Htc capable
   IN OUT   UINT8                LocalApicId;                 ///< Local Apic Id
-  IN OUT   S_PSTATE_VALUES      PStateStruct[1];             ///< P state struc
+  IN OUT   S_PSTATE_VALUES      PStateStruct[];              ///< P state struc
 } S_PSTATE;
 
 /// P-state structure for each node
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
index b75ea3e..95768d2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
@@ -78,7 +78,7 @@
   IN OUT   UINT8                HtcCapable;                  ///< Htc capable
   IN OUT   UINT8                LocalApicId;                 ///< Local Apic Id
   IN OUT   UINT8                NumberOfBoostedStates;       ///< Number of boost P-states
-  IN OUT   S_PSTATE_VALUES      PStateStruct[1];             ///< P state struc
+  IN OUT   S_PSTATE_VALUES      PStateStruct[];              ///< P state struc
 } S_PSTATE;
 
 /// P-state structure for each node
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
index 9ccacb4..a01845e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
@@ -78,7 +78,7 @@
   IN OUT   UINT8                HtcCapable;                  ///< Htc capable
   IN OUT   UINT8                LocalApicId;                 ///< Local Apic Id
   IN OUT   UINT8                NumberOfBoostedStates;       ///< Number of boost P-states
-  IN OUT   S_PSTATE_VALUES      PStateStruct[1];             ///< P state struc
+  IN OUT   S_PSTATE_VALUES      PStateStruct[];              ///< P state struc
 } S_PSTATE;
 
 /// P-state structure for each node