intel/haswell,lynxpoint: Fix out() parameter order
Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index e1b8b730..6e6948b 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -408,7 +408,7 @@
/* Clear DMISCI status */
reg16 = inw(get_pmbase() + TCO1_STS);
reg16 &= DMISCI_STS;
- outw(get_pmbase() + TCO1_STS, reg16);
+ outw(reg16, get_pmbase() + TCO1_STS);
/* Clear and enable ACPI TCO SCI */
enable_tco_sci();
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 8117b4d..dd7f199 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -356,7 +356,7 @@
u16 gpe0_sts = pch_is_lp() ? LP_GPE0_STS_4 : GPE0_STS;
/* Clear pending events */
- outl(get_pmbase() + gpe0_sts, TCOSCI_STS);
+ outl(TCOSCI_STS, get_pmbase() + gpe0_sts);
/* Enable TCO SCI events */
enable_gpe(TCOSCI_EN);