amd/southbridge/lpc: SPI BAR has fixed size/location
The CIMX sb700/sb800/sb900 and agesa/hudson code was treating
the LPC SPI BAR as a normal PCI BAR. This will set the
resources for a fixed size at a fixed address. This was tested
on hp/abm, amd/persimmon, and gizmosphere/gizmo boards.
Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5947
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index a1e0dc9..519e3c1 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -33,8 +34,6 @@
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
- pci_get_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); /* SPI ROM base address */
-
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
@@ -48,6 +47,9 @@
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ /* Add a memory resource for the SPI BAR. */
+ fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
+
res = new_resource(dev, 3);
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
@@ -64,8 +66,8 @@
printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n");
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
- res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER);
- res->base |= PCI_COMMAND_MEMORY;
+ res = find_resource(dev, 2);
+ pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev);