soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BP
The patch triggeres CrOS recovery mode if the sizes of CSE CBFS RW blob
and CSE RW boot are different.
TEST=Verified on drawcia.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48423
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index eb4be6e..8e89723 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -74,6 +74,9 @@
/* CSE CBFS RW metadata is not found */
CSE_LITE_SKU_RW_METADATA_NOT_FOUND = 10,
+
+ /* CSE CBFS RW blob layout is not correct */
+ CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR = 11,
};
/*
@@ -674,6 +677,11 @@
const void *cse_cbfs_rw, const size_t cse_blob_sz,
struct region_device *target_rdev)
{
+ if (region_device_sz(target_rdev) < cse_blob_sz) {
+ printk(BIOS_ERR, "RW update does not fit. CSE RW flash region size: %zx, Update blob size:%zx\n",
+ region_device_sz(target_rdev), cse_blob_sz);
+ return CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR;
+ }
if (!cse_erase_rw_region(target_rdev))
return CSE_LITE_SKU_FW_UPDATE_ERROR;