commit ab87254b6130d74f080e2c5ee9abb4570560e6a0
author Stefan Reinauer <reinauer@chromium.org> Fri Oct 14 15:18:29 2011 -0700
committer Uwe Hermann <uwe@hermann-uwe.de> Sat Oct 15 12:30:02 2011 +0200
tree 8e239c8b64b9f2177a953f9ead4b41421831c00c
parent 2d172993953ae777aaec13efddfe6ed91209bd02

use acpi.h include instead of manually adding acpi_slp_type.

Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/276
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

src/northbridge/intel/i945/northbridge.c

diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index dfe4fe7..a10bb4a 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -29,6 +29,7 @@
 #include <bitops.h>
 #include <cpu/cpu.h>
 #include <boot/tables.h>
+#include <arch/acpi.h>
 #include "chip.h"
 #include "i945.h"
 
@@ -252,8 +253,6 @@
 }
 
 #if CONFIG_HAVE_ACPI_RESUME
-extern u8 acpi_slp_type;
-
 static void northbridge_init(struct device *dev)
 {
 	switch (pci_read_config32(dev, SKPAD)) {

src/northbridge/intel/sch/northbridge.c

diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index ccd0d33..7b7c67b 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -29,6 +29,7 @@
 #include <bitops.h>
 #include <cpu/cpu.h>
 #include <boot/tables.h>
+#include <arch/acpi.h>
 #include "chip.h"
 #include "sch.h"
 
@@ -267,8 +268,6 @@
 }
 
 #if CONFIG_HAVE_ACPI_RESUME
-extern u8 acpi_slp_type;
-
 static void northbridge_init(struct device *dev)
 {
 	switch (pci_read_config32(dev, SKPAD)) {

src/southbridge/intel/i82801gx/lpc.c

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index b4b2f41..ab3c915 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -27,6 +27,7 @@
 #include <pc80/i8259.h>
 #include <arch/io.h>
 #include <arch/ioapic.h>
+#include <arch/acpi.h>
 #include <cpu/cpu.h>
 #include "i82801gx.h"
 #include <cpu/x86/smm.h>
@@ -170,8 +171,6 @@
 	pci_write_config32(dev, 0xb8, reg32);
 }
 
-extern u8 acpi_slp_type;
-
 static void i82801gx_power_options(device_t dev)
 {
 	u8 reg8;

src/southbridge/via/vt8237r/lpc.c

diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 61f4989..3e2f215 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -32,6 +32,7 @@
 #include <pc80/keyboard.h>
 #include <pc80/i8259.h>
 #include <stdlib.h>
+#include <arch/acpi.h>
 #include "vt8237r.h"
 #include "chip.h"
 
@@ -147,9 +148,6 @@
  * This avoids having to handle any System Management Interrupts (SMIs).
  */
 
-extern u8 acpi_slp_type;
-
-
 static void setup_pm(device_t dev)
 {
 	u16 tmp;