| commit | ab1b606fd485f26563ec8fb4c84bf22c13b65a02 | [log] [tgz] |
|---|---|---|
| author | Felix Held <felix-coreboot@felixheld.de> | Tue May 25 20:53:19 2021 +0200 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Thu May 27 15:39:30 2021 +0000 |
| tree | c83532e515521c0d878fa1f80b7166f8f0716784 | |
| parent | a7c410b28602e337a85466429540663a7f3a219a [diff] |
mb/amd/majolica: set PSPP policy to balanced BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 0f540a1..8f4fc9b 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb
@@ -15,6 +15,8 @@ register "s0ix_enable" = "true" + register "pspp_policy" = "DXIO_PSPP_BALANCED" + device domain 0 on device ref gpp_gfx_bridge_0 on end # MXM device ref gpp_bridge_0 on end # NVMe