tree efbede7d3cdca01ef63870d8c82b762e65ee8510
parent 2183484e7aefdd576d01342ba4a7db74b480e8a3
author Jianjun Wang <jianjun.wang@mediatek.com> 1648021136 +0800
committer Paul Fagerburg <pfagerburg@chromium.org> 1648568510 +0000

soc/mediatek: Ensure PERST# deassertion time follows the spec

According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. To ensure the 100ms
delay requirement is met, calculate the elapsed time since assertion. If
it is smaller than 100ms, do an extra delay.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the measured PERST# time:
[DEBUG]  mtk_pcie_domain_enable: 432517 us elapsed since assert PERST#
[INFO ]  mtk_pcie_domain_enable: PCIe link up success (17 tries)

And the SSD information in boot log is as follows:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>