Gitiles
Code Review Sign In
review.coreboot.org / coreboot / a9efed5fd90534b20b6739fa24e5a6339f67b827
commita9efed5fd90534b20b6739fa24e5a6339f67b827[log] [tgz]
authorPaul Menzel <pmenzel@molgen.mpg.de>Tue May 18 21:38:27 2021 +0200
committerPatrick Georgi <pgeorgi@google.com>Thu May 20 08:00:54 2021 +0000
tree4bf0cff5267a8e7291abb468a94bcabdfc101710
parent650bf6550500a726f580e9ed9e3b646919f0e82a [diff]
mb/asus/f2a85-m_pro: Set resources for 2e.b

The v4 resource allocator logs the error below:

    […]
    === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
    DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
     update_constraints: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
     update_constraints: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
     update_constraints: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
     update_constraints: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
     update_constraints: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
     DOMAIN: 0000: Resource ranges:
     * Base: 1000, Size: f000, Tag: 100
      PCI: 00:01.0 14 *  [0x1000 - 0x10ff] limit: 10ff io
      PCI: 00:11.0 20 *  [0x1100 - 0x110f] limit: 110f io
      PCI: 00:11.0 10 *  [0x1110 - 0x1117] limit: 1117 io
      PCI: 00:11.0 18 *  [0x1118 - 0x111f] limit: 111f io
      PCI: 00:11.0 14 *  [0x1120 - 0x1123] limit: 1123 io
      PCI: 00:11.0 1c *  [0x1124 - 0x1127] limit: 1127 io
      ERROR: Resource didn't fit!!!   PNP: 002e.b 62 *  size: 0x2 limit: fff io
    DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
    […]
    === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
    […]
    PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
    PNP: 002e.b e2 <- [0x000000007f - 0x000000007e] size 0x00000000 gran 0x00 irq
    PNP: 002e.b e4 <- [0x00000000f1 - 0x00000000f0] size 0x00000000 gran 0x00 irq
    ERROR: PNP: 002e.b 62 io size: 0x0000000002 not assigned in devicetree
    ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree
    WARNING: PNP: 002e.b f0 irq size: 0x0000000001 not assigned in devicetree
    […]

So configure it, to use the resources from port 0.

TEST=With CB:54669 boot Asus F2A85-M PRO to SeaBIOS/GRUB and Debian’s
Linux 5.10.28
Solution-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: Ibfedca96e4b5ad17f99bc84e2fbf7d0a6aad4484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54670
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1 file changed
tree: 4bf0cff5267a8e7291abb468a94bcabdfc101710
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.