- First stab at getting the ppc ports building and working.
- The sandpointx3+altimus has been consolidated into one directory for now.
- Added support for having different versions of the pci access functions
on a per bus basis if needed.
Hopefully I have not broken something inadvertently.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/devices/Config.lb b/src/devices/Config.lb
index 80b64a0..12a3109 100644
--- a/src/devices/Config.lb
+++ b/src/devices/Config.lb
@@ -4,3 +4,4 @@
object pci_device.o
object pnp_device.o
object hypertransport.o
+object pci_ops.o
diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index fd8fdcf..6af2d37 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -114,9 +114,6 @@
case DEVICE_PATH_ROOT:
memcpy(buffer, "Root Device", 12);
break;
- case DEVICE_PATH_DEFAULT_CPU:
- memcpy(buffer, "Default CPU", 12);
- break;
case DEVICE_PATH_PCI:
sprintf(buffer, "PCI: %02x:%02x.%01x",
dev->bus->secondary,
@@ -142,6 +139,12 @@
sprintf(buffer, "APIC_CLUSTER: %01x",
dev->path.u.apic_cluster.cluster);
break;
+ case DEVICE_PATH_CPU:
+ sprintf(buffer, "CPU: %02x", dev->path.u.cpu.id);
+ break;
+ case DEVICE_PATH_CPU_BUS:
+ sprintf(buffer, "CPU_BUS: %02x", dev->path.u.cpu_bus.id);
+ break;
default:
printk_err("Unknown device path type: %d\n", dev->path.type);
break;
@@ -160,9 +163,6 @@
case DEVICE_PATH_ROOT:
equal = 1;
break;
- case DEVICE_PATH_DEFAULT_CPU:
- equal = 1;
- break;
case DEVICE_PATH_PCI:
equal = (path1->u.pci.devfn == path2->u.pci.devfn);
break;
@@ -182,6 +182,12 @@
case DEVICE_PATH_APIC_CLUSTER:
equal = (path1->u.apic_cluster.cluster == path2->u.apic_cluster.cluster);
break;
+ case DEVICE_PATH_CPU:
+ equal = (path1->u.cpu.id == path2->u.cpu.id);
+ break;
+ case DEVICE_PATH_CPU_BUS:
+ equal = (path1->u.cpu_bus.id == path2->u.cpu_bus.id);
+ break;
default:
printk_err("Uknown device type: %d\n", path1->type);
break;
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 1c8c8be..bd5e277 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -480,7 +480,7 @@
void pci_dev_enable_resources(struct device *dev)
{
- struct pci_operations *ops;
+ const struct pci_operations *ops;
uint16_t command;
/* Set the subsystem vendor and device id for mainboard devices */
@@ -515,6 +515,7 @@
enable_childrens_resources(dev);
}
+
void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -522,7 +523,7 @@
}
/** Default device operation for PCI devices */
-static struct pci_operations pci_ops_pci_dev = {
+static struct pci_operations pci_dev_ops_pci = {
.set_subsystem = pci_dev_set_subsystem,
};
@@ -533,11 +534,11 @@
.init = 0,
.scan_bus = 0,
.enable = 0,
- .ops_pci = &pci_ops_pci_dev,
+ .ops_pci = &pci_dev_ops_pci,
};
/** Default device operations for PCI bridges */
-static struct pci_operations pci_ops_pci_bus = {
+static struct pci_operations pci_bus_ops_pci = {
.set_subsystem = 0,
};
struct device_operations default_pci_ops_bus = {
@@ -547,7 +548,7 @@
.init = 0,
.scan_bus = pci_scan_bridge,
.enable = 0,
- .ops_pci = &pci_ops_pci_bus,
+ .ops_pci = &pci_bus_ops_pci,
};
/**
@@ -857,6 +858,7 @@
uint16_t cr;
bus = &dev->link[0];
+ bus->dev = dev;
dev->links = 1;
/* Set up the primary, secondary and subordinate bus numbers. We have
diff --git a/src/devices/pci_ops.c b/src/devices/pci_ops.c
new file mode 100644
index 0000000..441b328
--- /dev/null
+++ b/src/devices/pci_ops.c
@@ -0,0 +1,55 @@
+#include <console/console.h>
+#include <arch/pciconf.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static struct bus *get_pbus(device_t dev)
+{
+ struct bus *pbus = dev->bus;
+ while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
+ pbus = pbus->dev->bus;
+ }
+ if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) {
+ printk_alert("%s Cannot find pci bus operations", dev_path(dev));
+ die("");
+ for(;;);
+ }
+ return pbus;
+}
+
+uint8_t pci_read_config8(device_t dev, unsigned where)
+{
+ struct bus *pbus = get_pbus(dev);
+ return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, dev->path.u.pci.devfn, where);
+}
+
+uint16_t pci_read_config16(device_t dev, unsigned where)
+{
+ struct bus *pbus = get_pbus(dev);
+ return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, dev->path.u.pci.devfn, where);
+}
+
+uint32_t pci_read_config32(device_t dev, unsigned where)
+{
+ struct bus *pbus = get_pbus(dev);
+ return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, dev->path.u.pci.devfn, where);
+}
+
+void pci_write_config8(device_t dev, unsigned where, uint8_t val)
+{
+ struct bus *pbus = get_pbus(dev);
+ ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, dev->path.u.pci.devfn, where, val);
+}
+
+void pci_write_config16(device_t dev, unsigned where, uint16_t val)
+{
+ struct bus *pbus = get_pbus(dev);
+ ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, dev->path.u.pci.devfn, where, val);
+}
+
+void pci_write_config32(device_t dev, unsigned where, uint32_t val)
+{
+ struct bus *pbus = get_pbus(dev);
+ ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, dev->path.u.pci.devfn, where, val);
+}