tree 288b5c44bc23c7f5cb25fd822a0f4088f5c0f865
parent a50f190fd4f9392f85bbeee53114cb054ad047cc
author Rizwan Qureshi <rizwan.qureshi@intel.com> 1617894107 +0530
committer Patrick Georgi <pgeorgi@google.com> 1618996798 +0000

soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC

CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config
is for the number of PCIe Clock sources available which is different from PCIe clock reqs.
This is more relevant in alderlake, as the number clock source and clock reqs differ.
However since this is a better name, renaming it throughout the soc/intel tree.

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>