tree d1510f3466bc3905ecdb89d3e1999934a31c07ea
parent 4dfdce4223e9689d230809b64178af4af60b0dd6
author Sridhar Siricilla <sridhar.siricilla@intel.com> 1596624412 +0530
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1597253989 +0000

soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress

The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between
coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address
for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR
address is overridden with 0xfed1a000. This causes HECI transactions to
fail between FSP-M call and postcar.

BRANCH=puff
TEST=Verified sending HECI commands before and after FSP-M call on hatch.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>