| commit | a913b3df90da925246936cb421afe01901172211 | [log] [tgz] |
|---|---|---|
| author | Furquan Shaikh <furquan@google.com> | Sat Jul 06 22:09:28 2019 -0700 |
| committer | Patrick Georgi <pgeorgi@google.com> | Sun Jul 07 07:51:24 2019 +0000 |
| tree | e31bcebc543bf13b61483c5cfbb9bce5ae11547b | |
| parent | db6c3f25f0d4b7fc0fd7aefb0b2442584a7f2c99 [diff] |
soc/intel/cannonlake: Use SA_DEV_ROOT instead of PCH_DEV_PMC
PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets
removed from the root bus as leftover unused device. With change
903b40a8a46 ("soc/intel: Replace uses of dev_find_slot()"), all uses
of dev_find_slot() were replaced by pcidev_path_on_root() which relies
on scanning of root bus to find the requested device. Since PMC device
is removed from the root bus, pcidev_path_on_root() returns NULL for
it thus resulting in configuration being skipped for the PMC
ultimately resulting in S3 failures.
Since the PCH_DEV_PMC was just used to get to chip config, this change
replaces the use of PCH_DEV_PMC with SA_DEV_ROOT.
BUG=b:136861224
TEST=Verified that S3 works fine on hatch.
Change-Id: Ie5ade00ac2aca697608f1bdea9764b71c26e2112
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
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https://www.coreboot.org/Mailinglist
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coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.