This patch contains some significant updates to the i82801gx component and will
be required for a series of later patches. Roughly it contains:
* fixed SMBus driver (was not compiled in before)
* fixed S-ATA/P-ATA combination
* Added warnings to drivers being called with a NULL dev->chip_info
* Set subsystem ids for those boards that have none specified in Options.lb
* Fix license headers. The code was originally released under GPL v2 but
some files sneaked in with a v2 or later header.
* some attempts to fix azalia/Intel HDA.. not working yet
* clean up and fix pci bridge handling code
* Add Config based GPI handling to LPC driver
* Add HPET enable function
* Enable clock gating where appropriate
* first attempt at USB debug console support (not working yet)
* Add required options to kontron board
* many other minor changes
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c
index b2e4ce5..2bf228b 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pci.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c
@@ -3,10 +3,10 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -26,31 +26,42 @@
static void pci_init(struct device *dev)
{
u16 reg16;
+ u8 reg8;
-#if 0
- /* Commented out for now because it will break on some machines. */
- /* Set latency timer to 32. */
- pci_write_config16(dev, 0x1b, 0x20);
-#endif
+ /* Enable Bus Master */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MASTER;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
- /* disable parity error response */
+ /* This device has no interrupt */
+ pci_write_config8(dev, 0x3c, 0xff);
+
+ /* disable parity error response and SERR */
reg16 = pci_read_config16(dev, 0x3e);
reg16 &= ~(1 << 0);
+ reg16 &= ~(1 << 1);
pci_write_config16(dev, 0x3e, reg16);
- /* Clear errors in status registers */
- reg16 = pci_read_config16(dev, 0x06);
- reg16 |= 0xf900;
- pci_write_config16(dev, 0x06, reg16);
-
- reg16 = pci_read_config16(dev, 0x1e);
- reg16 |= 0xf900;
- pci_write_config16(dev, 0x1e, reg16);
+ /* Master Latency Count must be set to 0x04! */
+ reg8 = pci_read_config8(dev, 0x1b);
+ reg8 &= 0x07;
+ reg8 |= (0x04 << 3);
+ pci_write_config8(dev, 0x1b, reg8);
/* Will this improve throughput of bus masters? */
pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+
+ /* Clear errors in status registers */
+ reg16 = pci_read_config16(dev, 0x06);
+ //reg16 |= 0xf900;
+ pci_write_config16(dev, 0x06, reg16);
+
+ reg16 = pci_read_config16(dev, 0x1e);
+ // reg16 |= 0xf900;
+ pci_write_config16(dev, 0x1e, reg16);
}
+#undef PCI_BRIDGE_UPDATE_COMMAND
static void ich_pci_dev_enable_resources(struct device *dev)
{
const struct pci_operations *ops;
@@ -68,15 +79,17 @@
MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
}
-#if 0
+ command = pci_read_config16(dev, PCI_COMMAND);
+ command |= dev->command;
+#if PCI_BRIDGE_UPDATE_COMMAND
/* If we write to PCI_COMMAND, on some systems
* this will cause the ROM and APICs not being visible
* anymore.
*/
- command = pci_read_config16(dev, PCI_COMMAND);
- command |= dev->command;
printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
+#else
+ printk_debug("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
#endif
}
@@ -102,16 +115,14 @@
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
-#if 0
- /* Currently disabled because it causes a "BAR 9" memory resource
- * conflict:
- */
- u32 pci_id;
-
- printk_debug("Setting PCI bridge subsystem ID\n");
- pci_id = pci_read_config32(dev, 0);
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_id );
-#endif
+ /* NOTE: This is not the default position! */
+ if (!vendor || !device) {
+ pci_write_config32(dev, 0x54,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, 0x54,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
}
static struct pci_operations pci_ops = {