soc/amd/stoneyridge: drop empty sb_enable
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50437
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 9cae98b..f63a7c3 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -112,9 +112,6 @@
case DEVICE_PATH_CPU_CLUSTER:
dev->ops = &cpu_bus_ops;
break;
- case DEVICE_PATH_PCI:
- sb_enable(dev);
- break;
case DEVICE_PATH_MMIO:
if (i2c_acpi_name(dev) != NULL)
dev->ops = &stoneyridge_i2c_mmio_ops;
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 219af84..9480e8b 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -238,7 +238,6 @@
void enable_aoac_devices(void);
void sb_clk_output_48Mhz(u32 osc);
-void sb_enable(struct device *dev);
void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index f8a705e..161e3e8 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -352,11 +352,6 @@
fch_print_pmxc0_status();
}
-void sb_enable(struct device *dev)
-{
- printk(BIOS_DEBUG, "%s\n", __func__);
-}
-
static void fch_init_acpi_ports(void)
{
u32 reg;