commit a8c6c7f30c2793aff4f1ab8d01954bbaced2b4ae
author Timothy Pearson <tpearson@raptorengineeringinc.com> Thu Aug 13 17:45:12 2015 -0500
committer Martin Roth <martinroth@google.com> Mon Nov 23 23:03:34 2015 +0100
tree dd20b8c966d844d7dd86818069e2067557a022c5
parent 44e4a4e4db23677c960591d3209004f4f8b80326

southbridge/amd/sr5650: Hide clock configuration device after setup is complete

Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12045
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/southbridge/amd/sr5650/early_setup.c

diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 95e6ebf..1fc0427 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -410,14 +410,14 @@
 	set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310);
 
 	/* NBCFG (NBMISCIND 0x0): NB_CNTL -
-	 *   HIDE_NB_AGP_CAP  ([0], default=1)HIDE
-	 *   HIDE_P2P_AGP_CAP ([1], default=1)HIDE
-	 *   HIDE_NB_GART_BAR ([2], default=1)HIDE
-	 *   HIDE_MMCFG_BAR   ([3], default=1)SHOW
-	 *   AGPMODE30        ([4], default=0)DISABLE
-	 *   AGP30ENCHANCED   ([5], default=0)DISABLE
-	 *   HIDE_AGP_CAP     ([8], default=1)ENABLE */
-	set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6);
+	 *   HIDE_NB_AGP_CAP    ([0], default=1)HIDE
+	 *   HIDE_P2P_AGP_CAP   ([1], default=1)HIDE
+	 *   HIDE_NB_GART_BAR   ([2], default=1)HIDE
+	 *   HIDE_MMCFG_BAR     ([3], default=1)SHOW
+	 *   AGPMODE30          ([4], default=0)DISABLE
+	 *   AGP30ENCHANCED     ([5], default=0)DISABLE
+	 *   HIDE_CLKCFG_HEADER ([8], default=0)SHOW */
+	set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6 | 0 << 8);
 
 	/* IOC_LAT_PERF_CNTR_CNTL */
 	set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00);