tree 4dc85ef4557f4f79360dc610645139d2e685c40a
parent c7762466b3027396dd07cd79999bae26a70885eb
author Julius Werner <jwerner@chromium.org> 1614214697 -0800
committer Patrick Georgi <pgeorgi@google.com> 1614327508 +0000

rk3399: clock: Fix style for rkclk_ddr_reset()

This function should be using the RK_CLRSETBITS() macros to access the
special Rockchip write-mask registers, like the rest of our code. Also,
there were already existing bit field definitions for these bits that
should be used (although it makes sense to adjust them a bit to allow
passing in the channel number).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If1f5c06aabb16045d890df3bbd271f08a2cdf390
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51080
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>