Use more secure HTTPS URLs for coreboot sites
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/Documentation/CorebootBuildingGuide.tex b/Documentation/CorebootBuildingGuide.tex
index eb4dfd2..f18cc18 100644
--- a/Documentation/CorebootBuildingGuide.tex
+++ b/Documentation/CorebootBuildingGuide.tex
@@ -116,15 +116,15 @@
For users who doesn't need to change and commit the code:
{ \small
\begin{verbatim}
-$ git clone http://review.coreboot.org/p/coreboot
+$ git clone https://review.coreboot.org/p/coreboot
\end{verbatim}
}
For developers, you need to get a gerrit account which you can register
-at \url{http://review.coreboot.org}. Please refer section ~\ref{sec:gerrit}
+at \url{https://review.coreboot.org}. Please refer section ~\ref{sec:gerrit}
{ \small
\begin{verbatim}
$ git clone ssh://<username>@review.coreboot.org:29418/coreboot
-$ git clone http://[<username>:<password>@]review.coreboot.org/coreboot.git
+$ git clone https://[<username>:<password>@]review.coreboot.org/coreboot.git
\end{verbatim}
}
@@ -463,7 +463,7 @@
If you are a coreboot user, not planning to contribute, you can skip this section.
\subsection{Get gerrit account}
You need to get an OpenID first. Currently Google account give you an OpenID. It means, if you have a gmail account, you have an OpenID. You can try to signed in.
-click \url{http://review.coreboot.org}
+click \url{https://review.coreboot.org}
%\includegraphics[width=6.00in,height=1.00in]{gerrit_signin.png}
{ \small
@@ -655,7 +655,7 @@
\begin{itemize}
\item
- \textit{\url{http://www.coreboot.org/Documentation}}
+ \textit{\url{https://www.coreboot.org/Documentation}}
\end{itemize}
\subsection {Links}
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html
index 1b2d323..489d802 100644
--- a/Documentation/Intel/Board/board.html
+++ b/Documentation/Intel/Board/board.html
@@ -161,20 +161,20 @@
<ol type="A">
<li>0x34:
- Just after entering
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
</li>
<li>0x36:
- Just before displaying the
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
for FSP MemoryInit
</li>
- <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
+ <li>0x92: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
- Just before calling FSP
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
</li>
<li>0x37:
- Just after returning from FSP
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
</li>
</ol>
</li>
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 8f1d75c..6f6d630 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -108,11 +108,11 @@
When the reset vector is successfully invoked, port 0x80 will output the following value:
</p>
<ul>
- <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
+ <li>0x01: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
- Bootblock successfully executed the
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
and entered the 16-bit code at
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
</li>
</ul>
@@ -154,15 +154,15 @@
<li>Add the necessary .h files to define the necessary values and structures</li>
<li>When successful port 0x80 will output the following values:
<ol type="A">
- <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
+ <li>0x01: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
- Bootblock successfully executed the
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
and entered the 16-bit code at
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
</li>
- <li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a>
+ <li>0x10: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a>
- Bootblock executing in
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a>
</li>
<li>0x10 - Verstage/romstage reached 32-bit mode</li>
</ol>
@@ -173,26 +173,26 @@
<b>Build Note:</b> The following files are included into the default bootblock image:
</p>
<ul>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a>
- added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a>
+ added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
and includes the following files:
<ul>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li>
<li>The code in
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a>
includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the
CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
</li>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li>
<li>The code in
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a>
invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
<ul>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li>
<li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in
src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c
</li>
@@ -200,14 +200,14 @@
</li>
</ul>
</li>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a>
- added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a>
+ added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
</li>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a>
- added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a>
+ added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
</li>
- <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a>
- added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
+ <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a>
+ added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
</li>
</ul>
@@ -231,19 +231,19 @@
<li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
<ol type="A">
<li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
</li>
<li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
specifically building
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a>
</li>
</ol>
</li>
<li>Debug the result until port 0x80 outputs
<ol type="A">
- <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
+ <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
- Just before calling
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
</li>
<li>Alternating 0xba and 0x01 - The FSP image was not found</li>
</ol>
@@ -257,9 +257,9 @@
</li>
<li>Debug the result until port 0x80 outputs
<ol type="A">
- <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
+ <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
- Just before calling
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
</li>
<li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li>
</ol>
@@ -287,12 +287,12 @@
</li>
<li>Debug the result until port 0x80 outputs
<ol type="A">
- <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
+ <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
- Just before calling
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
</li>
<li>0x2A - Just before calling
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">cache_as_ram_main</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">cache_as_ram_main</a>
which is the start of the verstage code which may be part of romstage
</li>
</ol>
@@ -349,14 +349,14 @@
<ol type="A">
<li>0x32:
- Just after entering
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l99">romstage_common</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l99">romstage_common</a>
</li>
<li>0x33 - Just after calling
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l113">soc_pre_ram_init</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l113">soc_pre_ram_init</a>
</li>
<li>0x34:
- Just after entering
- <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
</li>
</ol>
</ol>
@@ -410,7 +410,7 @@
execution during ramstage. This file is processed by the util/sconfig utility
to generate build/mainboard/<Vendor>/<Board>/static.c. The various
state routines in
- src/lib/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwaremain.c;hb=HEAD#l128">hardwaremain.c</a>
+ src/lib/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwaremain.c;hb=HEAD#l128">hardwaremain.c</a>
call dev_* routines which use the tables in static.c to locate operation tables
associated with the various chips and devices. After location the operation
tables, the state routines call one or more functions depending upon the
@@ -540,7 +540,7 @@
BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically
specify the DRAM resources while the other drivers will typically specify
the IO resources. These resources are hung off the device_t data structure by
- src/device/device_util.c/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>.
+ src/device/device_util.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>.
</p>
<p>
During the BS_WRITE_TABLES state, coreboot collects these resources and
@@ -552,7 +552,7 @@
<ol>
<li>
Implement a read_resources routine which calls macros defined in
- src/include/device/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/device/device.h;hb=HEAD#l237">device.h</a>
+ src/include/device/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/device/device.h;hb=HEAD#l237">device.h</a>
like:
<ul>
<li>ram_resource</li>
@@ -661,7 +661,7 @@
The EDK2 data structure is defined in
MdeModulePkg/Include/IndustryStandard/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandard/Acpi61.h#l111">Acpi61.h</a>
The coreboot data structure is defined in
- src/arch/x86/include/arch/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/acpi.h;hb=HEAD#l237">acpi.h</a>
+ src/arch/x86/include/arch/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/acpi.h;hb=HEAD#l237">acpi.h</a>
</p>
<ol>
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index a2ba278..24b2fa9 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -170,7 +170,7 @@
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
</td>
<td>FindFSP: POST code 0x90
- (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
+ (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
is displayed<br>
Enable: POST code
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
@@ -303,7 +303,7 @@
<td>TempRamInit</td>
<td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td>
<td>FSP binary found: POST code 0x90
- (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
+ (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
is displayed<br>
TempRamInit successful: POST code
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
@@ -332,7 +332,7 @@
</tr>
<tr>
<td>TempRamExit</td>
- <td>src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
+ <td>src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
<td>Post code 0x91
(<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>)
is displayed before calling TempRamExit by
@@ -354,7 +354,7 @@
<td>FspNotify</td>
<td>
The code which calls FspNotify is located in
- src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
+ src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
The fsp_notify_boot_state_callback routine is called three times as specified
by the BOOT_STATE_INIT_ENTRY macros below the routine.
</td>
diff --git a/Documentation/gerrit_guidelines.md b/Documentation/gerrit_guidelines.md
index 1833b0a..cf7d5e8 100644
--- a/Documentation/gerrit_guidelines.md
+++ b/Documentation/gerrit_guidelines.md
@@ -41,7 +41,7 @@
you wrote that might be owned by your employer, make sure that your
employer is aware and you are authorized to submit the code. For
clarification, see the Developer's Certificate of Origin in the coreboot
-[Signed-off-by policy](http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
+[Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
* Let non-trivial patches sit in a review state for at least 24 hours
before submission. Remember that there are coreboot developers in timezones
@@ -205,7 +205,7 @@
the files that you’ve changed, and add those people.
* Familiarize yourself with the coreboot [commit message
-guidelines](http://www.coreboot.org/Git#Commit_messages), before pushing
+guidelines](https://www.coreboot.org/Git#Commit_messages), before pushing
patches. This will help to keep annoying requests to fix your commit
message to a minimum.
diff --git a/MAINTAINERS b/MAINTAINERS
index 32c72f6..b9adc25 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -35,7 +35,7 @@
PLEASE check your patch with the automated style checker
(util/lint/checkpatch.pl) to catch trival style violations.
- See http://coreboot.org/Coding_Style for guidance here.
+ See https://coreboot.org/Coding_Style for guidance here.
PLEASE add the maintainers that are generated by
util/scripts/get_maintainer.pl as reviewers. The results returned
@@ -54,7 +54,7 @@
of the OSDL certificate of contribution and should include a
Signed-off-by: line. The current version of this "Developer's
Certificate of Origin" (DCO) is listed at
- http://coreboot.org/Development_Guidelines#Sign-off_Procedure.
+ https://coreboot.org/Development_Guidelines#Sign-off_Procedure.
6. Make sure you have the right to send any changes you make. If you
do changes at work you may find your employer owns the patch
@@ -517,7 +517,7 @@
THE REST
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
-T: git http://review.coreboot.org/coreboot
+T: git https://review.coreboot.org/coreboot
S: Buried alive in mainboards
F: *
F: */
diff --git a/Makefile.inc b/Makefile.inc
index 99110ed..2f230ca 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -479,7 +479,7 @@
$(ROMCC_BIN): $(top)/util/romcc/romcc.c
@printf " HOSTCC $(subst $(obj)/,,$(@)) (this may take a while)\n"
@# Note: Adding -O2 here might cause problems. For details see:
- @# http://www.coreboot.org/pipermail/coreboot/2010-February/055825.html
+ @# https://www.coreboot.org/pipermail/coreboot/2010-February/055825.html
$(HOSTCC) -g $(STACK) -Wall -o $@ $<
IFDTOOL:=$(objutil)/ifdtool/ifdtool
diff --git a/README b/README
index 1f017a7..e7136ec 100644
--- a/README
+++ b/README
@@ -24,7 +24,7 @@
After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.
-See http://www.coreboot.org/Payloads for a list of supported payloads.
+See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
@@ -34,8 +34,8 @@
For details please consult:
- * http://www.coreboot.org/Supported_Motherboards
- * http://www.coreboot.org/Supported_Chipsets_and_Devices
+ * https://www.coreboot.org/Supported_Motherboards
+ * https://www.coreboot.org/Supported_Chipsets_and_Devices
Build Requirements
@@ -63,7 +63,7 @@
Building coreboot
-----------------
-Please consult http://www.coreboot.org/Build_HOWTO for details.
+Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
@@ -73,7 +73,7 @@
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.
-Please see http://www.coreboot.org/QEMU for details.
+Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
@@ -82,11 +82,11 @@
Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:
- http://www.coreboot.org
+ https://www.coreboot.org
You can contact us directly on the coreboot mailing list:
- http://www.coreboot.org/Mailinglist
+ https://www.coreboot.org/Mailinglist
Copyright and License
diff --git a/payloads/external/FILO/Kconfig.name b/payloads/external/FILO/Kconfig.name
index 244077d..ca94343 100644
--- a/payloads/external/FILO/Kconfig.name
+++ b/payloads/external/FILO/Kconfig.name
@@ -5,4 +5,4 @@
with a FILO payload. If you don't know what this is
about, just leave it enabled.
- See http://coreboot.org/Payloads for more information.
+ See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/GRUB2/Kconfig.name b/payloads/external/GRUB2/Kconfig.name
index c3a8ddf..cf23cf8 100644
--- a/payloads/external/GRUB2/Kconfig.name
+++ b/payloads/external/GRUB2/Kconfig.name
@@ -5,4 +5,4 @@
with a GRUB2 payload. If you don't know what this is
about, just leave it enabled.
- See http://coreboot.org/Payloads for more information.
+ See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/SeaBIOS/Kconfig.name b/payloads/external/SeaBIOS/Kconfig.name
index 9ab235d..bb1f30c 100644
--- a/payloads/external/SeaBIOS/Kconfig.name
+++ b/payloads/external/SeaBIOS/Kconfig.name
@@ -6,4 +6,4 @@
with a SeaBIOS payload. If you don't know what this is
about, just leave it enabled.
- See http://coreboot.org/Payloads for more information.
+ See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/U-Boot/Kconfig.name b/payloads/external/U-Boot/Kconfig.name
index 36e751f..cd2df7c 100644
--- a/payloads/external/U-Boot/Kconfig.name
+++ b/payloads/external/U-Boot/Kconfig.name
@@ -5,6 +5,6 @@
Select this option if you want to build a coreboot image
with a U-Boot payload.
- See http://coreboot.org/Payloads and U-Boot's documentation
+ See https://coreboot.org/Payloads and U-Boot's documentation
at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
for more information.
diff --git a/payloads/external/depthcharge/Kconfig.name b/payloads/external/depthcharge/Kconfig.name
index bc564ec..5a6c920 100644
--- a/payloads/external/depthcharge/Kconfig.name
+++ b/payloads/external/depthcharge/Kconfig.name
@@ -5,4 +5,4 @@
Select this option if you want to build a coreboot image
with a depthcharge payload.
- See http://coreboot.org/Payloads for more information.
+ See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/tianocore/Kconfig.name b/payloads/external/tianocore/Kconfig.name
index d57f7e1..11451b0 100644
--- a/payloads/external/tianocore/Kconfig.name
+++ b/payloads/external/tianocore/Kconfig.name
@@ -5,4 +5,4 @@
with a Tiano Core payload. If you don't know what this is
about, just leave it enabled.
- See http://coreboot.org/Payloads for more information.
+ See https://coreboot.org/Payloads for more information.
diff --git a/payloads/libpayload/README b/payloads/libpayload/README
index 0f905cb..6ed3da3 100644
--- a/payloads/libpayload/README
+++ b/payloads/libpayload/README
@@ -8,13 +8,13 @@
Note: This is _not_ a standard library for use with an operating system,
rather it's only useful for coreboot payload development!
-See http://coreboot.org for details on coreboot.
+See https://coreboot.org for details on coreboot.
Installation
------------
- $ git clone http://review.coreboot.org/p/coreboot.git
+ $ git clone https://review.coreboot.org/p/coreboot.git
$ cd coreboot/payloads/libpayload
@@ -52,10 +52,10 @@
Website and Mailing List
------------------------
-The main website is http://www.coreboot.org/Libpayload.
+The main website is https://www.coreboot.org/Libpayload.
For additional information, patches, and discussions, please join the
-coreboot mailing list at http://coreboot.org/Mailinglist, where most
+coreboot mailing list at https://coreboot.org/Mailinglist, where most
libpayload developers are subscribed.
diff --git a/payloads/libpayload/arch/x86/exec.S b/payloads/libpayload/arch/x86/exec.S
index f5cb0e3..3398106 100644
--- a/payloads/libpayload/arch/x86/exec.S
+++ b/payloads/libpayload/arch/x86/exec.S
@@ -30,7 +30,7 @@
/* calling syntax: i386_do_exec(long addr, int argc, char **argv, int *ret) */
/* This implements the payload API detailed here:
- * http://www.coreboot.org/Payload_API
+ * https://www.coreboot.org/Payload_API
*/
.align 4
diff --git a/payloads/libpayload/arch/x86/head.S b/payloads/libpayload/arch/x86/head.S
index 5250470..0575dbe 100644
--- a/payloads/libpayload/arch/x86/head.S
+++ b/payloads/libpayload/arch/x86/head.S
@@ -74,7 +74,7 @@
movl %ebx, loader_ebx
/* Copy argv[] and argc as demanded by the Payload API,
- * see http://www.coreboot.org/Payload_API and exec.S.
+ * see https://www.coreboot.org/Payload_API and exec.S.
*/
cmpl $CB_MAGIC_VALUE, CB_MAGIC(%esp)
jne 1f
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 5305603..3f0eca5 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -378,7 +378,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 442c2b4..ac17571 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -233,7 +233,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index d8a4fd9..db779fa 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -306,7 +306,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index f0d4939..388c2ea 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -132,7 +132,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 93d6907..33a7a6c 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -138,7 +138,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 149cae6..d1678bf 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -132,7 +132,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 21f63ec..4b85c07 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -107,7 +107,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 8d02e5d..2c19453 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -114,7 +114,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
@@ -160,7 +160,7 @@
#ifdef CARTEST
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %esi
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
@@ -241,7 +241,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
diff --git a/src/drivers/usb/Kconfig b/src/drivers/usb/Kconfig
index 935108f..802eced 100644
--- a/src/drivers/usb/Kconfig
+++ b/src/drivers/usb/Kconfig
@@ -25,7 +25,7 @@
It also requires a USB2 controller which supports the EHCI
Debug Port capability.
- See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
+ See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
of supported controllers.
If unsure, say N.
diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README
index 1d7bbdc..ffcbcc0 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/README
+++ b/src/mainboard/supermicro/h8dmr_fam10/README
@@ -17,6 +17,6 @@
* to avoid very slow LZMA decompression I use this port with LZMA compression
disabled in CBFS. I'm not sure what's causing this particular slowness.
-See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html
+See also this thread: https://www.coreboot.org/pipermail/coreboot/2009-September/052107.html
Ward, 2009-09-22
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 7b7140e..f59eedb 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -46,7 +46,7 @@
/*
* This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
- * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
+ * https://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
*/
static int acpi_is_wakeup_early_via_vx800(void)
{
@@ -527,7 +527,7 @@
#if PAYLOAD_IS_SEABIOS == 1
if (boot_mode == 3) {
/* An idea of Libo.Feng at amd.com in
- * http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html
+ * https://www.coreboot.org/pipermail/coreboot/2008-December/043111.html
*
* I want move the 1M data, I have to set some MTRRs myself.
* Setting MTRR before back memory save s3 resume time about
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index edde13b..cc8c328 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -313,7 +313,7 @@
* 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided
*
* See also:
- * http://www.coreboot.org/pipermail/coreboot/2009-May/047966.html
+ * https://www.coreboot.org/pipermail/coreboot/2009-May/047966.html
*/
static void set_dram_buffer_strength(void)
{
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 24720d1..d1bb3ee 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -134,7 +134,7 @@
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
diff --git a/util/abuild/abuild.1 b/util/abuild/abuild.1
index c047f8b..fbd31f3 100644
--- a/util/abuild/abuild.1
+++ b/util/abuild/abuild.1
@@ -51,7 +51,7 @@
.B "\-T, \-\-test"
Submit generated image(s) to the automated test system.
The results of the tests will be made available at
-.B http://qa.coreboot.org/log_manual.php
+.B https://qa.coreboot.org/log_manual.php
.TP
.B "\-c, \-\-cpus [<numcpus>|max]"
Build on
@@ -73,7 +73,7 @@
Show version information and exit.
.SH BUGS
Please report any bugs on the coreboot mailing list
-.RB "(" http://coreboot.org/Mailinglist ")."
+.RB "(" https://coreboot.org/Mailinglist ")."
.SH LICENCE
.B abuild
is covered by the GNU General Public License (GPL), version 2 or later.
diff --git a/util/amdtools/k8-compare-pci-space.pl b/util/amdtools/k8-compare-pci-space.pl
index ffc4c49..77fdb59 100755
--- a/util/amdtools/k8-compare-pci-space.pl
+++ b/util/amdtools/k8-compare-pci-space.pl
@@ -9,7 +9,7 @@
my $AUTHOR = "Ward Vandewege <ward\@jhvc.com>";
my $COPYRIGHT = "2009";
my $LICENSE = "GPL v3 - http://www.fsf.org/licenses/gpl.txt";
-my $URL = "http://coreboot.org";
+my $URL = "https://coreboot.org";
my $DEBUG = 0;
diff --git a/util/amdtools/k8-interpret-extended-memory-settings.pl b/util/amdtools/k8-interpret-extended-memory-settings.pl
index 5535a23..176defc 100755
--- a/util/amdtools/k8-interpret-extended-memory-settings.pl
+++ b/util/amdtools/k8-interpret-extended-memory-settings.pl
@@ -9,7 +9,7 @@
my $AUTHOR = "Ward Vandewege <ward\@jhvc.com>";
my $COPYRIGHT = "2009";
my $LICENSE = "GPL v3 - http://www.fsf.org/licenses/gpl.txt";
-my $URL = "http://coreboot.org";
+my $URL = "https://coreboot.org";
my $DEBUG = 0;
diff --git a/util/amdtools/parse-bkdg.pl b/util/amdtools/parse-bkdg.pl
index 8ef93b7..d0bb4c7 100755
--- a/util/amdtools/parse-bkdg.pl
+++ b/util/amdtools/parse-bkdg.pl
@@ -6,7 +6,7 @@
my $AUTHOR = "Ward Vandewege <ward\@jhvc.com>";
my $COPYRIGHT = "2009";
my $LICENSE = "GPL v3 - http://www.fsf.org/licenses/gpl.txt";
-my $URL = "http://coreboot.org";
+my $URL = "https://coreboot.org";
my $DEBUG = 0;
diff --git a/util/autoport/readme.md b/util/autoport/readme.md
index 35526f8..b673b5b 100644
--- a/util/autoport/readme.md
+++ b/util/autoport/readme.md
@@ -261,7 +261,7 @@
Which controller the most easily accessible USB debug port is. On intel
1 is for `00:1d.0` and 2 is `00:1a.0` (yes, it's reversed). See
-<http://www.coreboot.org/EHCI_Debug_Port> for more info.
+<https://www.coreboot.org/EHCI_Debug_Port> for more info.
If you're able to use EHCI debug port without setting HCD index manually
in config this is correct.
diff --git a/util/board_status/to-wiki/foreword.wiki b/util/board_status/to-wiki/foreword.wiki
index f0ae854..95ef38a 100644
--- a/util/board_status/to-wiki/foreword.wiki
+++ b/util/board_status/to-wiki/foreword.wiki
@@ -30,7 +30,7 @@
If the board is not found in the corebootv4's source code, there might
be some form of support that is not ready yet for inclusion in coreboot,
usually people willing to send their patches to coreboot goes through
-[http://review.coreboot.org gerrit], so looking there could find some
+[https://review.coreboot.org gerrit], so looking there could find some
code for boards that are not yet merged.
= Vendor trees =
diff --git a/util/board_status/to-wiki/push-to-wiki.sh b/util/board_status/to-wiki/push-to-wiki.sh
index 58e2cbb..6ad3c4a 100755
--- a/util/board_status/to-wiki/push-to-wiki.sh
+++ b/util/board_status/to-wiki/push-to-wiki.sh
@@ -3,7 +3,7 @@
# $2: wiki page to update
. ~/.wikiaccount
-WIKIAPI="http://www.coreboot.org/api.php"
+WIKIAPI="https://www.coreboot.org/api.php"
TITLE="$2"
cookie_jar="$HOME/.wikicookiejar"
#Will store file in wikifile
diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile
index d31eaf6..8345c18 100644
--- a/util/docker/coreboot-sdk/Dockerfile
+++ b/util/docker/coreboot-sdk/Dockerfile
@@ -30,7 +30,7 @@
RUN \
cd /root && \
- git clone http://review.coreboot.org/coreboot && \
+ git clone https://review.coreboot.org/coreboot && \
cd coreboot/util/crossgcc && \
git checkout {{DOCKER_COMMIT}} && \
make all_without_gdb \
diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h
index deb2eac..491ab5f 100644
--- a/util/intelmetool/intelmetool.h
+++ b/util/intelmetool/intelmetool.h
@@ -28,7 +28,7 @@
#include <sys/io.h>
#endif
#if (defined(__MACH__) && defined(__APPLE__))
-/* DirectHW is available here: http://www.coreboot.org/DirectHW */
+/* DirectHW is available here: https://www.coreboot.org/DirectHW */
#define __DARWIN__
#include <DirectHW/DirectHW.h>
#endif
diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8
index 49aafc3..86a76bd 100644
--- a/util/inteltool/inteltool.8
+++ b/util/inteltool/inteltool.8
@@ -9,7 +9,7 @@
CPUs, northbridges and southbridges.
.sp
This tool has been developed for the coreboot project (see
-.B http://coreboot.org
+.B https://coreboot.org
for details on coreboot).
.SH OPTIONS
.TP
@@ -64,7 +64,7 @@
Dump Advanced Memory Buffer (AMB) registers.
.SH BUGS
Please report any bugs on the coreboot mailing list
-.RB "(" http://coreboot.org/Mailinglist ")."
+.RB "(" https://coreboot.org/Mailinglist ")."
.SH LICENCE
.B inteltool
is covered by the GNU General Public License (GPL), version 2.
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 54ddf84..e463260 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -22,7 +22,7 @@
#include <sys/io.h>
#endif
#if (defined(__MACH__) && defined(__APPLE__))
-/* DirectHW is available here: http://www.coreboot.org/DirectHW */
+/* DirectHW is available here: https://www.coreboot.org/DirectHW */
#define __DARWIN__
#include <DirectHW/DirectHW.h>
#endif
diff --git a/util/msrtool/darwin.c b/util/msrtool/darwin.c
index 10ec145..1423fbd 100644
--- a/util/msrtool/darwin.c
+++ b/util/msrtool/darwin.c
@@ -23,7 +23,7 @@
#include "msrtool.h"
/* This Darwin support requires DirectHW, which is available at
- * http://www.coreboot.org/DirectHW
+ * https://www.coreboot.org/DirectHW
*/
int darwin_probe(const struct sysdef *system)
diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h
index fe7f0f0..93881e9 100644
--- a/util/msrtool/msrtool.h
+++ b/util/msrtool/msrtool.h
@@ -20,7 +20,7 @@
#include <stdio.h>
#include <stdint.h>
#if (defined(__MACH__) && defined(__APPLE__))
-/* DirectHW is available here: http://www.coreboot.org/DirectHW */
+/* DirectHW is available here: https://www.coreboot.org/DirectHW */
#define __DARWIN__
#include <DirectHW/DirectHW.h>
#endif
diff --git a/util/nvramtool/DISCLAIMER b/util/nvramtool/DISCLAIMER
index 290ab52..bed93be 100644
--- a/util/nvramtool/DISCLAIMER
+++ b/util/nvramtool/DISCLAIMER
@@ -10,7 +10,7 @@
This file is part of nvramtool, a utility for reading/writing coreboot
parameters and displaying information from the coreboot table.
-For details, see http://coreboot.org/nvramtool.
+For details, see https://coreboot.org/nvramtool.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (as published by the
diff --git a/util/nvramtool/README b/util/nvramtool/README
index 183b84c..4d4b38f 100644
--- a/util/nvramtool/README
+++ b/util/nvramtool/README
@@ -10,7 +10,7 @@
specifies locations in the CMOS (nonvolatile RAM) where the coreboot
parameters are stored.
-For information about coreboot, see http://www.coreboot.org/.
+For information about coreboot, see https://www.coreboot.org/.
Ideas for Future Improvements
-----------------------------
diff --git a/util/nvramtool/accessors/layout-bin.c b/util/nvramtool/accessors/layout-bin.c
index 9f92283..e545dc5 100644
--- a/util/nvramtool/accessors/layout-bin.c
+++ b/util/nvramtool/accessors/layout-bin.c
@@ -16,7 +16,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/accessors/layout-common.c b/util/nvramtool/accessors/layout-common.c
index 22a81fa..7dcfd3e 100644
--- a/util/nvramtool/accessors/layout-common.c
+++ b/util/nvramtool/accessors/layout-common.c
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c
index f2735b9..9567b7f 100644
--- a/util/nvramtool/accessors/layout-text.c
+++ b/util/nvramtool/accessors/layout-text.c
@@ -15,7 +15,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/accessors/layout-text.h b/util/nvramtool/accessors/layout-text.h
index 6232e73..abbd414 100644
--- a/util/nvramtool/accessors/layout-text.h
+++ b/util/nvramtool/accessors/layout-text.h
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/cli/nvramtool.8 b/util/nvramtool/cli/nvramtool.8
index 8c4e2dc..1737c4e 100644
--- a/util/nvramtool/cli/nvramtool.8
+++ b/util/nvramtool/cli/nvramtool.8
@@ -9,7 +9,7 @@
.\"
.\" This file is part of nvramtool, a utility for reading/writing coreboot
.\" parameters and displaying information from the coreboot table.
-.\" For details, see http://coreboot.org/nvramtool.
+.\" For details, see https://coreboot.org/nvramtool.
.\"
.\" Please also read the file DISCLAIMER which is included in this software
.\" distribution.
@@ -71,7 +71,7 @@
This program is intended for (x86-based) systems that use coreboot. For
information about coreboot, see
.br
-http://www.coreboot.org/.
+https://www.coreboot.org/.
.SH PARAMETERS
.TP
.B "[-n] -r NAME"
diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c
index 7f5fba8..9181800 100644
--- a/util/nvramtool/cli/nvramtool.c
+++ b/util/nvramtool/cli/nvramtool.c
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/cli/opts.c b/util/nvramtool/cli/opts.c
index 8b62a47..d4ea9ce 100644
--- a/util/nvramtool/cli/opts.c
+++ b/util/nvramtool/cli/opts.c
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/cli/opts.h b/util/nvramtool/cli/opts.h
index 4800492..e6bd1f6 100644
--- a/util/nvramtool/cli/opts.h
+++ b/util/nvramtool/cli/opts.h
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/cmos_lowlevel.c b/util/nvramtool/cmos_lowlevel.c
index 7221f23..eadda62 100644
--- a/util/nvramtool/cmos_lowlevel.c
+++ b/util/nvramtool/cmos_lowlevel.c
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/cmos_lowlevel.h b/util/nvramtool/cmos_lowlevel.h
index 329a1ae..2b10ae3 100644
--- a/util/nvramtool/cmos_lowlevel.h
+++ b/util/nvramtool/cmos_lowlevel.h
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/cmos_ops.c b/util/nvramtool/cmos_ops.c
index 6f616a0..3c5a08b 100644
--- a/util/nvramtool/cmos_ops.c
+++ b/util/nvramtool/cmos_ops.c
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/cmos_ops.h b/util/nvramtool/cmos_ops.h
index 10185c6..12a11b6 100644
--- a/util/nvramtool/cmos_ops.h
+++ b/util/nvramtool/cmos_ops.h
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/common.c b/util/nvramtool/common.c
index adb5613..8ae6ea8 100644
--- a/util/nvramtool/common.c
+++ b/util/nvramtool/common.c
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/common.h b/util/nvramtool/common.h
index 489381f..559e80f 100644
--- a/util/nvramtool/common.h
+++ b/util/nvramtool/common.h
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/compute_ip_checksum.c b/util/nvramtool/compute_ip_checksum.c
index f19e943..240da43 100644
--- a/util/nvramtool/compute_ip_checksum.c
+++ b/util/nvramtool/compute_ip_checksum.c
@@ -6,7 +6,7 @@
#include "ip_checksum.h"
/* Note: The contents of this file were borrowed from the coreboot source
- * code which may be obtained from http://www.coreboot.org.
+ * code which may be obtained from https://www.coreboot.org.
* Specifically, this code was obtained from coreboot (LinuxBIOS)
* version 1.0.0.8.
*/
diff --git a/util/nvramtool/coreboot_tables.h b/util/nvramtool/coreboot_tables.h
index 22570ac..1bd1e53 100644
--- a/util/nvramtool/coreboot_tables.h
+++ b/util/nvramtool/coreboot_tables.h
@@ -8,7 +8,7 @@
#include <stdint.h>
/* Note: The contents of this file were borrowed from the coreboot source
- * code which may be obtained from http://www.coreboot.org/.
+ * code which may be obtained from https://www.coreboot.org/.
* Specifically, this code was obtained from LinuxBIOS version 1.1.8.
*/
diff --git a/util/nvramtool/input_file.c b/util/nvramtool/input_file.c
index cce9a10..730ea37 100644
--- a/util/nvramtool/input_file.c
+++ b/util/nvramtool/input_file.c
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/input_file.h b/util/nvramtool/input_file.h
index 5f860d1..0fce720 100644
--- a/util/nvramtool/input_file.h
+++ b/util/nvramtool/input_file.h
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/ip_checksum.h b/util/nvramtool/ip_checksum.h
index f2a1307..19f3428 100644
--- a/util/nvramtool/ip_checksum.h
+++ b/util/nvramtool/ip_checksum.h
@@ -6,7 +6,7 @@
#define IP_CHECKSUM_H
/* Note: The contents of this file were borrowed from the coreboot source
- * code which may be obtained from http://www.coreboot.org.
+ * code which may be obtained from https://www.coreboot.org.
* Specifically, this code was obtained from coreboot (LinuxBIOS)
* version 1.0.0.8.
*/
diff --git a/util/nvramtool/layout.c b/util/nvramtool/layout.c
index 6fdb282..a340671 100644
--- a/util/nvramtool/layout.c
+++ b/util/nvramtool/layout.c
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/layout.h b/util/nvramtool/layout.h
index bde0603..a75654b 100644
--- a/util/nvramtool/layout.h
+++ b/util/nvramtool/layout.h
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/lbtable.c b/util/nvramtool/lbtable.c
index 5db61c5..d2ae1b5 100644
--- a/util/nvramtool/lbtable.c
+++ b/util/nvramtool/lbtable.c
@@ -10,7 +10,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/lbtable.h b/util/nvramtool/lbtable.h
index ea1d141..60609a9 100644
--- a/util/nvramtool/lbtable.h
+++ b/util/nvramtool/lbtable.h
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/reg_expr.c b/util/nvramtool/reg_expr.c
index 0e9baca..5be80fc 100644
--- a/util/nvramtool/reg_expr.c
+++ b/util/nvramtool/reg_expr.c
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/nvramtool/reg_expr.h b/util/nvramtool/reg_expr.h
index 08c9070..553c96a 100644
--- a/util/nvramtool/reg_expr.h
+++ b/util/nvramtool/reg_expr.h
@@ -9,7 +9,7 @@
*
* This file is part of nvramtool, a utility for reading/writing coreboot
* parameters and displaying information from the coreboot table.
- * For details, see http://coreboot.org/nvramtool.
+ * For details, see https://coreboot.org/nvramtool.
*
* Please also read the file DISCLAIMER which is included in this software
* distribution.
diff --git a/util/optionlist/README b/util/optionlist/README
index 616633a..6e670e8 100644
--- a/util/optionlist/README
+++ b/util/optionlist/README
@@ -1 +1 @@
-This script creates the page http://www.coreboot.org/Coreboot_Options
+This script creates the page https://www.coreboot.org/Coreboot_Options
diff --git a/util/optionlist/kconfig2wiki b/util/optionlist/kconfig2wiki
index a587a9c5..471357c 100755
--- a/util/optionlist/kconfig2wiki
+++ b/util/optionlist/kconfig2wiki
@@ -1,7 +1,7 @@
#!/usr/bin/env python
#
# kconfig2wiki - Kconfig to MediaWiki converter for
-# http://www.coreboot.org/Coreboot_Options
+# https://www.coreboot.org/Coreboot_Options
#
# Copyright (C) 2010 coresystems GmbH
# based on http://landley.net/kdocs/make/menuconfig2html.py
diff --git a/util/superiotool/README b/util/superiotool/README
index 1f6a20a..72b786a 100644
--- a/util/superiotool/README
+++ b/util/superiotool/README
@@ -18,7 +18,7 @@
Installation
------------
- $ git clone http://review.coreboot.org/p/coreboot.git
+ $ git clone https://review.coreboot.org/p/coreboot.git
$ cd coreboot/util/superiotool
@@ -53,23 +53,23 @@
Supported Super I/O Chips
-------------------------
-Please see http://coreboot.org/Superiotool#Supported_devices, or type
+Please see https://coreboot.org/Superiotool#Supported_devices, or type
$ superiotool -l
There's also a collection of sample register dumps from various Super I/O
chips on that web page. Please send further register dumps (either from a
proprietary BIOS and/or from coreboot) to the coreboot mailing list
-(http://coreboot.org/Mailinglist).
+(https://coreboot.org/Mailinglist).
Website and Mailing List
------------------------
-The main website is http://coreboot.org/Superiotool.
+The main website is https://coreboot.org/Superiotool.
For additional information, patches, and discussions, please join the
-coreboot mailing list at http://coreboot.org/Mailinglist, where most
+coreboot mailing list at https://coreboot.org/Mailinglist, where most
superiotool developers are subscribed.
diff --git a/util/superiotool/superiotool.8 b/util/superiotool/superiotool.8
index c47a4a9..41d0780 100644
--- a/util/superiotool/superiotool.8
+++ b/util/superiotool/superiotool.8
@@ -18,7 +18,7 @@
for details on coreboot), but it may also be useful for other things.
.PP
The list of supported Super I/O chips is available at
-.BR http://coreboot.org/Superiotool#Supported_devices ","
+.BR https://coreboot.org/Superiotool#Supported_devices ","
but it can also be viewed by running
.BR "superiotool -l" "."
.SH OPTIONS
@@ -110,7 +110,7 @@
Show a help text and exit.
.SH BUGS
Please report any bugs on the coreboot mailing list
-.RB "(" http://coreboot.org/Mailinglist ")."
+.RB "(" https://coreboot.org/Mailinglist ")."
.SH AUTHORS
Please see the individual source code files and/or the README file.
.SH LICENCE
diff --git a/util/superiotool/superiotool.c b/util/superiotool/superiotool.c
index aadf8ea..3e21b0c 100644
--- a/util/superiotool/superiotool.c
+++ b/util/superiotool/superiotool.c
@@ -275,7 +275,7 @@
for (i = 0; i < ARRAY_SIZE(vendor_print_functions); i++)
vendor_print_functions[i].print_list();
- printf("See <http://coreboot.org/Superiotool#Supported_devices> "
+ printf("See <https://coreboot.org/Superiotool#Supported_devices> "
"for more information.\n");
}
diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index 92bb4ea..58a9d61 100644
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -29,7 +29,7 @@
#include <sys/io.h>
#endif
#if (defined(__MACH__) && defined(__APPLE__))
-/* DirectHW is available here: http://www.coreboot.org/DirectHW */
+/* DirectHW is available here: https://www.coreboot.org/DirectHW */
#include <DirectHW/DirectHW.h>
#endif
diff --git a/util/viatool/viatool.h b/util/viatool/viatool.h
index 3a6f048..a95547a 100644
--- a/util/viatool/viatool.h
+++ b/util/viatool/viatool.h
@@ -24,7 +24,7 @@
#include <sys/io.h>
#endif
#if (defined(__MACH__) && defined(__APPLE__))
-/* DirectHW is available here: http://www.coreboot.org/DirectHW */
+/* DirectHW is available here: https://www.coreboot.org/DirectHW */
#define __DARWIN__
#include <DirectHW/DirectHW.h>
#endif