diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h
index 90a0e1e..a4a7a75 100644
--- a/src/northbridge/intel/gm45/chip.h
+++ b/src/northbridge/intel/gm45/chip.h
@@ -21,11 +21,10 @@
 #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H
 #define NORTHBRIDGE_INTEL_GM45_CHIP_H
 
+#include <drivers/intel/gma/i915.h>
+
 struct northbridge_intel_gm45_config {
-	int gpu_use_spread_spectrum_clock;
-	int gpu_lvds_dual_channel;
-	int gpu_link_frequency_270_mhz;
-	int gpu_lvds_num_lanes;
+	struct i915_gpu_controller_info gfx;
 };
 
 #endif				/* NORTHBRIDGE_INTEL_GM45_CHIP_H */
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 12a0b4d..74e16ad 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -39,31 +39,6 @@
 #include <pc80/vga.h>
 #include <pc80/vga_io.h>
 
-typedef struct {
-	u16	signature;
-	u8	size;
-	u8	reserved[21];
-	u16	pcir_offset;
-	u16	vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
-
-#define OPROM_SIGNATURE 0xaa55
-
-typedef struct {
-	u32 signature;
-	u16 vendor;
-	u16 device;
-	u16 reserved1;
-	u16 length;
-	u8  revision;
-	u8  classcode[3];
-	u16 imagelength;
-	u16 coderevision;
-	u8  codetype;
-	u8  indicator;
-	u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
-
 static struct resource *gtt_res = NULL;
 
 void gtt_write(u32 reg, u32 data)
@@ -144,7 +119,7 @@
 	u32 pixel_n = 1;
 	u32 pixel_m1 = 1;
 	u32 pixel_m2 = 1;
-	u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000;
+	u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
 	u32 data_m1;
 	u32 data_n1 = 0x00800000;
 	u32 link_m1;
@@ -197,7 +172,7 @@
 	hfront_porch = edid.hso;
 	vfront_porch = edid.vso;
 
-	target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock
+	target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
 		: (2 * edid.pixel_clock);
 #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_textmode_init();
@@ -267,7 +242,7 @@
 
 	link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
 	data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
-		/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4));
+		/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
 
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
 	       hactive, vactive);
@@ -279,10 +254,10 @@
 	       hsync, vsync);
 	printk(BIOS_DEBUG, "Front porch %d x %d\n",
 	       hfront_porch, vfront_porch);
-	printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock
+	printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
 			    ? "Spread spectrum clock\n" : "DREF clock\n"));
 	printk(BIOS_DEBUG,
-	       info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
+	       info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
 	printk(BIOS_DEBUG, "Polarities %d, %d\n",
 	       hpolarity, vpolarity);
 	printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@@ -299,7 +274,7 @@
 
 	write32(mmio + LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
 	mdelay(1);
@@ -310,18 +285,18 @@
 		| ((pixel_m1 - 2) << 8) | pixel_m2);
 	write32(mmio + DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 	mdelay(1);
 	write32(mmio + DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 	/* Re-lock the registers.  */
 	write32(mmio + PP_CONTROL,
@@ -329,7 +304,7 @@
 
 	write32(mmio + LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
 
@@ -423,7 +398,7 @@
 	write32(mmio + LVDS,
 		LVDS_PORT_ENABLE
 		| (hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
 
@@ -457,54 +432,6 @@
 #endif
 }
 
-static size_t generate_vbt(const struct northbridge_intel_gm45_config *conf,
-			   void *vbt)
-{
-	struct vbt_header *head = vbt;
-	struct bdb_header *bdb_head;
-	struct bdb_general_features *genfeat;
-	u8 *ptr;
-
-	memset (head, 0, sizeof (*head));
-
-	memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20);
-	head->version = 100;
-	head->header_size = sizeof (*head);
-	head->bdb_offset = sizeof (*head);
-
-	bdb_head = (struct bdb_header *) (head + 1);
-	memset (bdb_head, 0, sizeof (*bdb_head));
-	memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
-	bdb_head->version = 0xa8;
-	bdb_head->header_size = sizeof (*bdb_head);
-
-	ptr = (u8 *) (bdb_head + 1);
-
-	ptr[0] = BDB_GENERAL_FEATURES;
-	ptr[1] = sizeof (*genfeat);
-	ptr[2] = sizeof (*genfeat) >> 8;
-	ptr += 3;
-
-	genfeat = (struct bdb_general_features *) ptr;
-	memset (genfeat, 0, sizeof (*genfeat));
-	genfeat->panel_fitting = 3;
-	genfeat->flexaim = 1;
-	genfeat->download_ext_vbt = 1;
-	genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
-	genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
-	genfeat->rsvd10 = 0x4;
-	genfeat->legacy_monitor_detect = 1;
-	genfeat->int_crt_support = 1;
-	genfeat->dp_ssc_enb = 1;
-
-	ptr += sizeof (*genfeat);
-
-	bdb_head->bdb_size = ptr - (u8 *)bdb_head;
-	head->vbt_size = ptr - (u8 *)head;
-	head->vbt_checksum = 0;
-	return ptr - (u8 *)head;
-}
-
 #endif
 
 static void gma_func0_init(struct device *dev)
@@ -542,34 +469,7 @@
 	}
 
 	/* Linux relies on VBT for panel info.  */
-	if (read16(PCI_VGA_RAM_IMAGE_START) != PCI_ROM_HDR) {
-		optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START;
-		optionrom_pcir_t *pcir;
-		size_t vbt_size;
-		size_t fake_oprom_size;
-
-		memset(oh, 0, 8192);
-
-		oh->signature = PCI_ROM_HDR;
-		oh->pcir_offset = 0x40;
-		oh->vbt_offset = 0x80;
-
-		pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
-		pcir->signature = 0x52494350;	// PCIR
-		pcir->vendor = dev->vendor;
-		pcir->device = dev->device;
-		pcir->length = sizeof(*pcir);
-		pcir->revision = dev->class;
-		pcir->classcode[0] = dev->class >> 8;
-		pcir->classcode[1] = dev->class >> 16;
-		pcir->classcode[2] = dev->class >> 24;
-		pcir->indicator = 0x80;
-
-		vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
-		fake_oprom_size = (0x80 + vbt_size + 511) / 512;
-		oh->size = fake_oprom_size;
-		pcir->imagelength = fake_oprom_size;
-	}
+	generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
 #endif
 
 	/* Post VBIOS init */
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 9b7357c..6f694e2 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -31,6 +31,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <drivers/intel/gma/intel_bios.h>
 #include <build.h>
 #include <arch/acpigen.h>
 #include <cpu/cpu.h>
diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h
index e33d108..1a31238 100644
--- a/src/northbridge/intel/nehalem/chip.h
+++ b/src/northbridge/intel/nehalem/chip.h
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <drivers/intel/gma/i915.h>
+
 /*
  * Digital Port Hotplug Enable:
  *  0x04 = Enabled, 2ms short pulse
@@ -39,8 +41,5 @@
 	u32 gpu_cpu_backlight;	/* CPU Backlight PWM value */
 	u32 gpu_pch_backlight;	/* PCH Backlight PWM value */
 
-	int gpu_use_spread_spectrum_clock;
-	int gpu_lvds_dual_channel;
-	int gpu_link_frequency_270_mhz;
-	int gpu_lvds_num_lanes;
+	struct i915_gpu_controller_info gfx;
 };
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index a57bf6b..c3e2a49 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -654,7 +654,7 @@
 	u32 pixel_n = 1;
 	u32 pixel_m1 = 1;
 	u32 pixel_m2 = 1;
-	u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000;
+	u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
 	u32 data_m1;
 	u32 data_n1 = 0x00800000;
 	u32 link_m1;
@@ -719,7 +719,7 @@
 	hfront_porch = edid.hso;
 	vfront_porch = edid.vso;
 
-	target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock
+	target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
 		: (2 * edid.pixel_clock);
 #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_textmode_init();
@@ -790,7 +790,7 @@
 
 	link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
 	data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
-		/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4));
+		/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
 
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
 	       hactive, vactive);
@@ -802,10 +802,10 @@
 	       hsync, vsync);
 	printk(BIOS_DEBUG, "Front porch %d x %d\n",
 	       hfront_porch, vfront_porch);
-	printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock
+	printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
 			    ? "Spread spectrum clock\n" : "DREF clock\n"));
 	printk(BIOS_DEBUG,
-	       info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
+	       info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
 	printk(BIOS_DEBUG, "Polarities %d, %d\n",
 	       hpolarity, vpolarity);
 	printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@@ -822,12 +822,12 @@
 
 	write32(mmio + PCH_LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
 	write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
-	write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock
+	write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock
 					  ? 0x1002 : 0x400));
 	mdelay(1);
 	write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
@@ -837,18 +837,18 @@
 		| ((pixel_m1 - 2) << 8) | pixel_m2);
 	write32(mmio + _PCH_DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 	mdelay(1);
 	write32(mmio + _PCH_DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 	/* Re-lock the registers.  */
 	write32(mmio + PCH_PP_CONTROL,
@@ -856,7 +856,7 @@
 
 	write32(mmio + PCH_LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
@@ -953,7 +953,7 @@
 	write32(mmio + PCH_LVDS,
 		LVDS_PORT_ENABLE
 		| (hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
@@ -988,53 +988,6 @@
 #endif
 }
 
-static size_t generate_vbt(const struct northbridge_intel_nehalem_config *conf,
-			   void *vbt)
-{
-	struct vbt_header *head = vbt;
-	struct bdb_header *bdb_head;
-	struct bdb_general_features *genfeat;
-	u8 *ptr;
-
-	memset(head, 0, sizeof (*head));
-
-	memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20);
-	head->version = 100;
-	head->header_size = sizeof (*head);
-	head->bdb_offset = sizeof (*head);
-
-	bdb_head = (struct bdb_header *) (head + 1);
-	memset(bdb_head, 0, sizeof (*bdb_head));
-	memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
-	bdb_head->version = 0xa8;
-	bdb_head->header_size = sizeof (*bdb_head);
-
-	ptr = (u8 *) (bdb_head + 1);
-
-	ptr[0] = BDB_GENERAL_FEATURES;
-	ptr[1] = sizeof (*genfeat);
-	ptr[2] = sizeof (*genfeat) >> 8;
-	ptr += 3;
-
-	genfeat = (struct bdb_general_features *) ptr;
-	memset(genfeat, 0, sizeof (*genfeat));
-	genfeat->panel_fitting = 3;
-	genfeat->flexaim = 1;
-	genfeat->download_ext_vbt = 1;
-	genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
-	genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
-	genfeat->rsvd10 = 0x4;
-	genfeat->legacy_monitor_detect = 1;
-	genfeat->int_crt_support = 1;
-	genfeat->dp_ssc_enb = 1;
-
-	ptr += sizeof (*genfeat);
-
-	bdb_head->bdb_size = ptr - (u8 *)bdb_head;
-	head->vbt_size = ptr - (u8 *)head;
-	head->vbt_checksum = 0;
-	return ptr - (u8 *)head;
-}
 #endif
 
 static void gma_func0_init(struct device *dev)
@@ -1072,34 +1025,7 @@
 	}
 
 	/* Linux relies on VBT for panel info.  */
-	if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) {
-		optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START;
-		optionrom_pcir_t *pcir;
-		size_t vbt_size;
-		size_t fake_oprom_size;
-
-		memset(oh, 0, 8192);
-
-		oh->signature = OPROM_SIGNATURE;
-		oh->pcir_offset = 0x40;
-		oh->vbt_offset = 0x80;
-
-		pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
-		pcir->signature = 0x52494350;	// PCIR
-		pcir->vendor = dev->vendor;
-		pcir->device = dev->device;
-		pcir->length = sizeof(*pcir);
-		pcir->revision = dev->class;
-		pcir->classcode[0] = dev->class >> 8;
-		pcir->classcode[1] = dev->class >> 16;
-		pcir->classcode[2] = dev->class >> 24;
-		pcir->indicator = 0x80;
-
-		vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
-		fake_oprom_size = (0x80 + vbt_size + 511) / 512;
-		oh->size = fake_oprom_size;
-		pcir->imagelength = fake_oprom_size;
-	}
+	generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
 #endif
 
 
diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h
index fdea85a..f0e1c53 100644
--- a/src/northbridge/intel/nehalem/gma.h
+++ b/src/northbridge/intel/nehalem/gma.h
@@ -118,56 +118,4 @@
 	opregion_vbt_t vbt;
 } __attribute__((packed)) igd_opregion_t;
 
-/* Intel Video BIOS (Option ROM) */
-typedef struct {
-	u16	signature;
-	u8	size;
-	u8	reserved[21];
-	u16	pcir_offset;
-	u16	vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
-
-#define OPROM_SIGNATURE 0xaa55
-
-typedef struct {
-	u32 signature;
-	u16 vendor;
-	u16 device;
-	u16 reserved1;
-	u16 length;
-	u8  revision;
-	u8  classcode[3];
-	u16 imagelength;
-	u16 coderevision;
-	u8  codetype;
-	u8  indicator;
-	u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
-
-typedef struct {
-	u8  hdr_signature[20];
-	u16 hdr_version;
-	u16 hdr_size;
-	u16 hdr_vbt_size;
-	u8  hdr_vbt_checksum;
-	u8  hdr_reserved;
-	u32 hdr_vbt_datablock;
-	u32 hdr_aim[4];
-	u8  datahdr_signature[16];
-	u16 datahdr_version;
-	u16 datahdr_size;
-	u16 datahdr_datablocksize;
-	u8  coreblock_id;
-	u16 coreblock_size;
-	u16 coreblock_biossize;
-	u8  coreblock_biostype;
-	u8  coreblock_releasestatus;
-	u8  coreblock_hwsupported;
-	u8  coreblock_integratedhw;
-	u8  coreblock_biosbuild[4];
-	u8  coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
-
-#define VBT_SIGNATURE 0x54425624
-
 #endif
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 925812a..c77b5cc 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -33,6 +33,7 @@
 #include <arch/acpigen.h>
 #include "sandybridge.h"
 #include <cbmem.h>
+#include <drivers/intel/gma/intel_bios.h>
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h
index cc32c37..07809f5 100644
--- a/src/northbridge/intel/sandybridge/chip.h
+++ b/src/northbridge/intel/sandybridge/chip.h
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <drivers/intel/gma/i915.h>
+
 /*
  * Digital Port Hotplug Enable:
  *  0x04 = Enabled, 2ms short pulse
@@ -39,8 +41,5 @@
 	u32 gpu_cpu_backlight;	/* CPU Backlight PWM value */
 	u32 gpu_pch_backlight;	/* PCH Backlight PWM value */
 
-	int gpu_use_spread_spectrum_clock;
-	int gpu_lvds_dual_channel;
-	int gpu_link_frequency_270_mhz;
-	int gpu_lvds_num_lanes;
+	struct i915_gpu_controller_info gfx;
 };
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index f305b81..247c723 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -278,12 +278,12 @@
 
 static struct resource *gtt_res = NULL;
 
-static inline u32 gtt_read(u32 reg)
+u32 gtt_read(u32 reg)
 {
 	return read32(gtt_res->base + reg);
 }
 
-static inline void gtt_write(u32 reg, u32 data)
+void gtt_write(u32 reg, u32 data)
 {
 	write32(gtt_res->base + reg, data);
 }
@@ -295,7 +295,7 @@
 }
 
 #define GTT_RETRY 1000
-static int gtt_poll(u32 reg, u32 mask, u32 value)
+int gtt_poll(u32 reg, u32 mask, u32 value)
 {
 	unsigned try = GTT_RETRY;
 	u32 data;
@@ -595,7 +595,7 @@
 	physbase = pci_read_config32(dev, 0x5c) & ~0xf;
 	graphics_base = dev->resource_list[1].base;
 
-	int lightup_ok = i915lightup_sandy(conf, physbase, iobase, mmiobase, graphics_base);
+	int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base);
 	if (lightup_ok)
 		gfx_set_init_done(1);
 #endif
diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h
index b7502cd..3a73e08 100644
--- a/src/northbridge/intel/sandybridge/gma.h
+++ b/src/northbridge/intel/sandybridge/gma.h
@@ -114,59 +114,7 @@
 	opregion_vbt_t vbt;
 } __attribute__((packed)) igd_opregion_t;
 
-/* Intel Video BIOS (Option ROM) */
-typedef struct {
-	u16	signature;
-	u8	size;
-	u8	reserved[21];
-	u16	pcir_offset;
-	u16	vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
+struct i915_gpu_controller_info;
 
-#define OPROM_SIGNATURE 0xaa55
-
-typedef struct {
-	u32 signature;
-	u16 vendor;
-	u16 device;
-	u16 reserved1;
-	u16 length;
-	u8  revision;
-	u8  classcode[3];
-	u16 imagelength;
-	u16 coderevision;
-	u8  codetype;
-	u8  indicator;
-	u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
-
-typedef struct {
-	u8  hdr_signature[20];
-	u16 hdr_version;
-	u16 hdr_size;
-	u16 hdr_vbt_size;
-	u8  hdr_vbt_checksum;
-	u8  hdr_reserved;
-	u32 hdr_vbt_datablock;
-	u32 hdr_aim[4];
-	u8  datahdr_signature[16];
-	u16 datahdr_version;
-	u16 datahdr_size;
-	u16 datahdr_datablocksize;
-	u8  coreblock_id;
-	u16 coreblock_size;
-	u16 coreblock_biossize;
-	u8  coreblock_biostype;
-	u8  coreblock_releasestatus;
-	u8  coreblock_hwsupported;
-	u8  coreblock_integratedhw;
-	u8  coreblock_biosbuild[4];
-	u8  coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
-
-#define VBT_SIGNATURE 0x54425624
-
-struct northbridge_intel_sandybridge_config;
-
-int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
+int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 		u32 physbase, u16 pio, u32 mmio, u32 lfb);
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index 53fbfda..e3e1f4b 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -36,54 +36,6 @@
 
 #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
 
-static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf,
-			   void *vbt)
-{
-	struct vbt_header *head = vbt;
-	struct bdb_header *bdb_head;
-	struct bdb_general_features *genfeat;
-	u8 *ptr;
-
-	memset(head, 0, sizeof (*head));
-
-	memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20);
-	head->version = 100;
-	head->header_size = sizeof (*head);
-	head->bdb_offset = sizeof (*head);
-
-	bdb_head = (struct bdb_header *) (head + 1);
-	memset(bdb_head, 0, sizeof (*bdb_head));
-	memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
-	bdb_head->version = 0xa8;
-	bdb_head->header_size = sizeof (*bdb_head);
-
-	ptr = (u8 *) (bdb_head + 1);
-
-	ptr[0] = BDB_GENERAL_FEATURES;
-	ptr[1] = sizeof (*genfeat);
-	ptr[2] = sizeof (*genfeat) >> 8;
-	ptr += 3;
-
-	genfeat = (struct bdb_general_features *) ptr;
-	memset(genfeat, 0, sizeof (*genfeat));
-	genfeat->panel_fitting = 3;
-	genfeat->flexaim = 1;
-	genfeat->download_ext_vbt = 1;
-	genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
-	genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
-	genfeat->rsvd10 = 0x4;
-	genfeat->legacy_monitor_detect = 1;
-	genfeat->int_crt_support = 1;
-	genfeat->dp_ssc_enb = 1;
-
-	ptr += sizeof (*genfeat);
-
-	bdb_head->bdb_size = ptr - (u8 *)bdb_head;
-	head->vbt_size = ptr - (u8 *)head;
-	head->vbt_checksum = 0;
-	return ptr - (u8 *)head;
-}
-
 static void link_train(u32 mmio)
 {
 	write32(mmio+0xf000c,0x40);
@@ -207,8 +159,8 @@
 	read32(mmio + 0xc4000);
 }
 
-int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
-		u32 physbase, u16 piobase, u32 mmio, u32 lfb)
+int i915lightup_sandy(const struct i915_gpu_controller_info *info,
+		      u32 physbase, u16 piobase, u32 mmio, u32 lfb)
 {
 	int i;
 	u8 edid_data[128];
@@ -277,7 +229,7 @@
 	u32 candp1, candn;
 	u32 best_delta = 0xffffffff;
 
-	u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock
+	u32 target_frequency = info->lvds_dual_channel ? edid.pixel_clock
 		: (2 * edid.pixel_clock);
 	u32 pixel_p1 = 1;
 	u32 pixel_n = 1;
@@ -350,7 +302,7 @@
 		return 0;
 	}
 
-	u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000;
+	u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000;
 	u32 data_m1;
 	u32 data_n1 = 0x00800000;
 	u32 link_m1;
@@ -359,7 +311,7 @@
 	link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
 
 	data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
-		/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1));
+		/ (link_frequency * 8 * (info->lvds_num_lanes ? : 1));
 
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
 	       hactive, vactive);
@@ -371,10 +323,10 @@
 	       hsync, vsync);
 	printk(BIOS_DEBUG, "Front porch %d x %d\n",
 	       hfront_porch, vfront_porch);
-	printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock
+	printk(BIOS_DEBUG, (info->use_spread_spectrum_clock
 			    ? "Spread spectrum clock\n" : "DREF clock\n"));
 	printk(BIOS_DEBUG,
-	       info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
+	       info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
 	printk(BIOS_DEBUG, "Polarities %d, %d\n",
 	       hpolarity, vpolarity);
 	printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@@ -391,12 +343,12 @@
 
 	write32(mmio + PCH_LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
 	write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
-	write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock
+	write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
 					  ? 0x1002 : 0x400));
 	mdelay(1);
 	write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
@@ -406,10 +358,10 @@
 		| ((pixel_m1 - 2) << 8) | pixel_m2);
 	write32(mmio + _PCH_DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 
 	mdelay(1);
@@ -418,10 +370,10 @@
 	mdelay(1);
 	write32(mmio + _PCH_DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 	/* Re-lock the registers.  */
 	write32(mmio + PCH_PP_CONTROL,
@@ -429,7 +381,7 @@
 
 	write32(mmio + PCH_LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
@@ -526,7 +478,7 @@
 	write32(mmio + PCH_LVDS,
 		LVDS_PORT_ENABLE
 		| (hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
@@ -562,35 +514,9 @@
 #endif
 
 	/* Linux relies on VBT for panel info.  */
-	optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START;
-	optionrom_pcir_t *pcir;
-	size_t vbt_size;
-	size_t fake_oprom_size;
-	struct device *dev;
+	generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
+				  "$VBT SNB/IVB-MOBILE ");
 
-	dev = dev_find_slot(0, PCI_DEVFN(2, 0));
-
-	memset(oh, 0, 8192);
-
-	oh->signature = OPROM_SIGNATURE;
-	oh->pcir_offset = 0x40;
-	oh->vbt_offset = 0x80;
-
-	pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
-	pcir->signature = 0x52494350;	// PCIR
-	pcir->vendor = dev->vendor;
-	pcir->device = dev->device;
-	pcir->length = sizeof(*pcir);
-	pcir->revision = dev->class;
-	pcir->classcode[0] = dev->class >> 8;
-	pcir->classcode[1] = dev->class >> 16;
-	pcir->classcode[2] = dev->class >> 24;
-	pcir->indicator = 0x80;
-
-	vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
-	fake_oprom_size = (0x80 + vbt_size + 511) / 512;
-	oh->size = fake_oprom_size;
-	pcir->imagelength = fake_oprom_size;
 	return 1;
 }
 
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index 77c5b6f..08cceea 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -26,7 +26,6 @@
 
 #include <drivers/intel/gma/edid.h>
 #include <drivers/intel/gma/i915.h>
-#include <drivers/intel/gma/intel_bios.h>
 #include "gma.h"
 #include "chip.h"
 #include <pc80/vga.h>
@@ -36,54 +35,6 @@
 
 #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
 
-static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf,
-			   void *vbt)
-{
-	struct vbt_header *head = vbt;
-	struct bdb_header *bdb_head;
-	struct bdb_general_features *genfeat;
-	u8 *ptr;
-
-	memset(head, 0, sizeof (*head));
-
-	memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20);
-	head->version = 100;
-	head->header_size = sizeof (*head);
-	head->bdb_offset = sizeof (*head);
-
-	bdb_head = (struct bdb_header *) (head + 1);
-	memset(bdb_head, 0, sizeof (*bdb_head));
-	memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
-	bdb_head->version = 0xa8;
-	bdb_head->header_size = sizeof (*bdb_head);
-
-	ptr = (u8 *) (bdb_head + 1);
-
-	ptr[0] = BDB_GENERAL_FEATURES;
-	ptr[1] = sizeof (*genfeat);
-	ptr[2] = sizeof (*genfeat) >> 8;
-	ptr += 3;
-
-	genfeat = (struct bdb_general_features *) ptr;
-	memset(genfeat, 0, sizeof (*genfeat));
-	genfeat->panel_fitting = 3;
-	genfeat->flexaim = 1;
-	genfeat->download_ext_vbt = 1;
-	genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
-	genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
-	genfeat->rsvd10 = 0x4;
-	genfeat->legacy_monitor_detect = 1;
-	genfeat->int_crt_support = 1;
-	genfeat->dp_ssc_enb = 1;
-
-	ptr += sizeof (*genfeat);
-
-	bdb_head->bdb_size = ptr - (u8 *)bdb_head;
-	head->vbt_size = ptr - (u8 *)head;
-	head->vbt_checksum = 0;
-	return ptr - (u8 *)head;
-}
-
 static void train_link(u32 mmio)
 {
 	/* Clear interrupts. */
@@ -171,7 +122,7 @@
 	read32(mmio + 0x000e1180); // = 0x40000002
 }
 
-int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
+int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 		u32 physbase, u16 piobase, u32 mmio, u32 lfb)
 {
 	int i;
@@ -187,7 +138,7 @@
 	u32 pixel_n = 1;
 	u32 pixel_m1 = 1;
 	u32 pixel_m2 = 1;
-	u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000;
+	u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000;
 	u32 data_m1;
 	u32 data_n1 = 0x00800000;
 	u32 link_m1;
@@ -252,7 +203,7 @@
 	hfront_porch = edid.hso;
 	vfront_porch = edid.vso;
 
-	target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock
+	target_frequency = info->lvds_dual_channel ? edid.pixel_clock
 		: (2 * edid.pixel_clock);
 #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_textmode_init();
@@ -323,7 +274,7 @@
 
 	link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
 	data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
-		/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4));
+		/ (link_frequency * 8 * (info->lvds_num_lanes ? : 4));
 
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
 	       hactive, vactive);
@@ -335,10 +286,10 @@
 	       hsync, vsync);
 	printk(BIOS_DEBUG, "Front porch %d x %d\n",
 	       hfront_porch, vfront_porch);
-	printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock
+	printk(BIOS_DEBUG, (info->use_spread_spectrum_clock
 			    ? "Spread spectrum clock\n" : "DREF clock\n"));
 	printk(BIOS_DEBUG,
-	       info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
+	       info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
 	printk(BIOS_DEBUG, "Polarities %d, %d\n",
 	       hpolarity, vpolarity);
 	printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@@ -355,12 +306,12 @@
 
 	write32(mmio + PCH_LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
 	write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
-	write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock
+	write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
 					  ? 0x1002 : 0x400));
 	mdelay(1);
 	write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
@@ -371,18 +322,18 @@
 	write32(mmio + PCH_DPLL_SEL, 8);
 	write32(mmio + _PCH_DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 	mdelay(1);
 	write32(mmio + _PCH_DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 	/* Re-lock the registers.  */
 	write32(mmio + PCH_PP_CONTROL,
@@ -390,7 +341,7 @@
 
 	write32(mmio + PCH_LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
@@ -487,7 +438,7 @@
 	write32(mmio + PCH_LVDS,
 		LVDS_PORT_ENABLE
 		| (hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
@@ -522,35 +473,8 @@
 #endif
 
 	/* Linux relies on VBT for panel info.  */
-	optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START;
-	optionrom_pcir_t *pcir;
-	size_t vbt_size;
-	size_t fake_oprom_size;
-	struct device *dev;
-
-	dev = dev_find_slot(0, PCI_DEVFN(2, 0));
-
-	memset(oh, 0, 8192);
-
-	oh->signature = OPROM_SIGNATURE;
-	oh->pcir_offset = 0x40;
-	oh->vbt_offset = 0x80;
-
-	pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
-	pcir->signature = 0x52494350;	// PCIR
-	pcir->vendor = dev->vendor;
-	pcir->device = dev->device;
-	pcir->length = sizeof(*pcir);
-	pcir->revision = dev->class;
-	pcir->classcode[0] = dev->class >> 8;
-	pcir->classcode[1] = dev->class >> 16;
-	pcir->classcode[2] = dev->class >> 24;
-	pcir->indicator = 0x80;
-
-	vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
-	fake_oprom_size = (0x80 + vbt_size + 511) / 512;
-	oh->size = fake_oprom_size;
-	pcir->imagelength = fake_oprom_size;
+	generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
+				  "$VBT SNB/IVB-MOBILE ");
 
 	return 1;
 }