diff --git a/Documentation/mainboard/hp/pro_3500_series.md b/Documentation/mainboard/hp/pro_3500_series.md
new file mode 100644
index 0000000..241b567
--- /dev/null
+++ b/Documentation/mainboard/hp/pro_3500_series.md
@@ -0,0 +1,103 @@
+# HP Pro 3500 Series
+
+This page describes how to run coreboot on the [Pro 3500 Series]
+desktop from [HP].
+
+## State
+
+All peripherals should work. Automatic fan control as well as S3 are
+working. The board was tested to boot Linux and Windows. EHCI debug
+is untested. When using MrChromebox edk2 with secure boot build in, the
+board will hang on each boot for about 20 seconds before continuing.
+With disabled ME, the SuperIO will not get CPU temperatures via PECI and
+therefore the automatic fan control will not increase the fan speed.
+
+## Flashing coreboot
+
+```{eval_rst}
++---------------------+-------------------------+
+| Type                | Value                   |
++=====================+=========================+
+| Socketed flash      | No                      |
++---------------------+-------------------------+
+| Model               | W25Q64FVSIG             |
++---------------------+-------------------------+
+| Size                | 8 MiB                   |
++---------------------+-------------------------+
+| In circuit flashing | Yes                     |
++---------------------+-------------------------+
+| Package             | SOIC-8                  |
++---------------------+-------------------------+
+| Write protection    | See below               |
++---------------------+-------------------------+
+| Dual BIOS feature   | No                      |
++---------------------+-------------------------+
+| Internal flashing   | Yes                     |
++---------------------+-------------------------+
+```
+
+### Flash layout
+The original layout of the flash should look like this:
+```
+00000000:00000fff fd
+00400000:007fffff bios
+00001000:003fffff me
+00fff000:00000fff gbe
+00fff000:00000fff pd
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom] (although it reports as
+"N25Q064..3E", it works fine).
+
+With a missing FDO jumper, `fd` region is read-only, `bios` region is
+read-write and `me` region is locked. Vendor firmware will additionally
+protect the flash chip. After shorting the FDO jumper (E2) full
+read-write access is granted.
+
+Do **NOT shutdown** the operating system **after flashing** coreboot
+from the vendor firmware! This will brick your device because the bios
+region will be modified on shutdown. Cut the AC power or do a restart
+from the OS.
+
+**Position of FDO jumper (E2) close to the F_USB3**
+![][pro_3500_jumper]
+
+[pro_3500_jumper]: pro_3500_series_jumper.avif
+
+### External programming
+
+External programming with an SPI adapter and [flashrom] does work, but
+it powers the whole southbridge complex. The average current will be
+400mA but spikes may be higher. Connect the power to the flash or the
+programming header next to the flash otherwise programming is unstable.
+The supply needs to quickly reach 3V3 or else the chip is also unstable
+until cleanly power cycled.
+
+**Position of SOIC-8 flash and pin-header near ATX power connector**
+![][pro_3500_flash]
+
+[pro_3500_flash]: pro_3500_series_flash.avif
+
+## Technology
+
+```{eval_rst}
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x (bd82h61)                                |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| SuperIO          | IT8779E (identifies as IT8772F via register)     |
++------------------+--------------------------------------------------+
+| EC               | Fixed function as part of SuperIO                |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
+```
+
+[Pro 3500 Series]: https://support.hp.com/us-en/document/c03364089
+[HP]: https://www.hp.com/
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/hp/pro_3500_series_flash.avif b/Documentation/mainboard/hp/pro_3500_series_flash.avif
new file mode 100644
index 0000000..764feb1
--- /dev/null
+++ b/Documentation/mainboard/hp/pro_3500_series_flash.avif
Binary files differ
diff --git a/Documentation/mainboard/hp/pro_3500_series_jumper.avif b/Documentation/mainboard/hp/pro_3500_series_jumper.avif
new file mode 100644
index 0000000..5cbdcd4
--- /dev/null
+++ b/Documentation/mainboard/hp/pro_3500_series_jumper.avif
Binary files differ
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 6178738..7559628 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -127,6 +127,7 @@
 
 Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
 Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
+Pro 3500 Series <hp/pro_3500_series.md>
 Z220 Workstation SFF <hp/z220_sff.md>
 ```
 
diff --git a/src/mainboard/hp/pro_3500_series/Kconfig b/src/mainboard/hp/pro_3500_series/Kconfig
new file mode 100644
index 0000000..ab77654
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if BOARD_HP_PRO_3500_SERIES
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select NO_UART_ON_SUPERIO
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_ITE_IT8772F
+	select USE_NATIVE_RAMINIT
+
+config CBFS_SIZE
+	default 0x400000
+
+config MAINBOARD_DIR
+	default "hp/pro_3500_series"
+
+config MAINBOARD_PART_NUMBER
+	default "Pro 3500 Series"
+
+config VGA_BIOS_ID
+	default "8086,0152"
+
+config DRAM_RESET_GATE_GPIO
+	default 60
+
+config USBDEBUG_HCD_INDEX
+	default 2
+endif
diff --git a/src/mainboard/hp/pro_3500_series/Kconfig.name b/src/mainboard/hp/pro_3500_series/Kconfig.name
new file mode 100644
index 0000000..fd1222c
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/Kconfig.name
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config BOARD_HP_PRO_3500_SERIES
+	bool "Pro 3500 Series"
diff --git a/src/mainboard/hp/pro_3500_series/Makefile.mk b/src/mainboard/hp/pro_3500_series/Makefile.mk
new file mode 100644
index 0000000..6554ed5
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/Makefile.mk
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+bootblock-y += led.c
+
+romstage-y += early_init.c
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+
+smm-y += led.c
diff --git a/src/mainboard/hp/pro_3500_series/acpi/ec.asl b/src/mainboard/hp/pro_3500_series/acpi/ec.asl
new file mode 100644
index 0000000..16990d4
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/hp/pro_3500_series/acpi/platform.asl b/src/mainboard/hp/pro_3500_series/acpi/platform.asl
new file mode 100644
index 0000000..aff432b
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/hp/pro_3500_series/acpi/superio.asl b/src/mainboard/hp/pro_3500_series/acpi/superio.asl
new file mode 100644
index 0000000..829a391
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/acpi/superio.asl
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Values should match those defined in devicetree.cb */
+
+#undef SIO_ENABLE_FDC0           // pnp 2e.0: Disable Floppy Controller
+#undef SIO_ENABLE_COM1           // pnp 2e.1: Disable Serial Port 1
+#undef SIO_ENABLE_PS2K           // pnp 2e.5: Disable PS/2 Keyboard
+#undef SIO_ENABLE_PS2M           // pnp 2e.6: Disable PS/2 Mouse
+#undef SIO_ENABLE_INFR           // pnp 2e.a: Disable Consumer IR
+
+#define SIO_ENABLE_ENVC          // pnp 2e.4: Enable Environmental Controller
+#define SIO_ENVC_IO0      0xa30  // pnp 2e.4: io 0x60
+#define SIO_ENVC_IO1      0xa20  // pnp 2e.4: io 0x62
+#define SIO_ENABLE_GPIO          // pnp 2e.7: Enable GPIO
+#define SIO_GPIO_IO0      0x0    // pnp 2e.7: io 0x60
+#define SIO_GPIO_IO1      0xa00  // pnp 2e.7: io 0x62
+
+#include <superio/ite/it8772f/acpi/superio.asl>
diff --git a/src/mainboard/hp/pro_3500_series/acpi_tables.c b/src/mainboard/hp/pro_3500_series/acpi_tables.c
new file mode 100644
index 0000000..230584e
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/acpi_tables.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+	gnvs->tcrt = 100;
+	gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/hp/pro_3500_series/board_info.txt b/src/mainboard/hp/pro_3500_series/board_info.txt
new file mode 100644
index 0000000..1780394
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/hp/pro_3500_series/common_defines.h b/src/mainboard/hp/pro_3500_series/common_defines.h
new file mode 100644
index 0000000..e3c25ca
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/common_defines.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MAINBOARD_COMMON_DEFINES_H
+#define __MAINBOARD_COMMON_DEFINES_H
+
+#include <superio/ite/it8772f/it8772f.h>
+
+#define IT8772F_BASE	0x2e
+#define EC_DEV		PNP_DEV(IT8772F_BASE, IT8772F_EC)
+#define GPIO_DEV	PNP_DEV(IT8772F_BASE, IT8772F_GPIO)
+
+#endif /* __MAINBOARD_COMMON_DEFINES_H */
diff --git a/src/mainboard/hp/pro_3500_series/data.vbt b/src/mainboard/hp/pro_3500_series/data.vbt
new file mode 100644
index 0000000..7309d99
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/data.vbt
Binary files differ
diff --git a/src/mainboard/hp/pro_3500_series/devicetree.cb b/src/mainboard/hp/pro_3500_series/devicetree.cb
new file mode 100644
index 0000000..cf75313
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/devicetree.cb
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	# XMM1: CH0S0 0x50
+	# XMM3: CH1S0 0x52
+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+	device domain 0x0 on
+		subsystemid 0x103c 0x2abf inherit
+
+		device ref peg10 on end
+		device ref igd on end
+
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "gen1_dec" = "0x003c0a01"
+			register "pcie_port_coalesce" = "1"
+			register "sata_interface_speed_support" = "0x3"
+			# SATA0: ata1 0x01
+			# SATA1: ata2 0x02
+			# SATA2: ata5 0x10
+			# SATA3: ata6 0x20
+			register "sata_port_map" = "0x33"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+			device ref ehci2 on end
+			device ref hda on end
+			device ref pcie_rp2 on end # MINI_PCIE
+			device ref pcie_rp3 on end # PCIEx1_1
+			device ref pcie_rp4 on end # PCIEx1_2
+			device ref pcie_rp5 on end # PCIEx1_3
+			device ref pcie_rp6 on end # RTL8171EH
+			device ref ehci1 on end
+			device ref lpc on
+				chip superio/ite/it8772f
+					# GPIO registers all zero or written by LED code
+
+					register "ec.smbus_en"		= "1"
+
+					register "TMPIN1.mode"		= "THERMAL_MODE_DISABLED"
+					register "TMPIN2.mode"		= "THERMAL_DIODE" # Near ATX_CPU connector
+					register "TMPIN3.mode"		= "THERMAL_PECI"
+					# TMPIN3.offset is set to TJ_MAX at runtime
+
+					# CPU fan
+					register "FAN2.mode"		= "FAN_SMART_AUTOMATIC"
+					register "FAN2.smart.tmpin"	= "3"
+					register "FAN2.smart.tmp_off"	= "-127"
+					register "FAN2.smart.tmp_start"	= "40"
+					register "FAN2.smart.tmp_full"	= "86"
+					register "FAN2.smart.tmp_delta"	= "5"
+					register "FAN2.smart.pwm_start"	= "25"
+					register "FAN2.smart.slope"	= "6"
+					# System fan
+					register "FAN3.mode"		= "FAN_SMART_AUTOMATIC"
+					register "FAN3.smart.tmpin"	= "3"
+					register "FAN3.smart.tmp_off"	= "-127"
+					register "FAN3.smart.tmp_start"	= "40"
+					register "FAN3.smart.tmp_full"	= "86"
+					register "FAN3.smart.tmp_delta"	= "5"
+					register "FAN3.smart.pwm_start"	= "34"
+					register "FAN3.smart.slope"	= "11"
+
+					register "FAN_VECA.tmpin"	= "2"
+					register "FAN_VECA.fanout"	= "2"
+					register "FAN_VECA.tmp_start"	= "57"
+					register "FAN_VECA.tmp_delta"	= "5"
+					register "FAN_VECA.slope"	= "26"
+
+					register "FAN_VECB.tmpin"	= "2"
+					register "FAN_VECB.fanout"	= "3"
+					register "FAN_VECB.tmp_start"	= "48"
+					register "FAN_VECB.tmp_delta"	= "5"
+					register "FAN_VECB.slope"	= "5"
+
+					register "ec.vin_mask"		= "VIN_ALL"
+
+					device pnp 2e.0 off end # FDC
+					device pnp 2e.1 off end # Serial Port 1
+					device pnp 2e.4 on # Environment Controller
+						io 0x60 = 0xa30
+						io 0x62 = 0xa20
+					end
+					device pnp 2e.7 on # GPIO
+						io 0x60 = 0x0
+						io 0x62 = 0xa00
+					end
+					device pnp 2e.5 off end # Keyboard, enabled in vendor firmware but missing connector
+					device pnp 2e.6 off end # Mouse   , enabled in vendor firmware but missing connector
+					device pnp 2e.a off end # IR
+				end
+			end
+			device ref sata1 on end
+		end
+	end
+end
diff --git a/src/mainboard/hp/pro_3500_series/dsdt.asl b/src/mainboard/hp/pro_3500_series/dsdt.asl
new file mode 100644
index 0000000..cbdf0c6
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/dsdt.asl
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/hp/pro_3500_series/early_init.c b/src/mainboard/hp/pro_3500_series/early_init.c
new file mode 100644
index 0000000..fbf73cfb
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/early_init.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <superio/ite/common/ite.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/hwm5_conf.h>
+#include "common_defines.h"
+#include "led.h"
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1,  6, 0 },
+	{ 1,  6, 0 },
+	{ 1,  6, 1 },
+	{ 1,  9, 1 },
+	{ 1, 10, 2 },
+	{ 1, 11, 2 },
+	{ 1,  6, 3 },
+	{ 1,  6, 3 },
+	{ 1,  6, 4 },
+	{ 1, 12, 4 },
+	{ 1,  6, 6 },
+	{ 1, 11, 5 },
+	{ 1,  6, 5 },
+	{ 1,  6, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
+
+	/* Early SuperIO setup */
+	ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24);
+	/* Clear when resuming from S3: */
+	ite_disable_3vsbsw(GPIO_DEV);
+	ite_disable_pme_out(EC_DEV);
+	ite_ac_resume_southbridge(EC_DEV);
+
+	set_power_led(LED_WHITE);
+}
diff --git a/src/mainboard/hp/pro_3500_series/gma-mainboard.ads b/src/mainboard/hp/pro_3500_series/gma-mainboard.ads
new file mode 100644
index 0000000..c9e4326
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/gma-mainboard.ads
@@ -0,0 +1,16 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/pro_3500_series/gpio.c b/src/mainboard/hp/pro_3500_series/gpio.c
new file mode 100644
index 0000000..3ab365f
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/gpio.c
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_NATIVE,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_NATIVE,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_GPIO,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio49 = GPIO_LEVEL_HIGH,
+	.gpio57 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_LOW,
+	.gpio61 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/hp/pro_3500_series/hda_verb.c b/src/mainboard/hp/pro_3500_series/hda_verb.c
new file mode 100644
index 0000000..4b3104e
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/hda_verb.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0662,	/* Codec Vendor / Device ID: Realtek */
+	0x103c2abf,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x103c2abf),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19830),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19831),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x0221401f),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/pro_3500_series/led.c b/src/mainboard/hp/pro_3500_series/led.c
new file mode 100644
index 0000000..073f5f5
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/led.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "common_defines.h"
+#include "led.h"
+
+void set_power_led(int state)
+{
+	// Board has a dual color LED
+	it8772f_gpio_setup(
+		GPIO_DEV,
+		2,			/* set */
+		0xf3 | LED_BOTH,	/* select, 0xf3 is default */
+		state,			/* polarity */
+		0x00,			/* pullup */
+		LED_BOTH,		/* output */
+		0x00);			/* enable */
+}
diff --git a/src/mainboard/hp/pro_3500_series/led.h b/src/mainboard/hp/pro_3500_series/led.h
new file mode 100644
index 0000000..b0e7595
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/led.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MAINBOARD_LED_H
+#define __MAINBOARD_LED_H
+
+#ifndef __ACPI__
+void set_power_led(int state);
+
+enum {
+	LED_WHITE =  1 << 2, // GPIO 22
+	LED_YELLOW = 1 << 3, // GPIO 23
+	LED_BOTH = LED_WHITE | LED_YELLOW,
+	LED_OFF = LED_BOTH
+};
+#endif
+
+#endif /* __MAINBOARD_LED_H */
diff --git a/src/mainboard/hp/pro_3500_series/mainboard.c b/src/mainboard/hp/pro_3500_series/mainboard.c
new file mode 100644
index 0000000..a3b7504
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/mainboard.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <cpu/x86/msr.h>
+#include <device/device.h>
+#include <static_devices.h>
+#include <superio/ite/it8772f/chip.h>
+
+static u8 cpu_get_temp_offset(void)
+{
+	msr_t msr = rdmsr(MSR_TEMPERATURE_TARGET);
+	u8 tj_max = (msr.lo >> 16) & 0xFF;
+	u8 tcc_offset = (msr.lo >> 24) & 0xf;
+
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if (msr.lo & (1 << 30)) {
+		return tj_max - tcc_offset;
+	} else {
+		return tj_max;
+	}
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	/* Set PECI TMPIN 3 offset to TJ_MAX temperature */
+	struct superio_ite_it8772f_config *const config = __pnp_002e_04->chip_info;
+	if (config)
+		config->ec.tmpin[2].offset = cpu_get_temp_offset();
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/hp/pro_3500_series/smihandler.c b/src/mainboard/hp/pro_3500_series/smihandler.c
new file mode 100644
index 0000000..a11db5d
--- /dev/null
+++ b/src/mainboard/hp/pro_3500_series/smihandler.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <superio/ite/common/ite.h>
+#include "common_defines.h"
+#include "led.h"
+
+/* Change power led state based on sleep type. */
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	printk(BIOS_DEBUG, "SMI: sleep S%d\n", slp_typ);
+	switch (slp_typ) {
+	case ACPI_S3:
+		/*
+		 * Vendor firmware also only enables this when entering sleep.
+		 * This saves some power when entering S5 via shutdown.
+		 */
+		ite_enable_3vsbsw(GPIO_DEV);
+		set_power_led(LED_YELLOW);
+		break;
+	case ACPI_S4:
+		/* Without 3vsbsw enabled the LED will be off in any case */
+	case ACPI_S5:
+		set_power_led(LED_OFF);
+		break;
+	default:
+		break;
+	}
+}