C and other Super I/O cosmetic fixes.
- Random coding style, whitespace and cosmetic fixes.
- Consistently use the same spacing and 4-hexdigit port number format
in the pnp_dev_info[] arrays.
- Drop dead/unused code and less useful comments.
- Add missing "(C)" characters and copyright years.
- Shorten and simplify some code snippets.
- Use u8/u16/etc. everywhere.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/superio/smsc/fdc37m60x/Makefile.inc b/src/superio/smsc/fdc37m60x/Makefile.inc
index 197ecd3..b6d524d 100644
--- a/src/superio/smsc/fdc37m60x/Makefile.inc
+++ b/src/superio/smsc/fdc37m60x/Makefile.inc
@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_FDC37M60X) += superio.c
+
diff --git a/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c b/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c
index 1c1d334..d8cd8c6 100644
--- a/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c
+++ b/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c
@@ -24,7 +24,7 @@
/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */
#define SIO_BASE 0x3f0
#define SIO_INDEX SIO_BASE
-#define SIO_DATA SIO_BASE+1
+#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */
#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */
@@ -37,7 +37,7 @@
/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the
LDN the register belongs to, before you can access the register. */
-static void fdc37m60x_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value)
{
outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE);
outb(ldn, SIO_DATA);
@@ -46,7 +46,7 @@
}
/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */
-static void fdc37m60x_enable_serial(device_t dev, unsigned iobase)
+static void fdc37m60x_enable_serial(device_t dev, u16 iobase)
{
/* (1) Enter the configuration state. */
outb(0x55, FDC37M60X_CONFIGURATION_PORT);
diff --git a/src/superio/smsc/fdc37m60x/superio.c b/src/superio/smsc/fdc37m60x/superio.c
index 0fc5eaa..d074c64 100644
--- a/src/superio/smsc/fdc37m60x/superio.c
+++ b/src/superio/smsc/fdc37m60x/superio.c
@@ -28,14 +28,11 @@
static void init(device_t dev)
{
- struct superio_smsc_fdc37m60x_config *conf;
+ struct superio_smsc_fdc37m60x_config *conf = dev->chip_info;
struct resource *res0;
- if (!dev->enabled) {
+ if (!dev->enabled)
return;
- }
-
- conf = dev->chip_info;
switch (dev->path.pnp.device) {
case FDC37M60X_FDC: /* TODO. */
@@ -68,9 +65,9 @@
/* TODO: FDC, PP, AUX. */
static struct pnp_info pnp_dev_info[] = {
- { &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
- { &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+ { &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
+ { &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/smsc/fdc37n972/Makefile.inc b/src/superio/smsc/fdc37n972/Makefile.inc
index 7139f68..3b1a190 100644
--- a/src/superio/smsc/fdc37n972/Makefile.inc
+++ b/src/superio/smsc/fdc37n972/Makefile.inc
@@ -18,3 +18,4 @@
##
ramstage-$(CONFIG_SUPERIO_SMSC_FDC37N972) += fdc37n972.c
+
diff --git a/src/superio/smsc/fdc37n972/fdc37n972.c b/src/superio/smsc/fdc37n972/fdc37n972.c
index 672e25e..9f94909 100644
--- a/src/superio/smsc/fdc37n972/fdc37n972.c
+++ b/src/superio/smsc/fdc37n972/fdc37n972.c
@@ -27,13 +27,10 @@
static void init(device_t dev)
{
- struct superio_smsc_fdc37n972_config *conf;
+ struct superio_smsc_fdc37n972_config *conf = dev->chip_info;
- if (!dev->enabled) {
+ if (!dev->enabled)
return;
- }
-
- conf = dev->chip_info;
switch (dev->path.pnp.device) {
case FDC37N972_FDC: /* TODO. */
@@ -56,9 +53,9 @@
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, FDC37N972_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
- { &ops, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+ { &ops, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, FDC37N972_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
+ { &ops, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/smsc/lpc47b272/Makefile.inc b/src/superio/smsc/lpc47b272/Makefile.inc
index e3ca5f2..c688f02 100644
--- a/src/superio/smsc/lpc47b272/Makefile.inc
+++ b/src/superio/smsc/lpc47b272/Makefile.inc
@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.c
+
diff --git a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c b/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
index 0c31b3a..75093ea 100644
--- a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
+++ b/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
@@ -23,17 +23,15 @@
#include <arch/romcc_io.h>
#include "lpc47b272.h"
-/** Enable access to the LPC47B272's configuration registers. */
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0x55, port);
}
-/** Disable access to the LPC47B272's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0xaa, port);
}
@@ -44,7 +42,7 @@
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Processor I/O port address to assign to this serial device.
*/
-static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
+static void lpc47b272_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c
index 7fd1a9d..5bf385c 100644
--- a/src/superio/smsc/lpc47b272/superio.c
+++ b/src/superio/smsc/lpc47b272/superio.c
@@ -45,7 +45,7 @@
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
-//static void dump_pnp_device(device_t dev);
+// static void dump_pnp_device(device_t dev);
struct chip_operations superio_smsc_lpc47b272_ops = {
CHIP_NAME("SMSC LPC47B272 Super I/O")
@@ -61,12 +61,12 @@
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
- { &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, },
+ { &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
+ { &ops, LPC47B272_RT, PNP_IO0, {0x0780, 0}, },
};
/**
@@ -105,13 +105,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
-
- if(dev->enabled) {
- pnp_set_enable(dev, 1);
- }
- else {
- pnp_set_enable(dev, 0);
- }
+ pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@@ -136,25 +130,21 @@
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
-
case LPC47B272_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
-
case LPC47B272_KBC:
pc_keyboard_init(&conf->keyboard);
break;
}
}
-/** Enable access to the LPC47B272's configuration registers. */
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
-/** Disable access to the LPC47B272's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
@@ -170,28 +160,30 @@
*/
static void dump_pnp_device(device_t dev)
{
- int register_index;
+ int i;
print_debug("\n");
- for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
- uint8_t register_value;
+ for (i = 0; i <= LPC47B272_MAX_CONFIG_REGISTER; i++) {
+ u8 register_value;
- if ((register_index & 0x0f) == 0) {
- print_debug_hex8(register_index);
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
print_debug_char(':');
}
- /* Skip over 'register' that would cause exit from configuration mode */
- if (register_index == 0xaa)
+ /*
+ * Skip over 'register' that would cause exit from
+ * configuration mode.
+ */
+ if (i == 0xaa)
register_value = 0xaa;
else
- register_value = pnp_read_config(dev, register_index);
+ register_value = pnp_read_config(dev, i);
print_debug_char(' ');
print_debug_hex8(register_value);
- if ((register_index & 0x0f) == 0x0f) {
+ if ((i & 0x0f) == 0x0f)
print_debug("\n");
- }
}
print_debug("\n");
diff --git a/src/superio/smsc/lpc47b397/Makefile.inc b/src/superio/smsc/lpc47b397/Makefile.inc
index 56d97a1..68b6ecd 100644
--- a/src/superio/smsc/lpc47b397/Makefile.inc
+++ b/src/superio/smsc/lpc47b397/Makefile.inc
@@ -20,5 +20,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c
+
diff --git a/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c b/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
index 8eff232..16066b7 100644
--- a/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
+++ b/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
@@ -20,30 +20,30 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-static void lpc47b397_gpio_offset_out(unsigned iobase, unsigned offset, unsigned value)
+static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value)
{
- outb(value,iobase+offset);
+ outb(value, iobase + offset);
}
-static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset)
+static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset)
{
return inb(iobase+offset);
}
#if 0
-/* for GP60-GP64, GP66-GP85 */
+/* For GP60-GP64, GP66-GP85. */
#define LPC47B397_GPIO_CNTL_INDEX 0x70
#define LPC47B397_GPIO_CNTL_DATA 0x71
-static void lpc47b397_gpio_index_out(unsigned iobase, unsigned index, unsigned value)
+static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value)
{
- outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX);
- outb(value, iobase+LPC47B397_GPIO_CNTL_DATA);
+ outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
+ outb(value, iobase + LPC47B397_GPIO_CNTL_DATA);
}
-static unsigned lpc47b397_gpio_index_in(unsigned iobase, unsigned index)
+static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index)
{
- outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX);
- return inb(iobase+LPC47B397_GPIO_CNTL_DATA);
+ outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
+ return inb(iobase + LPC47B397_GPIO_CNTL_DATA);
}
#endif
diff --git a/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c b/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
index e81b6a0..bea97b4 100644
--- a/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
+++ b/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
@@ -23,19 +23,19 @@
#include <arch/romcc_io.h>
#include "lpc47b397.h"
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0x55, port);
}
static void pnp_exit_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0xaa, port);
}
-static void lpc47b397_enable_serial(device_t dev, unsigned iobase)
+static void lpc47b397_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c
index 1e4ac80..9c4d8d9 100644
--- a/src/superio/smsc/lpc47b397/superio.c
+++ b/src/superio/smsc/lpc47b397/superio.c
@@ -37,41 +37,42 @@
{
outb(0x55, dev->path.pnp.port);
}
+
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
}
-static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
+static void pnp_write_index(u16 port, u8 reg, u8 value)
{
- outb(reg, port_base);
- outb(value, port_base + 1);
+ outb(reg, port);
+ outb(value, port + 1);
}
-static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
+static u8 pnp_read_index(u16 port, u8 reg)
{
- outb(reg, port_base);
- return inb(port_base + 1);
+ outb(reg, port);
+ return inb(port + 1);
}
static void enable_hwm_smbus(device_t dev)
{
- /* enable SensorBus register access */
- uint8_t reg, value;
- reg = 0xf0;
- value = pnp_read_config(dev, reg);
- value |= 0x01;
- pnp_write_config(dev, reg, value);
+ /* Enable SensorBus register access. */
+ u8 reg8;
+
+ reg8 = pnp_read_config(dev, 0xf0);
+ reg8 |= (1 << 1);
+ pnp_write_config(dev, 0xf0, reg8);
}
static void lpc47b397_init(device_t dev)
{
- struct superio_smsc_lpc47b397_config *conf;
+ struct superio_smsc_lpc47b397_config *conf = dev->chip_info;
struct resource *res0;
- if (!dev->enabled) {
+
+ if (!dev->enabled)
return;
- }
- conf = dev->chip_info;
+
switch(dev->path.pnp.device) {
case LPC47B397_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
@@ -91,9 +92,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_resources(dev);
-#if 0
- dump_pnp_device(dev);
-#endif
+ /* dump_pnp_device(dev); */
pnp_exit_conf_state(dev);
}
@@ -104,14 +103,12 @@
switch(dev->path.pnp.device) {
case LPC47B397_HWM:
- printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\n");
+ printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n");
pnp_set_logical_device(dev);
enable_hwm_smbus(dev);
break;
}
-#if 0
- dump_pnp_device(dev);
-#endif
+ /* dump_pnp_device(dev); */
pnp_exit_conf_state(dev);
}
@@ -119,13 +116,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
-
- if(dev->enabled) {
- pnp_set_enable(dev, 1);
- }
- else {
- pnp_set_enable(dev, 0);
- }
+ pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@@ -145,9 +136,9 @@
#define SB_DATA2 0x0e
#define SB_DATA3 0x0f
-static int lsmbus_read_byte(device_t dev, uint8_t address)
+static int lsmbus_read_byte(device_t dev, u8 address)
{
- unsigned device;
+ unsigned int device;
struct resource *res;
int result;
@@ -155,24 +146,26 @@
res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
- pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */
+ pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */
- result = pnp_read_index(res->base+SB_INDEX, address); /* we only read it one byte one time */
+ /* We only read it one byte one time. */
+ result = pnp_read_index(res->base + SB_INDEX, address);
return result;
}
-static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
+static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
{
- unsigned device;
+ unsigned int device;
struct resource *res;
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
- pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */
+ pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */
- pnp_write_index(res->base+SB_INDEX, address, val); /* we only write it one byte one time */
+ /* We only write it one byte one time. */
+ pnp_write_index(res->base+SB_INDEX, address, val);
return 0;
}
@@ -183,6 +176,7 @@
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
};
+
static struct device_operations ops_hwm = {
.read_resources = pnp_read_resources,
.set_resources = lpc47b397_pnp_set_resources,
@@ -194,13 +188,13 @@
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
- { &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, },
- { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, },
+ { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
+ { &ops_hwm, LPC47B397_HWM, PNP_IO0, {0x07f0, 0}, },
+ { &ops, LPC47B397_RT, PNP_IO0, {0x0780, 0}, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/smsc/lpc47m10x/Makefile.inc b/src/superio/smsc/lpc47m10x/Makefile.inc
index 578a8a7..3f71601 100644
--- a/src/superio/smsc/lpc47m10x/Makefile.inc
+++ b/src/superio/smsc/lpc47m10x/Makefile.inc
@@ -22,5 +22,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.c
+
diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h
index 604016c..4c78d9e 100644
--- a/src/superio/smsc/lpc47m10x/lpc47m10x.h
+++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h
@@ -28,9 +28,9 @@
#define LPC47M10X2_SP1 4 /* Com1 */
#define LPC47M10X2_SP2 5 /* Com2 */
#define LPC47M10X2_KBC 7 /* Keyboard & Mouse */
-#define LPC47M10X2_GAME 9 /* GAME */
+#define LPC47M10X2_GAME 9 /* GAME */
#define LPC47M10X2_PME 10 /* PME reg*/
-#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/
+#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/ // FIXME
#define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F
diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c b/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
index e2aa63a..06cf7d4 100644
--- a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
+++ b/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
@@ -1,6 +1,5 @@
/*
- * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
- * derived from lpc47n217
+ * This file is part of the coreboot project.
*
* Copyright (C) 2005 Digital Design Corporation
*
@@ -22,17 +21,15 @@
#include <arch/romcc_io.h>
#include "lpc47m10x.h"
-/** Enable access to the LPC47M10X2's configuration registers. */
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0x55, port);
}
-/** Disable access to the LPC47M10X2's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0xaa, port);
}
@@ -43,7 +40,7 @@
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Processor I/O port address to assign to this serial device.
*/
-static void lpc47m10x_enable_serial(device_t dev, unsigned iobase)
+static void lpc47m10x_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c
index 1cb7e7d..c935d62 100644
--- a/src/superio/smsc/lpc47m10x/superio.c
+++ b/src/superio/smsc/lpc47m10x/superio.c
@@ -1,11 +1,11 @@
/*
- * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
+ * This file is part of the coreboot project.
*
- * Copyright 2000 AG Electronics Ltd.
- * Copyright 2003-2004 Linux Networx
- * Copyright 2004 Tyan
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
* Copyright (C) 2005 Digital Design Corporation
- * Copyright (C) Ron Minnich, LANL
+ * Copyright (C) 2006 Ron Minnich, LANL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -44,7 +44,7 @@
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
-//static void dump_pnp_device(device_t dev);
+// static void dump_pnp_device(device_t dev);
struct chip_operations superio_smsc_lpc47m10x_ops = {
CHIP_NAME("SMSC LPC47M10x Super I/O")
@@ -60,11 +60,11 @@
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
};
/**
@@ -103,13 +103,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
-
- if(dev->enabled) {
- pnp_set_enable(dev, 1);
- }
- else {
- pnp_set_enable(dev, 0);
- }
+ pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@@ -134,25 +128,21 @@
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
-
case LPC47M10X2_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
-
case LPC47M10X2_KBC:
pc_keyboard_init(&conf->keyboard);
break;
}
}
-/** Enable access to the LPC47M10X2's configuration registers. */
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
-/** Disable access to the LPC47M10X2's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
@@ -168,30 +158,32 @@
*/
static void dump_pnp_device(device_t dev)
{
- int register_index;
+ int i;
print_debug("\n");
- for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) {
- uint8_t register_value;
+ for (i = 0; i <= LPC47M10X2_MAX_CONFIG_REGISTER; i++) {
+ u8 register_value;
- if ((register_index & 0x0f) == 0) {
- print_debug_hex8(register_index);
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
print_debug_char(':');
}
- /* Skip over 'register' that would cause exit from configuration mode */
- if (register_index == 0xaa)
+ /*
+ * Skip over 'register' that would cause exit from
+ * configuration mode.
+ */
+ if (i == 0xaa)
register_value = 0xaa;
else
- register_value = pnp_read_config(dev, register_index);
+ register_value = pnp_read_config(dev, i);
print_debug_char(' ');
print_debug_hex8(register_value);
- if ((register_index & 0x0f) == 0x0f) {
+ if ((i & 0x0f) == 0x0f)
print_debug("\n");
- }
}
- print_debug("\n");
+ print_debug("\n");
}
#endif
diff --git a/src/superio/smsc/lpc47m15x/Makefile.inc b/src/superio/smsc/lpc47m15x/Makefile.inc
index 1d3853f..cca8ba6 100644
--- a/src/superio/smsc/lpc47m15x/Makefile.inc
+++ b/src/superio/smsc/lpc47m15x/Makefile.inc
@@ -17,5 +17,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.c
+
diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x.h b/src/superio/smsc/lpc47m15x/lpc47m15x.h
index 5f62466..f53afb9 100644
--- a/src/superio/smsc/lpc47m15x/lpc47m15x.h
+++ b/src/superio/smsc/lpc47m15x/lpc47m15x.h
@@ -25,7 +25,7 @@
#define LPC47M15X_SP1 4 /* Com1 */
#define LPC47M15X_SP2 5 /* Com2 */
#define LPC47M15X_KBC 7 /* Keyboard & Mouse */
-#define LPC47M15X_GAME 9 /* GAME */
+#define LPC47M15X_GAME 9 /* GAME */
#define LPC47M15X_PME 10 /* PME reg*/
#define LPC47M15X_MPU 11 /* MPE -- who knows -- reg*/
diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c b/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c
index b252fd8..18b652e 100644
--- a/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c
+++ b/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c
@@ -22,19 +22,19 @@
#include <arch/romcc_io.h>
#include "lpc47m15x.h"
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0x55, port);
}
static void pnp_exit_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0xaa, port);
}
-static inline void lpc47m15x_enable_serial(device_t dev, unsigned iobase)
+static void lpc47m15x_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c
index c221583..acd4b39 100644
--- a/src/superio/smsc/lpc47m15x/superio.c
+++ b/src/superio/smsc/lpc47m15x/superio.c
@@ -56,16 +56,17 @@
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
};
static void enable_dev(device_t dev)
{
- pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+ pnp_enable_devices(dev, &pnp_ops,
+ ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
static void lpc47m15x_pnp_set_resources(device_t dev)
@@ -86,13 +87,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
-
- if(dev->enabled) {
- pnp_set_enable(dev, 1);
- }
- else {
- pnp_set_enable(dev, 0);
- }
+ pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@@ -109,12 +104,10 @@
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
-
case LPC47M15X_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
-
case LPC47M15X_KBC:
pc_keyboard_init(&conf->keyboard);
break;
diff --git a/src/superio/smsc/lpc47n217/Makefile.inc b/src/superio/smsc/lpc47n217/Makefile.inc
index 1547ac4..947ea57 100644
--- a/src/superio/smsc/lpc47n217/Makefile.inc
+++ b/src/superio/smsc/lpc47n217/Makefile.inc
@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.c
+
diff --git a/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c b/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
index 34f2c45..ce79db8 100644
--- a/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
+++ b/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
@@ -24,17 +24,15 @@
#include <assert.h>
#include "lpc47n217.h"
-/** Enable access to the LPC47N217's configuration registers. */
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0x55, port);
}
-/** Disable access to the LPC47N217's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0xaa, port);
}
@@ -44,24 +42,21 @@
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Base I/O port for the logical device.
*/
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
{
- /* LPC47N217 requires base ports to be a multiple of 4 */
+ /* LPC47N217 requires base ports to be a multiple of 4. */
ASSERT(!(iobase & 0x3));
switch(dev & 0xFF) {
case LPC47N217_PP:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
break;
-
case LPC47N217_SP1:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
-
case LPC47N217_SP2:
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break;
-
default:
break;
}
@@ -81,37 +76,29 @@
*/
void lpc47n217_pnp_set_enable(device_t dev, int enable)
{
- uint8_t power_register = 0;
- uint8_t power_mask = 0;
- uint8_t current_power;
- uint8_t new_power;
+ u8 power_register = 0, power_mask = 0, current_power, new_power;
switch(dev & 0xFF) {
case LPC47N217_PP:
power_register = 0x01;
power_mask = 0x04;
break;
-
case LPC47N217_SP1:
power_register = 0x02;
power_mask = 0x08;
break;
-
case LPC47N217_SP2:
power_register = 0x02;
power_mask = 0x80;
break;
-
default:
return;
}
current_power = pnp_read_config(dev, power_register);
- new_power = current_power & ~power_mask; /* disable by default */
-
+ new_power = current_power & ~power_mask; /* Disable by default. */
if (enable)
- new_power |= power_mask; /* Enable */
-
+ new_power |= power_mask; /* Enable. */
pnp_write_config(dev, power_register, new_power);
}
@@ -122,7 +109,7 @@
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Processor I/O port address to assign to this serial device.
*/
-static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
+static void lpc47n217_enable_serial(device_t dev, u16 iobase)
{
/*
* NOTE: Cannot use pnp_set_XXX() here because they assume chip
diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c
index 95277cd..4cc5806 100644
--- a/src/superio/smsc/lpc47n217/superio.c
+++ b/src/superio/smsc/lpc47n217/superio.c
@@ -22,7 +22,6 @@
*/
/* RAM-based driver for SMSC LPC47N217 Super I/O chip. */
-/* Based on coreboot code for SMSC 47B397. */
#include <arch/io.h>
#include <device/device.h>
@@ -43,13 +42,11 @@
static void lpc47n217_pnp_enable_resources(device_t dev);
static void lpc47n217_pnp_enable(device_t dev);
static void lpc47n217_init(device_t dev);
-
static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
-static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
-static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
-static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
+static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase);
+static void lpc47n217_pnp_set_drq(device_t dev, u8 drq);
+static void lpc47n217_pnp_set_irq(device_t dev, u8 irq);
static void lpc47n217_pnp_set_enable(device_t dev, int enable);
-
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
@@ -67,9 +64,9 @@
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
+ { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }
};
/**
@@ -88,6 +85,9 @@
* Configure the specified Super I/O device with the resources (I/O space,
* etc.) that have been allocate for it.
*
+ * NOTE: Cannot use pnp_set_resources() here because it assumes chip
+ * support for logical devices, which the LPC47N217 doesn't have.
+ *
* @param dev Pointer to structure describing a Super I/O device.
*/
static void lpc47n217_pnp_set_resources(device_t dev)
@@ -95,46 +95,31 @@
struct resource *res;
pnp_enter_conf_state(dev);
-
- /* NOTE: Cannot use pnp_set_resources() here because it assumes chip
- * support for logical devices, which the LPC47N217 doesn't have
- */
- for(res = dev->resource_list; res; res = res->next)
+ for (res = dev->resource_list; res; res = res->next)
lpc47n217_pnp_set_resource(dev, res);
-
/* dump_pnp_device(dev); */
-
pnp_exit_conf_state(dev);
}
+/*
+ * NOTE: Cannot use pnp_enable_resources() here because it assumes chip
+ * support for logical devices, which the LPC47N217 doesn't have.
+ */
static void lpc47n217_pnp_enable_resources(device_t dev)
{
pnp_enter_conf_state(dev);
-
- /*
- * NOTE: Cannot use pnp_enable_resources() here because it assumes chip
- * support for logical devices, which the LPC47N217 doesn't have.
- */
lpc47n217_pnp_set_enable(dev, 1);
-
pnp_exit_conf_state(dev);
}
+/*
+ * NOTE: Cannot use pnp_set_enable() here because it assumes chip
+ * support for logical devices, which the LPC47N217 doesn't have.
+ */
static void lpc47n217_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
-
- /*
- * NOTE: Cannot use pnp_set_enable() here because it assumes chip
- * support for logical devices, which the LPC47N217 doesn't have.
- */
- if(dev->enabled) {
- lpc47n217_pnp_set_enable(dev, 1);
- }
- else {
- lpc47n217_pnp_set_enable(dev, 0);
- }
-
+ lpc47n217_pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@@ -159,7 +144,6 @@
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
-
case LPC47N217_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
@@ -171,27 +155,25 @@
{
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
printk(BIOS_ERR, "ERROR: %s %02x not allocated\n",
- dev_path(dev), resource->index);
+ dev_path(dev), resource->index);
return;
}
- /* Now store the resource */
+ /* Now store the resource. */
+
/*
* NOTE: Cannot use pnp_set_XXX() here because they assume chip
* support for logical devices, which the LPC47N217 doesn't have.
*/
if (resource->flags & IORESOURCE_IO) {
lpc47n217_pnp_set_iobase(dev, resource->base);
- }
- else if (resource->flags & IORESOURCE_DRQ) {
+ } else if (resource->flags & IORESOURCE_DRQ) {
lpc47n217_pnp_set_drq(dev, resource->base);
- }
- else if (resource->flags & IORESOURCE_IRQ) {
+ } else if (resource->flags & IORESOURCE_IRQ) {
lpc47n217_pnp_set_irq(dev, resource->base);
- }
- else {
+ } else {
printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n",
- dev_path(dev), resource->index);
+ dev_path(dev), resource->index);
return;
}
resource->flags |= IORESOURCE_STORED;
@@ -199,7 +181,7 @@
report_resource_stored(dev, resource, "");
}
-static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
{
ASSERT(!(iobase & 0x3));
@@ -207,30 +189,28 @@
case LPC47N217_PP:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
break;
-
case LPC47N217_SP1:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
-
case LPC47N217_SP2:
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break;
-
default:
BUG();
break;
}
}
-static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
+static void lpc47n217_pnp_set_drq(device_t dev, u8 drq)
{
- if (dev->path.pnp.device == LPC47N217_PP) {
- const uint8_t PP_DMA_MASK = 0x0F;
- const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
- uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
- uint8_t new_config;
+ const u8 PP_DMA_MASK = 0x0F;
+ const u8 PP_DMA_SELECTION_REGISTER = 0x26;
+ u8 current_config, new_config;
- ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range?? */
+ if (dev->path.pnp.device == LPC47N217_PP) {
+ current_config = pnp_read_config(dev,
+ PP_DMA_SELECTION_REGISTER);
+ ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range? */
new_config = (current_config & ~PP_DMA_MASK) | drq;
pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
} else {
@@ -238,36 +218,31 @@
}
}
-static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
+static void lpc47n217_pnp_set_irq(device_t dev, u8 irq)
{
- uint8_t irq_config_register = 0;
- uint8_t irq_config_mask = 0;
- uint8_t current_config;
- uint8_t new_config;
+ u8 irq_config_register = 0, irq_config_mask = 0;
+ u8 current_config, new_config;
switch(dev->path.pnp.device) {
case LPC47N217_PP:
irq_config_register = 0x27;
irq_config_mask = 0x0F;
break;
-
case LPC47N217_SP1:
irq_config_register = 0x28;
irq_config_mask = 0xF0;
irq <<= 4;
break;
-
case LPC47N217_SP2:
irq_config_register = 0x28;
irq_config_mask = 0x0F;
break;
-
default:
BUG();
return;
}
- ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range?? */
+ ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range? */
current_config = pnp_read_config(dev, irq_config_register);
new_config = (current_config & ~irq_config_mask) | irq;
@@ -276,54 +251,44 @@
static void lpc47n217_pnp_set_enable(device_t dev, int enable)
{
- uint8_t power_register = 0;
- uint8_t power_mask = 0;
- uint8_t current_power;
- uint8_t new_power;
+ u8 power_register = 0, power_mask = 0, current_power, new_power;
switch(dev->path.pnp.device) {
case LPC47N217_PP:
power_register = 0x01;
power_mask = 0x04;
break;
-
case LPC47N217_SP1:
power_register = 0x02;
power_mask = 0x08;
break;
-
case LPC47N217_SP2:
power_register = 0x02;
power_mask = 0x80;
break;
-
default:
BUG();
return;
}
current_power = pnp_read_config(dev, power_register);
- new_power = current_power & ~power_mask; /* disable by default */
-
+ new_power = current_power & ~power_mask; /* Disable by default. */
if (enable) {
- struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
+ struct resource* ioport_resource;
+ ioport_resource = find_resource(dev, PNP_IDX_IO0);
lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
-
- new_power |= power_mask; /* Enable */
-
+ new_power |= power_mask; /* Enable. */
} else {
lpc47n217_pnp_set_iobase(dev, 0);
}
pnp_write_config(dev, power_register, new_power);
}
-/** Enable access to the LPC47N217's configuration registers. */
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
-/** Disable access to the LPC47N217's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
@@ -339,30 +304,32 @@
*/
static void dump_pnp_device(device_t dev)
{
- int register_index;
+ int i;
print_debug("\n");
- for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
- uint8_t register_value;
+ for (i = 0; i <= LPC47N217_MAX_CONFIG_REGISTER; i++) {
+ u8 register_value;
- if ((register_index & 0x0f) == 0) {
- print_debug_hex8(register_index);
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
print_debug_char(':');
}
- /* Skip over 'register' that would cause exit from configuration mode */
- if (register_index == 0xaa)
+ /*
+ * Skip over 'register' that would cause exit from
+ * configuration mode.
+ */
+ if (i == 0xaa)
register_value = 0xaa;
else
- register_value = pnp_read_config(dev, register_index);
+ register_value = pnp_read_config(dev, i);
print_debug_char(' ');
print_debug_hex8(register_value);
- if ((register_index & 0x0f) == 0x0f) {
+ if ((i & 0x0f) == 0x0f)
print_debug("\n");
- }
}
- print_debug("\n");
+ print_debug("\n");
}
#endif
diff --git a/src/superio/smsc/lpc47n227/Makefile.inc b/src/superio/smsc/lpc47n227/Makefile.inc
index 22864f9..0159813 100644
--- a/src/superio/smsc/lpc47n227/Makefile.inc
+++ b/src/superio/smsc/lpc47n227/Makefile.inc
@@ -18,3 +18,4 @@
##
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N227) += superio.c
+
diff --git a/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c b/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c
index 318f0f3..32bd3e3 100644
--- a/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c
+++ b/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c
@@ -23,25 +23,15 @@
#include <arch/romcc_io.h>
#include "lpc47n227.h"
-/**
- * Enable access to the LPC47N227's configuration registers.
- *
- * @param dev High 8 bits = Super I/O port.
- */
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
{
- unsigned port = dev >> 8;
+ u16 port = dev >> 8;
outb(0x55, port);
}
-/**
- * Disable access to the LPC47N227's configuration registers.
- *
- * @param dev High 8 bits = Super I/O port.
- */
static void pnp_exit_conf_state(device_t dev)
{
- unsigned port = dev >> 8;
+ u16 port = dev >> 8;
outb(0xaa, port);
}
@@ -51,24 +41,21 @@
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Base I/O port for the logical device.
*/
-void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase)
+void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase)
{
- // LPC47N227 requires base ports to be a multiple of 4
+ /* LPC47N227 requires base ports to be a multiple of 4. */
ASSERT(!(iobase & 0x3));
switch (dev & 0xFF) {
case LPC47N227_PP:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
break;
-
case LPC47N227_SP1:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
-
case LPC47N227_SP2:
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break;
-
default:
break;
}
@@ -88,37 +75,29 @@
*/
void lpc47n227_pnp_set_enable(device_t dev, int enable)
{
- uint8_t power_register = 0;
- uint8_t power_mask = 0;
- uint8_t current_power;
- uint8_t new_power;
+ u8 power_register = 0, power_mask = 0, current_power, new_power;
switch (dev & 0xFF) {
case LPC47N227_PP:
power_register = 0x01;
power_mask = 0x04;
break;
-
case LPC47N227_SP1:
power_register = 0x02;
power_mask = 0x08;
break;
-
case LPC47N227_SP2:
power_register = 0x02;
power_mask = 0x80;
break;
-
default:
return;
}
current_power = pnp_read_config(dev, power_register);
- new_power = current_power & ~power_mask; // disable by default
-
+ new_power = current_power & ~power_mask; /* Disable by default. */
if (enable)
- new_power |= power_mask; // Enable
-
+ new_power |= power_mask; /* Enable. */
pnp_write_config(dev, power_register, new_power);
}
@@ -129,7 +108,7 @@
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Processor I/O port address to assign to this serial device.
*/
-static void lpc47n227_enable_serial(device_t dev, unsigned iobase)
+static void lpc47n227_enable_serial(device_t dev, u16 iobase)
{
/*
* NOTE: Cannot use pnp_set_XXX() here because they assume chip
diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c
index 5a994f7..2a4ead9 100644
--- a/src/superio/smsc/lpc47n227/superio.c
+++ b/src/superio/smsc/lpc47n227/superio.c
@@ -33,41 +33,38 @@
#include "chip.h"
#include "lpc47n227.h"
-// Forward declarations
+/* Forward declarations. */
static void enable_dev(device_t dev);
void lpc47n227_pnp_set_resources(device_t dev);
void lpc47n227_pnp_enable_resources(device_t dev);
void lpc47n227_pnp_enable(device_t dev);
static void lpc47n227_init(device_t dev);
-
static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource);
-void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase);
-void lpc47n227_pnp_set_drq(device_t dev, unsigned drq);
-void lpc47n227_pnp_set_irq(device_t dev, unsigned irq);
+void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase);
+void lpc47n227_pnp_set_drq(device_t dev, u8 drq);
+void lpc47n227_pnp_set_irq(device_t dev, u8 irq);
void lpc47n227_pnp_set_enable(device_t dev, int enable);
-
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
struct chip_operations superio_smsc_lpc47n227_ops = {
CHIP_NAME("SMSC LPC47N227 Super I/O")
- .enable_dev = enable_dev,
+ .enable_dev = enable_dev,
};
static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = lpc47n227_pnp_set_resources,
+ .read_resources = pnp_read_resources,
+ .set_resources = lpc47n227_pnp_set_resources,
.enable_resources = lpc47n227_pnp_enable_resources,
- .enable = lpc47n227_pnp_enable,
- .init = lpc47n227_init,
+ .enable = lpc47n227_pnp_enable,
+ .init = lpc47n227_init,
};
static struct pnp_info pnp_dev_info[] = {
- {&ops, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
- {&ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
- {&ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
- {&ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
- {0x7f8, 0x4},}
+ { &ops, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
};
/**
@@ -86,6 +83,9 @@
* Configure the specified Super I/O device with the resources (I/O space,
* etc.) that have been allocate for it.
*
+ * NOTE: Cannot use pnp_set_resources() here because it assumes chip
+ * support for logical devices, which the LPC47N227 doesn't have.
+ *
* @param dev Pointer to structure describing a Super I/O device.
*/
void lpc47n227_pnp_set_resources(device_t dev)
@@ -93,44 +93,30 @@
struct resource *res;
pnp_enter_conf_state(dev);
-
- /*
- * NOTE: Cannot use pnp_set_resources() here because it assumes chip
- * support for logical devices, which the LPC47N227 doesn't have.
- */
for (res = dev->resource_list; res; res = res->next)
lpc47n227_pnp_set_resource(dev, res);
-
pnp_exit_conf_state(dev);
}
+/*
+ * NOTE: Cannot use pnp_enable_resources() here because it assumes chip
+ * support for logical devices, which the LPC47N227 doesn't have.
+ */
void lpc47n227_pnp_enable_resources(device_t dev)
{
pnp_enter_conf_state(dev);
-
- /*
- * NOTE: Cannot use pnp_enable_resources() here because it assumes chip
- * support for logical devices, which the LPC47N227 doesn't have.
- */
lpc47n227_pnp_set_enable(dev, 1);
-
pnp_exit_conf_state(dev);
}
+/*
+ * NOTE: Cannot use pnp_set_enable() here because it assumes chip
+ * support for logical devices, which the LPC47N227 doesn't have.
+ */
void lpc47n227_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
-
- /*
- * NOTE: Cannot use pnp_set_enable() here because it assumes chip
- * support for logical devices, which the LPC47N227 doesn't have.
- */
- if (dev->enabled) {
- lpc47n227_pnp_set_enable(dev, 1);
- } else {
- lpc47n227_pnp_set_enable(dev, 0);
- }
-
+ lpc47n227_pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@@ -155,12 +141,10 @@
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
-
case LPC47N227_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
-
case LPC47N227_KBDC:
printk(BIOS_DEBUG, "LPC47N227: Initializing keyboard.\n");
pc_keyboard_init(&conf->keyboard);
@@ -172,11 +156,11 @@
{
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n",
- dev_path(dev), resource->index);
+ dev_path(dev), resource->index);
return;
}
- /* Now store the resource */
+ /* Now store the resource. */
/*
* NOTE: Cannot use pnp_set_XXX() here because they assume chip
* support for logical devices, which the LPC47N227 doesn't have.
@@ -189,7 +173,7 @@
lpc47n227_pnp_set_irq(dev, resource->base);
} else {
printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n",
- dev_path(dev), resource->index);
+ dev_path(dev), resource->index);
return;
}
resource->flags |= IORESOURCE_STORED;
@@ -197,7 +181,7 @@
report_resource_stored(dev, resource, "");
}
-void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase)
+void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase)
{
ASSERT(!(iobase & 0x3));
@@ -205,33 +189,29 @@
case LPC47N227_PP:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
break;
-
case LPC47N227_SP1:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
-
case LPC47N227_SP2:
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break;
-
case LPC47N227_KBDC:
break;
-
default:
BUG();
break;
}
}
-void lpc47n227_pnp_set_drq(device_t dev, unsigned drq)
+void lpc47n227_pnp_set_drq(device_t dev, u8 drq)
{
- if (dev->path.pnp.device == LPC47N227_PP) {
- const uint8_t PP_DMA_MASK = 0x0F;
- const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
- uint8_t current_config =
- pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
- uint8_t new_config;
+ const u8 PP_DMA_MASK = 0x0F;
+ const u8 PP_DMA_SELECTION_REGISTER = 0x26;
+ u8 current_config, new_config;
+ if (dev->path.pnp.device == LPC47N227_PP) {
+ current_config = pnp_read_config(dev,
+ PP_DMA_SELECTION_REGISTER);
ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range??
new_config = (current_config & ~PP_DMA_MASK) | drq;
pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
@@ -240,33 +220,27 @@
}
}
-void lpc47n227_pnp_set_irq(device_t dev, unsigned irq)
+void lpc47n227_pnp_set_irq(device_t dev, u8 irq)
{
- uint8_t irq_config_register = 0;
- uint8_t irq_config_mask = 0;
- uint8_t current_config;
- uint8_t new_config;
+ u8 irq_config_register = 0, irq_config_mask = 0;
+ u8 current_config, new_config;
switch (dev->path.pnp.device) {
case LPC47N227_PP:
irq_config_register = 0x27;
irq_config_mask = 0x0F;
break;
-
case LPC47N227_SP1:
irq_config_register = 0x28;
irq_config_mask = 0xF0;
irq <<= 4;
break;
-
case LPC47N227_SP2:
irq_config_register = 0x28;
irq_config_mask = 0x0F;
break;
-
case LPC47N227_KBDC:
break;
-
default:
BUG();
return;
@@ -279,58 +253,46 @@
void lpc47n227_pnp_set_enable(device_t dev, int enable)
{
- uint8_t power_register = 0;
- uint8_t power_mask = 0;
- uint8_t current_power;
- uint8_t new_power;
+ u8 power_register = 0, power_mask = 0, current_power, new_power;
switch (dev->path.pnp.device) {
case LPC47N227_PP:
power_register = 0x01;
power_mask = 0x04;
break;
-
case LPC47N227_SP1:
power_register = 0x02;
power_mask = 0x08;
break;
-
case LPC47N227_SP2:
power_register = 0x02;
power_mask = 0x80;
break;
-
case LPC47N227_KBDC:
break;
-
default:
BUG();
return;
}
current_power = pnp_read_config(dev, power_register);
- new_power = current_power & ~power_mask; // disable by default
-
+ new_power = current_power & ~power_mask; /* Disable by default. */
if (enable) {
- struct resource *ioport_resource =
- find_resource(dev, PNP_IDX_IO0);
+ struct resource *ioport_resource;
+ ioport_resource = find_resource(dev, PNP_IDX_IO0);
lpc47n227_pnp_set_iobase(dev, ioport_resource->base);
-
- new_power |= power_mask; // Enable
-
+ new_power |= power_mask; /* Enable. */
} else {
lpc47n227_pnp_set_iobase(dev, 0);
}
pnp_write_config(dev, power_register, new_power);
}
-/** Enable access to the LPC47N227's configuration registers. */
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
-/** Disable access to the LPC47N227's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
diff --git a/src/superio/smsc/sio10n268/Makefile.inc b/src/superio/smsc/sio10n268/Makefile.inc
index eeefa2d..fdde560 100644
--- a/src/superio/smsc/sio10n268/Makefile.inc
+++ b/src/superio/smsc/sio10n268/Makefile.inc
@@ -18,3 +18,4 @@
##
ramstage-$(CONFIG_SUPERIO_SMSC_SIO10N268) += sio10n268.c
+
diff --git a/src/superio/smsc/sio10n268/sio10n268.c b/src/superio/smsc/sio10n268/sio10n268.c
index 477ea96..66e3c87 100644
--- a/src/superio/smsc/sio10n268/sio10n268.c
+++ b/src/superio/smsc/sio10n268/sio10n268.c
@@ -27,13 +27,10 @@
static void init(device_t dev)
{
- struct superio_smsc_sio10n268_config *conf;
+ struct superio_smsc_sio10n268_config *conf = dev->chip_info;
- if (!dev->enabled) {
+ if (!dev->enabled)
return;
- }
-
- conf = dev->chip_info;
switch (dev->path.pnp.device) {
case SIO10N268_FDC: /* TODO. */
@@ -58,7 +55,7 @@
/* TODO: FDC, PP, AUX. */
static struct pnp_info pnp_dev_info[] = {
- { &ops, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+ { &ops, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, {0x07f8, 0}, {0x07f8, 4}, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/smsc/smscsuperio/Makefile.inc b/src/superio/smsc/smscsuperio/Makefile.inc
index 0dfc8d8..a0951f6 100644
--- a/src/superio/smsc/smscsuperio/Makefile.inc
+++ b/src/superio/smsc/smscsuperio/Makefile.inc
@@ -19,3 +19,4 @@
##
ramstage-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += superio.c
+
diff --git a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c b/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
index de2e891..ff47c4e 100644
--- a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
+++ b/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
@@ -33,9 +33,9 @@
* @param dev The device to use.
* @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8).
*/
-static inline void smscsuperio_enable_serial(device_t dev, uint16_t iobase)
+static void smscsuperio_enable_serial(device_t dev, u16 iobase)
{
- uint16_t port = dev >> 8;
+ u16 port = dev >> 8;
outb(0x55, port); /* Enter the configuration state. */
pnp_set_logical_device(dev);
diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c
index 99e9783..ff8b1b92 100644
--- a/src/superio/smsc/smscsuperio/superio.c
+++ b/src/superio/smsc/smscsuperio/superio.c
@@ -70,8 +70,8 @@
/* Static variables for the Super I/O device ID and revision. */
static int first_time = 1;
-static uint8_t superio_id = 0;
-static uint8_t superio_rev = 0;
+static u8 superio_id = 0;
+static u8 superio_rev = 0;
/**
* A list of all possible logical devices which may be supported by at least
@@ -117,7 +117,7 @@
* The result would be that the init code would be executed twice!
*/
static const struct logical_devices {
- uint8_t superio_id;
+ u8 superio_id;
int devs[MAX_LOGICAL_DEVICES];
} logical_device_table[] = {
/* Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB */
@@ -150,7 +150,7 @@
*
* @param dev The device to use.
*/
-static inline void smsc_pnp_enter_conf_state(device_t dev)
+static void smsc_pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
@@ -162,7 +162,7 @@
*
* @param dev The device to use.
*/
-static inline void smsc_pnp_exit_conf_state(device_t dev)
+static void smsc_pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
}
@@ -260,20 +260,19 @@
* TODO: FDC, PP, SP1, SP2, and KBC should work, the rest probably not (yet).
*/
static struct pnp_info pnp_dev_info[] = {
- { &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
- { &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
- { &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LD_RTC, },
- { &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 },
- { 0x7ff, 4 },},
+ { &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, LD_AUX, },
{ &ops, LD_XBUS, },
- { &ops, LD_HWM, PNP_IO0, { 0x7f0, 0 }, },
+ { &ops, LD_HWM, PNP_IO0, {0x07f0, 0}, },
{ &ops, LD_GAME, },
{ &ops, LD_PME, },
{ &ops, LD_MPU401, },
- { &ops, LD_RT, PNP_IO0, { 0x780, 0 }, },
+ { &ops, LD_RT, PNP_IO0, {0x0780, 0}, },
{ &ops, LD_ACPI, },
{ &ops, LD_SMB, },
};
@@ -291,7 +290,7 @@
{
int i, j, fn;
int tmp[MAX_LOGICAL_DEVICES];
- uint8_t test7;
+ u8 test7;
if (first_time) {
/* Read the device ID and revision of the Super I/O chip. */
@@ -302,21 +301,23 @@
/* TODO: Error handling? */
- printk(BIOS_INFO, "Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
- superio_id, superio_rev);
+ printk(BIOS_INFO, "Found SMSC Super I/O (ID=0x%02x, "
+ "rev=0x%02x)\n", superio_id, superio_rev);
first_time = 0;
- if(superio_id == LPC47M172) {
- /* Do not use the default logical device number
- * but instead the standard smsc registers set
- */
+ if (superio_id == LPC47M172) {
+ /*
+ * Do not use the default logical device number but
+ * instead the standard SMSC registers set.
+ */
- /* TEST7 configuration register (0x29)
- * bit 0 : LD_NUM (0 = new, 1 = std smsc)
- */
- test7 = pnp_read_config(dev, DEVICE_TEST7_REG);
- test7 |= 1;
- pnp_write_config(dev, DEVICE_TEST7_REG, test7);
+ /*
+ * TEST7 configuration register (0x29)
+ * Bit 0: LD_NUM (0 = new, 1 = std SMSC)
+ */
+ test7 = pnp_read_config(dev, DEVICE_TEST7_REG);
+ test7 |= (1 << 0);
+ pnp_write_config(dev, DEVICE_TEST7_REG, test7);
}
}
@@ -333,7 +334,8 @@
for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)
tmp[j] = pnp_dev_info[j].function;
- /* Replace the LD_FOO markers in pnp_dev_info[] with
+ /*
+ * Replace the LD_FOO markers in pnp_dev_info[] with
* the real logical device IDs of this Super I/O chip.
*/
for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) {