mb/google/brya: Add Kconfig for SLP_S0_GATE
Nissa doesn't have a SLP_S0_GATE signal, so we shouldn't generate the
related ACPI code. Therefore, move this behind a Kconfig which is
currently selected by the brya and brask baseboards.
BUG=b:197479026
TEST=Build brya0, check that there's no change to the generated dsdt.asl
Change-Id: I5a73c6794f6d3977cbff47aeff571154e41944cc
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 34d9cba..45e55bf 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -39,6 +39,7 @@
config BOARD_GOOGLE_BASEBOARD_BRYA
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
+ select HAVE_SLP_S0_GATE
select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
select SOC_INTEL_ALDERLAKE_PCH_P
select SYSTEM_TYPE_LAPTOP
@@ -47,6 +48,7 @@
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
+ select HAVE_SLP_S0_GATE
select MEMORY_SODIMM
select RT8168_GEN_ACPI_POWER_RESOURCE
select RT8168_GET_MAC_FROM_VPD
@@ -227,4 +229,7 @@
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
select HAVE_SPD_IN_CBFS
+config HAVE_SLP_S0_GATE
+ def_bool n
+
endif # BOARD_GOOGLE_BRYA_COMMON