soc/amd/morgana: Enable GPP clk req disabling
Enable GPP clk req disabling on morgana after reviewing against morgana
ppr #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/amd/birman/Makefile.inc b/src/mainboard/amd/birman/Makefile.inc
index b0466e7..e214337 100644
--- a/src/mainboard/amd/birman/Makefile.inc
+++ b/src/mainboard/amd/birman/Makefile.inc
@@ -8,6 +8,7 @@
ramstage-y += chromeos.c
ramstage-y += gpio.c
+ramstage-y += port_descriptors.c
ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin),)
APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin
diff --git a/src/mainboard/amd/mayan/Makefile.inc b/src/mainboard/amd/mayan/Makefile.inc
index 20d6f4b..1fbeccd 100644
--- a/src/mainboard/amd/mayan/Makefile.inc
+++ b/src/mainboard/amd/mayan/Makefile.inc
@@ -8,6 +8,7 @@
ramstage-y += chromeos.c
ramstage-y += gpio.c
+ramstage-y += port_descriptors.c
ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin),)
APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin
diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig
index 6e6033b..ec0572c 100644
--- a/src/soc/amd/morgana/Kconfig
+++ b/src/soc/amd/morgana/Kconfig
@@ -61,9 +61,10 @@
select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_MCAX
select SOC_AMD_COMMON_BLOCK_NONCAR
- select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct
- select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct
- select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct
+ select SOC_AMD_COMMON_BLOCK_PCI
+ select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+ select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
+ select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct
diff --git a/src/soc/amd/morgana/chip.h b/src/soc/amd/morgana/chip.h
index 8875c5e..cceea10 100644
--- a/src/soc/amd/morgana/chip.h
+++ b/src/soc/amd/morgana/chip.h
@@ -7,6 +7,7 @@
#include <amdblocks/chip.h>
#include <amdblocks/i2c.h>
+#include <amdblocks/pci_clk_req.h>
#include <gpio.h>
#include <soc/i2c.h>
#include <soc/southbridge.h>
@@ -92,11 +93,7 @@
/* The array index is the general purpose PCIe clock output number. Values in here
aren't the values written to the register to have the default to be always on. */
- enum {
- GPP_CLK_ON, /* GPP clock always on; default */
- GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
- GPP_CLK_OFF, /* GPP clk off */
- } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
+ enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
/* performance policy for the PCIe links: power consumption vs. link speed */
enum {
diff --git a/src/soc/amd/morgana/fch.c b/src/soc/amd/morgana/fch.c
index 08fbe98..b740f47 100644
--- a/src/soc/amd/morgana/fch.c
+++ b/src/soc/amd/morgana/fch.c
@@ -1,11 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* TODO: Update for Morgana */
-
#include <amdblocks/acpi.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/gpio.h>
+#include <amdblocks/pci_clk_req.h>
#include <amdblocks/smi.h>
#include <assert.h>
#include <bootstate.h>
@@ -125,7 +124,7 @@
/* configure the general purpose PCIe clock outputs according to the devicetree settings */
static void gpp_clk_setup(void)
{
- const struct soc_amd_morgana_config *cfg = config_of_soc();
+ struct soc_amd_morgana_config *cfg = config_of_soc();
/* look-up table to be able to iterate over the PCIe clock output settings */
const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
@@ -140,6 +139,8 @@
uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
+ pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
+ ARRAY_SIZE(cfg->gpp_clk_config));
for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
/*
diff --git a/src/soc/amd/morgana/include/soc/southbridge.h b/src/soc/amd/morgana/include/soc/southbridge.h
index 216bf42..b64d38a 100644
--- a/src/soc/amd/morgana/include/soc/southbridge.h
+++ b/src/soc/amd/morgana/include/soc/southbridge.h
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* TODO: Update for Morgana */
-
#ifndef AMD_MORGANA_SOUTHBRIDGE_H
#define AMD_MORGANA_SOUTHBRIDGE_H
@@ -13,7 +11,7 @@
#define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25)
#define PWR_RESET_CFG 0x10
-#define TOGGLE_ALL_PWR_GOOD (1 << 1)
+#define TOGGLE_ALL_PWR_GOOD BIT(1)
#define PM_SERIRQ_CONF 0x54
#define PM_SERIRQ_NUM_BITS_17 0x0000
#define PM_SERIRQ_NUM_BITS_18 0x0004
@@ -61,7 +59,6 @@
#define PM_ACPI_SW_S5PWRMUX BIT(16)
#define PM_ACPI_EN_SHUTDOWN_MSG BIT(17)
#define PM_ACPI_EN_SYNC_FLOOD BIT(18)
-#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19)
#define PM_ACPI_EN_DF_INTRWAKE BIT(20)
#define PM_ACPI_MASK_USB_S5_RST BIT(21)
#define PM_ACPI_USE_RSMU_RESET BIT(22)
@@ -96,7 +93,7 @@
#define GPP_CLK5_REQ_SHIFT 10
#define GPP_CLK6_REQ_SHIFT 12
#define GPP_CLK_OUTPUT_COUNT 7
-#define GPP_CLK_OUTPUT_AVAILABLE 4
+#define GPP_CLK_OUTPUT_AVAILABLE 7
#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))