soc/amd/common/cpu/tsc: factor out family-specific get_pstate_core_freq
Factor out the get_pstate_core_freq function from the SoC's acpi.c files
to both avoid duplication and to also be able to use the same function
in the TSC frequency calculation in a follow-up patch. The family 17h
and 19h SoCs use the same frequency encoding in the P state MSRs while
the family 1Ah SoCs use a different encoding. The family 15h and 16h
SoCs use another encoding, but since this isn't implemented in
Stoneyridge's acpi.c, this will be added in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8619822c2c61e06ae5db86896d5323c9b105b25b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 96a287c..bd2becc 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -44,6 +44,7 @@
select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_APOB_HASH
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
+ select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index c98ec68..8e90d44 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -16,11 +16,9 @@
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/amd/cpuid.h>
-#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h>
#include <soc/acpi.h>
#include <soc/iomap.h>
-#include <soc/msr.h>
#include <types.h>
#include "chip.h"
@@ -98,43 +96,6 @@
fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
}
-uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
-{
- uint32_t core_freq, core_freq_mul, core_freq_div;
- bool valid_freq_divisor;
-
- /* Core frequency multiplier */
- core_freq_mul = pstate_reg.cpu_fid_0_7;
-
- /* Core frequency divisor ID */
- core_freq_div = pstate_reg.cpu_dfs_id;
-
- if (core_freq_div == 0) {
- return 0;
- } else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
- && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
- /* Allow 1/8 integer steps for this range */
- valid_freq_divisor = true;
- } else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
- && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
- /* Only allow 1/4 integer steps for this range */
- valid_freq_divisor = true;
- } else {
- valid_freq_divisor = false;
- }
-
- if (valid_freq_divisor) {
- /* 25 * core_freq_mul / (core_freq_div / 8) */
- core_freq =
- ((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
- } else {
- printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
- core_freq_div);
- core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
- }
- return core_freq;
-}
-
const acpi_cstate_t cstate_cfg_table[] = {
[0] = {
.ctype = 1,
diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h
index 173ee09..7acf321 100644
--- a/src/soc/amd/phoenix/include/soc/msr.h
+++ b/src/soc/amd/phoenix/include/soc/msr.h
@@ -20,11 +20,6 @@
uint64_t raw;
};
-#define PSTATE_DEF_FREQ_DIV_MIN 0x8
-#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A
-#define PSTATE_DEF_FREQ_DIV_MAX 0x3E
-#define PSTATE_DEF_CORE_FREQ_BASE 25
-
#define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24
#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16