nb/intel/x4x: Use new fixed BAR accessors
Some cases break reproducibility if refactored, and are left as-is.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I163995c0b107860449c2f36ad63e4e4ca52decb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51878
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 6045f3b..854e143 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -167,7 +167,7 @@
for (count = 0; count < WT_PATTERN_SIZE; count++) {
for (count1 = 0; count1 < WT_PATTERN_SIZE; count1++) {
if ((count1 % 16) == 0)
- MCHBAR32(0xf90) = 1;
+ mchbar_write32(0xf90, 1);
const u32 pattern = write_training_schedule[count1];
write32((u32 *)address + 8 * count1, pattern);
write32((u32 *)address + 8 * count1 + 4, pattern);
@@ -620,7 +620,7 @@
write32((u32 *)address + 4, 0x12341234);
udelay(5);
FOR_EACH_BYTELANE(lane) {
- u8 dq_high = (MCHBAR8(0x561 + 0x400 * channel
+ u8 dq_high = (mchbar_read8(0x561 + 0x400 * channel
+ (lane * 4)) >> 7) & 1;
high_found[lane] += dq_high;
}
@@ -639,7 +639,7 @@
FOR_EACH_BYTELANE(lane)
dqsset(channel, lane, &dqs_setting[lane]);
- saved_24d = MCHBAR8(0x24d + 0x400 * channel);
+ saved_24d = mchbar_read8(0x24d + 0x400 * channel);
/* Loop 0: Find DQ sample low, by decreasing */
while (bytelane_ok != 0xff) {
@@ -715,7 +715,7 @@
s->dqs_settings[channel][lane] = dqs_setting[lane];
}
- MCHBAR8(0x24d + 0x400 * channel) = saved_24d;
+ mchbar_write8(0x24d + 0x400 * channel, saved_24d);
return CB_SUCCESS;
}
@@ -762,11 +762,9 @@
printk(BIOS_DEBUG, "\tCH%d\n", ch);
config = chanconfig_lut[s->dimm_config[ch]];
- MCHBAR8(0x5d8 + 0x400 * ch) = MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e;
- MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) &
- ~0x3fff) | 0x3fff;
- MCHBAR8(0x265 + 0x400 * ch) =
- MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;
+ mchbar_clrbits8(0x5d8 + 0x400 * ch, 0x0e);
+ mchbar_clrsetbits16(0x5c4 + 0x400 * ch, 0x3fff, 0x3fff);
+ mchbar_clrbits8(0x265 + 0x400 * ch, 0x1f);
/* find the first populated rank */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0)
break;
@@ -776,41 +774,33 @@
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank1)
set_rank_write_level(s, ch, config, rank1, rank0, 1);
- MCHBAR8(0x298 + 2 + 0x400 * ch) =
- (MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f)
- | odt_force[config][rank0];
- MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) | 0x4e;
- MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04;
- MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00014000;
+ mchbar_clrsetbits8(0x298 + 2 + 0x400 * ch, 0x0f, odt_force[config][rank0]);
+ mchbar_clrsetbits8(0x271 + 0x400 * ch, 0x7e, 0x4e);
+ mchbar_setbits8(0x5d9 + 0x400 * ch, 1 << 2);
+ mchbar_clrsetbits32(0x1a0, 0x07ffffff, 0x00014000);
if (increment_to_dqs_edge(s, ch, rank0))
die("Write Leveling failed!");
- MCHBAR8(0x298 + 2 + 0x400 * ch) =
- MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f;
- MCHBAR8(0x271 + 0x400 * ch) =
- (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e)
- | 0x0e;
- MCHBAR8(0x5d9 + 0x400 * ch) =
- (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04);
- MCHBAR32(0x1a0) = (MCHBAR32(0x1a0)
- & ~0x07ffffff) | 0x00555801;
+ mchbar_clrbits8(0x298 + 2 + 0x400 * ch, 0x0f);
+ mchbar_clrsetbits8(0x271 + 0x400 * ch, 0x7e, 0x0e);
+ mchbar_clrbits8(0x5d9 + 0x400 * ch, 1 << 2);
+ mchbar_clrsetbits32(0x1a0, 0x07ffffff, 0x00555801);
/* Disable WL on the trained rank */
set_rank_write_level(s, ch, config, rank0, rank0, 0);
send_jedec_cmd(s, rank0, ch, NORMALOP_CMD, 1 << 12);
- MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e) | 0x0e;
- MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch)
- & ~0x3fff) | 0x1807;
- MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;
+ mchbar_setbits8(0x5d8 + 0x400 * ch, 0x0e);
+ mchbar_clrsetbits16(0x5c4 + 0x400 * ch, 0x3fff, 0x1807);
+ mchbar_clrbits8(0x265 + 0x400 * ch, 0x1f);
/* Disable write level mode for all ranks */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0)
set_rank_write_level(s, ch, config, rank0, rank0, 0);
}
- MCHBAR8(0x5dc) = (MCHBAR8(0x5dc) & ~0x80) | 0x80;
+ mchbar_setbits8(0x5dc, 1 << 7);
/* Increment DQ (rx) dll setting by a standard amount past DQS,
This is further trained in write training. */
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index e6083d9..de261bd 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -59,59 +59,59 @@
u32 reg32;
/* VC0: TC0 only */
- EPBAR8(EPVC0RCTL) = 1;
- EPBAR8(EPPVCCAP1) = 1;
+ epbar_write8(EPVC0RCTL, 1);
+ epbar_write8(EPPVCCAP1, 1);
- switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {
+ switch (mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {
case 0x0:
/* FSB 1066 */
- EPBAR32(EPVC1ITC) = 0x0001a6db;
+ epbar_write32(EPVC1ITC, 0x0001a6db);
break;
case 0x2:
/* FSB 800 */
- EPBAR32(EPVC1ITC) = 0x00014514;
+ epbar_write32(EPVC1ITC, 0x00014514);
break;
default:
case 0x4:
/* FSB 1333 */
- EPBAR32(EPVC1ITC) = 0x00022861;
+ epbar_write32(EPVC1ITC, 0x00022861);
break;
}
- EPBAR32(EPVC1MTS) = 0x0a0a0a0a;
- EPBAR8(EPPVCCTL) = (EPBAR8(EPPVCCTL) & ~0xe) | 2;
- EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~0x7f0000) | 0x0a0000;
- MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7;
+ epbar_write32(EPVC1MTS, 0x0a0a0a0a);
+ epbar_clrsetbits8(EPPVCCTL, 7 << 1, 1 << 1);
+ epbar_clrsetbits32(EPVC1RCAP, 0x7f << 16, 0x0a << 16);
+ mchbar_setbits8(0x3c, 7);
/* VC1: ID1, TC7 */
- reg32 = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24);
+ reg32 = (epbar_read32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24);
reg32 = (reg32 & ~0xfe) | (1 << 7);
- EPBAR32(EPVC1RCTL) = reg32;
+ epbar_write32(EPVC1RCTL, reg32);
/* Init VC1 port arbitration table */
- EPBAR32(EP_PORTARB(0)) = 0x001000001;
- EPBAR32(EP_PORTARB(1)) = 0x000040000;
- EPBAR32(EP_PORTARB(2)) = 0x000001000;
- EPBAR32(EP_PORTARB(3)) = 0x000000040;
- EPBAR32(EP_PORTARB(4)) = 0x001000001;
- EPBAR32(EP_PORTARB(5)) = 0x000040000;
- EPBAR32(EP_PORTARB(6)) = 0x000001000;
- EPBAR32(EP_PORTARB(7)) = 0x000000040;
+ epbar_write32(EP_PORTARB(0), 0x001000001);
+ epbar_write32(EP_PORTARB(1), 0x000040000);
+ epbar_write32(EP_PORTARB(2), 0x000001000);
+ epbar_write32(EP_PORTARB(3), 0x000000040);
+ epbar_write32(EP_PORTARB(4), 0x001000001);
+ epbar_write32(EP_PORTARB(5), 0x000040000);
+ epbar_write32(EP_PORTARB(6), 0x000001000);
+ epbar_write32(EP_PORTARB(7), 0x000000040);
/* Load table */
- reg32 = EPBAR32(EPVC1RCTL) | (1 << 16);
- EPBAR32(EPVC1RCTL) = reg32;
+ reg32 = epbar_read32(EPVC1RCTL) | (1 << 16);
+ epbar_write32(EPVC1RCTL, reg32);
asm("nop");
- EPBAR32(EPVC1RCTL) = reg32;
+ epbar_write32(EPVC1RCTL, reg32);
/* Wait for table load */
- while ((EPBAR8(EPVC1RSTS) & (1 << 0)) != 0)
+ while ((epbar_read8(EPVC1RSTS) & (1 << 0)) != 0)
;
/* VC1: enable */
- EPBAR32(EPVC1RCTL) |= 1 << 31;
+ epbar_setbits32(EPVC1RCTL, 1 << 31);
/* Wait for VC1 */
- while ((EPBAR8(EPVC1RSTS) & (1 << 1)) != 0)
+ while ((epbar_read8(EPVC1RSTS) & (1 << 1)) != 0)
;
printk(BIOS_DEBUG, "Done Egress Port\n");
@@ -124,22 +124,22 @@
/* Assume IGD present */
/* Clear error status */
- DMIBAR32(DMIUESTS) = 0xffffffff;
- DMIBAR32(DMICESTS) = 0xffffffff;
+ dmibar_write32(DMIUESTS, 0xffffffff);
+ dmibar_write32(DMICESTS, 0xffffffff);
/* VC0: TC0 only */
- DMIBAR8(DMIVC0RCTL) = 1;
- DMIBAR8(DMIPVCCAP1) = 1;
+ dmibar_write8(DMIVC0RCTL, 1);
+ dmibar_write8(DMIPVCCAP1, 1);
/* VC1: ID1, TC7 */
- reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
+ reg32 = (dmibar_read32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
reg32 = (reg32 & ~0xff) | 1 << 7;
/* VC1: enable */
reg32 |= 1 << 31;
reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17);
- DMIBAR32(DMIVC1RCTL) = reg32;
+ dmibar_write32(DMIVC1RCTL, reg32);
/* Set up VCs in southbridge RCBA */
RCBA8(0x3022) &= ~1;
@@ -202,17 +202,17 @@
/* Set up VC1 max time */
RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000;
- while ((DMIBAR32(DMIVC1RSTS) & VC1NP) != 0)
+ while ((dmibar_read32(DMIVC1RSTS) & VC1NP) != 0)
;
printk(BIOS_DEBUG, "Done DMI setup\n");
/* ASPM on DMI */
- DMIBAR32(0x200) &= ~(0x3 << 26);
- DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101;
- DMIBAR32(DMILCTL) &= ~0x3;
- DMIBAR32(DMILCTL) |= 0x3;
+ dmibar_clrbits32(0x200, 3 << 26);
+ dmibar_clrsetbits16(0x210, 0xff7, 0x101);
+ dmibar_clrbits32(DMILCTL, 3);
+ dmibar_setbits32(DMILCTL, 3);
/* FIXME: Do we need to read RCBA16(DMILCTL)? Probably not. */
- DMIBAR16(DMILCTL);
+ dmibar_read16(DMILCTL);
}
void x4x_late_init(void)
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 5f937cf..460916b 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -412,7 +412,7 @@
static void find_fsb_speed(struct sysinfo *s)
{
- switch ((MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) {
+ switch ((mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) {
case 0x0:
s->max_fsb = FSB_CLOCK_1066MHz;
break;
@@ -532,7 +532,7 @@
u32 pmsts;
if (boot_path >= 1) {
- pmsts = MCHBAR32(PMSTS_MCHBAR);
+ pmsts = mchbar_read32(PMSTS_MCHBAR);
if (!(pmsts & 1))
printk(BIOS_DEBUG, "Channel 0 possibly not in self refresh\n");
if (!(pmsts & 2))
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 6863ef8..e5e17d1 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -37,7 +37,7 @@
{
u8 i, j;
u32 reg32;
- MCHBAR16_OR(0xc1c, (1 << 15));
+ mchbar_setbits16(0xc1c, 1 << 15);
static const u32 clkxtab[6][3][13] = {
/* MEMCLK 400 N/A */
@@ -100,56 +100,56 @@
i = (u8)s->selected_timings.mem_clk;
j = (u8)s->selected_timings.fsb_clk;
- MCHBAR32(0xc04) = clkxtab[i][j][0];
+ mchbar_write32(0xc04, clkxtab[i][j][0]);
reg32 = clkxtab[i][j][1];
if (s->spd_type == DDR3 && s->max_fsb == FSB_CLOCK_1333MHz
&& s->selected_timings.mem_clk == MEM_CLOCK_800MHz) {
reg32 &= ~(0xff << 24);
reg32 |= 0x3d << 24;
}
- MCHBAR32(0xc50) = reg32;
- MCHBAR32(0xc54) = clkxtab[i][j][2];
- MCHBAR8_OR(0xc08, (1 << 7));
- MCHBAR32(0x6d8) = clkxtab[i][j][3];
- MCHBAR32(0x6e0) = clkxtab[i][j][3];
- MCHBAR32(0x6dc) = clkxtab[i][j][4];
- MCHBAR32(0x6e4) = clkxtab[i][j][4];
- MCHBAR32(0x6e8) = clkxtab[i][j][5];
- MCHBAR32(0x6f0) = clkxtab[i][j][5];
- MCHBAR32(0x6ec) = clkxtab[i][j][6];
- MCHBAR32(0x6f4) = clkxtab[i][j][6];
- MCHBAR32(0x6f8) = clkxtab[i][j][7];
- MCHBAR32(0x6fc) = clkxtab[i][j][8];
- MCHBAR32(0x708) = clkxtab[i][j][11];
- MCHBAR32(0x70c) = clkxtab[i][j][12];
+ mchbar_write32(0xc50, reg32);
+ mchbar_write32(0xc54, clkxtab[i][j][2]);
+ mchbar_setbits8(0xc08, 1 << 7);
+ mchbar_write32(0x6d8, clkxtab[i][j][3]);
+ mchbar_write32(0x6e0, clkxtab[i][j][3]);
+ mchbar_write32(0x6dc, clkxtab[i][j][4]);
+ mchbar_write32(0x6e4, clkxtab[i][j][4]);
+ mchbar_write32(0x6e8, clkxtab[i][j][5]);
+ mchbar_write32(0x6f0, clkxtab[i][j][5]);
+ mchbar_write32(0x6ec, clkxtab[i][j][6]);
+ mchbar_write32(0x6f4, clkxtab[i][j][6]);
+ mchbar_write32(0x6f8, clkxtab[i][j][7]);
+ mchbar_write32(0x6fc, clkxtab[i][j][8]);
+ mchbar_write32(0x708, clkxtab[i][j][11]);
+ mchbar_write32(0x70c, clkxtab[i][j][12]);
}
static void setioclk_dram(struct sysinfo *s)
{
- MCHBAR32(0x1bc) = 0x08060402;
- MCHBAR16_OR(0x1c0, 0x200);
- MCHBAR16_OR(0x1c0, 0x100);
- MCHBAR16_OR(0x1c0, 0x20);
- MCHBAR16_AND(0x1c0, ~1);
+ mchbar_write32(0x1bc, 0x08060402);
+ mchbar_setbits16(0x1c0, 1 << 9);
+ mchbar_setbits16(0x1c0, 1 << 8);
+ mchbar_setbits16(0x1c0, 1 << 5);
+ mchbar_clrbits16(0x1c0, 1 << 0);
switch (s->selected_timings.mem_clk) {
default:
case MEM_CLOCK_800MHz:
case MEM_CLOCK_1066MHz:
- MCHBAR8_AND_OR(0x5d9, ~0x2, 0x2);
- MCHBAR8_AND_OR(0x9d9, ~0x2, 0x2);
- MCHBAR8_AND_OR(0x189, ~0xf0, 0xc0);
- MCHBAR8_AND_OR(0x189, ~0xf0, 0xe0);
- MCHBAR8_AND_OR(0x189, ~0xf0, 0xa0);
+ mchbar_setbits8(0x5d9, 1 << 1);
+ mchbar_setbits8(0x9d9, 1 << 1);
+ mchbar_clrsetbits8(0x189, 0xf0, 0xc0);
+ mchbar_clrsetbits8(0x189, 0xf0, 0xe0);
+ mchbar_clrsetbits8(0x189, 0xf0, 0xa0);
break;
case MEM_CLOCK_667MHz:
case MEM_CLOCK_1333MHz:
- MCHBAR8_AND(0x5d9, ~0x2);
- MCHBAR8_AND(0x9d9, ~0x2);
- MCHBAR8_AND_OR(0x189, ~0xf0, 0x40);
+ mchbar_clrbits8(0x5d9, 1 << 1);
+ mchbar_clrbits8(0x9d9, 1 << 1);
+ mchbar_clrsetbits8(0x189, 0xf0, 0x40);
break;
}
- MCHBAR32_OR(0x594, 1 << 31);
- MCHBAR32_OR(0x994, 1 << 31);
+ mchbar_setbits32(0x594, 1 << 31);
+ mchbar_setbits32(0x994, 1 << 31);
}
static void launch_dram(struct sysinfo *s)
@@ -234,27 +234,27 @@
}
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
- MCHBAR32(0x400*i + 0x220) = launch1;
- MCHBAR32(0x400*i + 0x224) = launch2;
- MCHBAR32(0x400*i + 0x21c) = 0;
- MCHBAR32_OR(0x400*i + 0x248, 1 << 23);
+ mchbar_write32(0x400 * i + 0x220, launch1);
+ mchbar_write32(0x400 * i + 0x224, launch2);
+ mchbar_write32(0x400 * i + 0x21c, 0);
+ mchbar_setbits32(0x400 * i + 0x248, 1 << 23);
}
- MCHBAR32_AND_OR(0x2c0, ~0x58000000, 0x48000000);
- MCHBAR32_OR(0x2c0, 0x1e0);
- MCHBAR32_AND_OR(0x2c4, ~0xf, 0xc);
+ mchbar_clrsetbits32(0x2c0, 0x58 << 24, 0x48 << 24);
+ mchbar_setbits32(0x2c0, 0xf << 5);
+ mchbar_clrsetbits32(0x2c4, 0xf, 0xc);
if (s->spd_type == DDR3)
- MCHBAR32_OR(0x2c4, 0x100);
+ mchbar_setbits32(0x2c4, 1 << 8);
}
static void write_txdll_tap_pi(u8 ch, u16 reg, u8 tap, u8 pi)
{
- MCHBAR8_AND_OR(0x400 * ch + reg, ~0x7f, pi << 4 | tap);
+ mchbar_clrsetbits8(0x400 * ch + reg, 0x7f, pi << 4 | tap);
}
static void clkset0(u8 ch, const struct dll_setting *setting)
{
- MCHBAR16_AND_OR(0x400*ch + 0x5a0, ~0xc440,
+ mchbar_clrsetbits16(0x400 * ch + 0x5a0, 0xc440,
(setting->clk_delay << 14) |
(setting->db_sel << 6) |
(setting->db_en << 10));
@@ -263,7 +263,7 @@
static void clkset1(u8 ch, const struct dll_setting *setting)
{
- MCHBAR32_AND_OR(0x400*ch + 0x5a0, ~0x30880,
+ mchbar_clrsetbits32(0x400 * ch + 0x5a0, 0x30880,
(setting->clk_delay << 16) |
(setting->db_sel << 7) |
(setting->db_en << 11));
@@ -272,7 +272,7 @@
static void ctrlset0(u8 ch, const struct dll_setting *setting)
{
- MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x3300000,
+ mchbar_clrsetbits32(0x400 * ch + 0x59c, 0x3300000,
(setting->clk_delay << 24) |
(setting->db_sel << 20) |
(setting->db_en << 21));
@@ -281,7 +281,7 @@
static void ctrlset1(u8 ch, const struct dll_setting *setting)
{
- MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x18c00000,
+ mchbar_clrsetbits32(0x400 * ch + 0x59c, 0x18c00000,
(setting->clk_delay << 27) |
(setting->db_sel << 22) |
(setting->db_en << 23));
@@ -295,7 +295,7 @@
* the reset default value is zero and it is only programmed once.
* As it makes no difference, we can safely use the correct mask.
*/
- MCHBAR32_AND_OR(0x400*ch + 0x598, ~0xf000,
+ mchbar_clrsetbits32(0x400 * ch + 0x598, 0xf000,
(setting->clk_delay << 14) |
(setting->db_sel << 12) |
(setting->db_en << 13));
@@ -309,7 +309,7 @@
* the reset default value is zero and it is only programmed once.
* As it makes no difference, we can safely use the correct mask.
*/
- MCHBAR32_AND_OR(0x400*ch + 0x598, ~0xf00,
+ mchbar_clrsetbits32(0x400 * ch + 0x598, 0xf00,
(setting->clk_delay << 10) |
(setting->db_sel << 8) |
(setting->db_en << 9));
@@ -318,8 +318,8 @@
static void cmdset(u8 ch, const struct dll_setting *setting)
{
- MCHBAR8_AND_OR(0x400*ch + 0x598, ~0x30, setting->clk_delay << 4);
- MCHBAR8_AND_OR(0x400*ch + 0x594, ~0x60,
+ mchbar_clrsetbits8(0x400 * ch + 0x598, 0x30, setting->clk_delay << 4);
+ mchbar_clrsetbits8(0x400 * ch + 0x594, 0x60,
(setting->db_sel << 5) |
(setting->db_en << 6));
write_txdll_tap_pi(ch, 0x580, setting->tap, setting->pi);
@@ -333,17 +333,16 @@
{
int rank;
- MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4 + 1)),
+ mchbar_clrsetbits32(0x400 * ch + 0x5fc, 1 << (lane * 4 + 1),
setting->coarse << (lane * 4 + 1));
for (rank = 0; rank < 4; rank++) {
- MCHBAR32_AND_OR(0x400 * ch + 0x5b4 + rank * 4, ~(0x201 << lane),
+ mchbar_clrsetbits32(0x400 * ch + 0x5b4 + rank * 4, 0x201 << lane,
(setting->db_en << (9 + lane)) |
(setting->db_sel << lane));
- MCHBAR32_AND_OR(0x400*ch + 0x5c8 + rank * 4,
- ~(0x3 << (16 + lane * 2)),
- setting->clk_delay << (16+lane * 2));
+ mchbar_clrsetbits32(0x400 * ch + 0x5c8 + rank * 4, 0x3 << (16 + lane * 2),
+ setting->clk_delay << (16 + lane * 2));
write_txdll_tap_pi(ch, 0x520 + lane * 4 + rank, setting->tap, setting->pi);
}
@@ -352,16 +351,16 @@
void dqset(u8 ch, u8 lane, const struct dll_setting *setting)
{
int rank;
- MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4)),
+ mchbar_clrsetbits32(0x400 * ch + 0x5fc, 1 << (lane * 4),
setting->coarse << (lane * 4));
for (rank = 0; rank < 4; rank++) {
- MCHBAR32_AND_OR(0x400 * ch + 0x5a4 + rank * 4, ~(0x201 << lane),
+ mchbar_clrsetbits32(0x400 * ch + 0x5a4 + rank * 4, 0x201 << lane,
(setting->db_en << (9 + lane)) |
(setting->db_sel << lane));
- MCHBAR32_AND_OR(0x400 * ch + 0x5c8 + rank * 4,
- ~(0x3 << (lane * 2)), setting->clk_delay << (2 * lane));
+ mchbar_clrsetbits32(0x400 * ch + 0x5c8 + rank * 4, 0x3 << (lane * 2),
+ setting->clk_delay << (2 * lane));
write_txdll_tap_pi(ch, 0x500 + lane * 4 + rank, setting->tap, setting->pi);
}
@@ -369,19 +368,19 @@
void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting)
{
- u16 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4);
- u16 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4);
+ u16 saved_tap = mchbar_read16(0x540 + 0x400 * channel + lane * 4);
+ u16 saved_pi = mchbar_read16(0x542 + 0x400 * channel + lane * 4);
printk(RAM_SPEW, "RT DQS: ch%d, r%d, L%d: %d.%d\n", channel, rank, lane,
dqs_setting->tap,
dqs_setting->pi);
saved_tap &= ~(0xf << (rank * 4));
saved_tap |= dqs_setting->tap << (rank * 4);
- MCHBAR16(0x540 + 0x400 * channel + lane * 4) = saved_tap;
+ mchbar_write16(0x540 + 0x400 * channel + lane * 4, saved_tap);
saved_pi &= ~(0x7 << (rank * 3));
saved_pi |= dqs_setting->pi << (rank * 3);
- MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi;
+ mchbar_write16(0x542 + 0x400 * channel + lane * 4, saved_pi);
}
static void program_timings(struct sysinfo *s)
@@ -502,18 +501,17 @@
}
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
- MCHBAR8_OR(0x400*i + 0x26f, 0x3);
- MCHBAR8_AND_OR(0x400*i + 0x228, ~0x7, 0x2);
+ mchbar_setbits8(0x400 * i + 0x26f, 0x3);
+ mchbar_clrsetbits8(0x400 * i + 0x228, 0x7, 0x2);
/* tWL - x ?? */
- MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf0, 0 << 4);
- MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf, adjusted_cas);
- MCHBAR16_AND_OR(0x400*i + 0x265, ~0x3f00,
- (adjusted_cas + 9) << 8);
+ mchbar_clrsetbits8(0x400 * i + 0x240, 0xf << 4, 0 << 4);
+ mchbar_clrsetbits8(0x400 * i + 0x240, 0xf, adjusted_cas);
+ mchbar_clrsetbits16(0x400 * i + 0x265, 0x3f << 8, (adjusted_cas + 9) << 8);
reg16 = (s->selected_timings.tRAS << 11) |
((twl + 4 + s->selected_timings.tWR) << 6) |
((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1;
- MCHBAR16(0x400*i + 0x250) = reg16;
+ mchbar_write16(0x400 * i + 0x250, reg16);
reg32 = (bankmod << 21) |
(s->selected_timings.tRRD << 17) |
@@ -521,7 +519,7 @@
((s->selected_timings.tRP + trpmod) << 9) |
s->selected_timings.tRFC;
if (bankmod == 0) {
- reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1;
+ reg8 = mchbar_read8(0x400 * i + 0x26f) >> 1 & 1;
if (s->spd_type == DDR2)
reg32 |= ddr2_x252_tab[s->selected_timings.mem_clk
- MEM_CLOCK_667MHz][reg8][pagemod] << 22;
@@ -529,24 +527,23 @@
reg32 |= ddr3_x252_tab[s->selected_timings.mem_clk
- MEM_CLOCK_800MHz][reg8][pagemod] << 22;
}
- MCHBAR32(0x400*i + 0x252) = reg32;
+ mchbar_write32(0x400 * i + 0x252, reg32);
- MCHBAR16(0x400*i + 0x256) = (s->selected_timings.tRCD << 12) |
- (0x4 << 8) | (ta2 << 4) | ta4;
+ mchbar_write16(0x400 * i + 0x256, s->selected_timings.tRCD << 12 | 4 << 8 |
+ ta2 << 4 | ta4);
- MCHBAR32(0x400*i + 0x258) = (s->selected_timings.tRCD << 17) |
- ((twl + 4 + s->selected_timings.tWTR) << 12) |
- (ta3 << 8) | (4 << 4) | ta1;
+ mchbar_write32(0x400 * i + 0x258, s->selected_timings.tRCD << 17 |
+ (twl + 4 + s->selected_timings.tWTR) << 12 |
+ ta3 << 8 | 4 << 4 | ta1);
- MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) |
- s->selected_timings.tRFC;
+ mchbar_write16(0x400 * i + 0x25b, (s->selected_timings.tRP + trpmod) << 9 |
+ s->selected_timings.tRFC);
- MCHBAR16_AND_OR(0x400*i + 0x260, ~0x3fe,
+ mchbar_clrsetbits16(0x400 * i + 0x260, 0x1ff << 1,
(s->spd_type == DDR2 ? 100 : 256) << 1);
- MCHBAR8(0x400*i + 0x264) = 0xff;
- MCHBAR8_AND_OR(0x400*i + 0x25d, ~0x3f,
- s->selected_timings.tRAS);
- MCHBAR16(0x400*i + 0x244) = 0x2310;
+ mchbar_write8(0x400 * i + 0x264, 0xff);
+ mchbar_clrsetbits8(0x400 * i + 0x25d, 0x3f, s->selected_timings.tRAS);
+ mchbar_write16(0x400 * i + 0x244, 0x2310);
switch (s->selected_timings.mem_clk) {
case MEM_CLOCK_667MHz:
@@ -557,7 +554,7 @@
break;
}
- MCHBAR8_AND_OR(0x400*i + 0x246, ~0x1f, (reg8 << 2) | 1);
+ mchbar_clrsetbits8(0x400 * i + 0x246, 0x1f, (reg8 << 2) | 1);
fsb = fsb_to_ps[s->selected_timings.fsb_clk];
ddr = ddr_to_ps[s->selected_timings.mem_clk];
@@ -568,7 +565,7 @@
ddr_to_mhz(s->selected_timings.mem_clk)) > 2) {
reg32 |= 1 << 24;
}
- MCHBAR32_AND_OR(0x400*i + 0x248, ~0x0f001f00, reg32);
+ mchbar_clrsetbits32(0x400 * i + 0x248, 0x0f001f00, reg32);
if (twl > 2)
flag1 = 1;
@@ -584,13 +581,13 @@
}
reg16 |= flag1 << 8;
reg16 |= flag2 << 9;
- MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x1ff, reg16);
- MCHBAR16(0x400*i + 0x25e) = 0x15a5;
- MCHBAR32_AND(0x400*i + 0x265, ~0x1f);
- MCHBAR32_AND_OR(0x400*i + 0x269, ~0x000fffff,
+ mchbar_clrsetbits16(0x400 * i + 0x24d, 0x1ff, reg16);
+ mchbar_write16(0x400 * i + 0x25e, 0x15a5);
+ mchbar_clrbits32(0x400 * i + 0x265, 0x1f);
+ mchbar_clrsetbits32(0x400 * i + 0x269, 0x000fffff,
(0x3f << 14) | lut1[s->selected_timings.mem_clk]);
- MCHBAR8_OR(0x400*i + 0x274, 1);
- MCHBAR8_AND(0x400*i + 0x24c, ~0x3);
+ mchbar_setbits8(0x400 * i + 0x274, 1);
+ mchbar_clrbits8(0x400 * i + 0x24c, 3);
reg16 = 0;
if (s->spd_type == DDR2) {
@@ -622,48 +619,48 @@
reg16 &= 0x7;
reg16 += twl + 9;
reg16 <<= 10;
- MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x7c00, reg16);
- MCHBAR8_AND_OR(0x400*i + 0x267, ~0x3f, 0x13);
- MCHBAR8_AND_OR(0x400*i + 0x268, ~0xff, 0x4a);
+ mchbar_clrsetbits16(0x400 * i + 0x24d, 0x1f << 10, reg16);
+ mchbar_clrsetbits8(0x400 * i + 0x267, 0x3f, 0x13);
+ mchbar_clrsetbits8(0x400 * i + 0x268, 0xff, 0x4a);
- reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2;
+ reg16 = (mchbar_read16(0x400 * i + 0x269) & 0xc000) >> 2;
reg16 += 2 << 12;
reg16 |= (0x15 << 6) | 0x1f;
- MCHBAR16_AND_OR(0x400*i + 0x26d, ~0x7fff, reg16);
+ mchbar_clrsetbits16(0x400 * i + 0x26d, 0x7fff, reg16);
reg32 = (1 << 25) | (6 << 27);
- MCHBAR32_AND_OR(0x400*i + 0x269, ~0xfa300000, reg32);
- MCHBAR8_AND(0x400*i + 0x271, ~0x80);
- MCHBAR8_AND(0x400*i + 0x274, ~0x6);
+ mchbar_clrsetbits32(0x400 * i + 0x269, 0xfa300000, reg32);
+ mchbar_clrbits8(0x400 * i + 0x271, 1 << 7);
+ mchbar_clrbits8(0x400 * i + 0x274, 3 << 1);
} /* END EACH POPULATED CHANNEL */
reg16 = 0x1f << 5;
reg16 |= 0xe << 10;
- MCHBAR16_AND_OR(0x125, ~0x3fe0, reg16);
- MCHBAR16_AND_OR(0x127, ~0x7ff, 0x540);
- MCHBAR8_OR(0x129, 0x1f);
- MCHBAR8_OR(0x12c, 0xa0);
- MCHBAR32_AND_OR(0x241, ~0x1ffff, 0x11);
- MCHBAR32_AND_OR(0x641, ~0x1ffff, 0x11);
- MCHBAR8_AND(0x246, ~0x10);
- MCHBAR8_AND(0x646, ~0x10);
- MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f;
- reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13);
- MCHBAR8_AND_OR(0x12d, ~0xf0, reg8 << 4);
- reg8 = (u8)((MCHBAR32(0x258) & 0x1e0000) >> 17);
- MCHBAR8_AND_OR(0x12d, ~0xf, reg8);
- MCHBAR8(0x12f) = 0x4c;
+ mchbar_clrsetbits16(0x125, 0x1ff << 5, reg16);
+ mchbar_clrsetbits16(0x127, 0x7ff, 0x540);
+ mchbar_setbits8(0x129, 0x1f);
+ mchbar_setbits8(0x12c, 0xa0);
+ mchbar_clrsetbits32(0x241, 0x1ffff, 0x11);
+ mchbar_clrsetbits32(0x641, 0x1ffff, 0x11);
+ mchbar_clrbits8(0x246, 1 << 4);
+ mchbar_clrbits8(0x646, 1 << 4);
+ mchbar_write32(0x120, 2 << 29 | 1 << 28 | 1 << 23 | 0xd7f5f);
+ reg8 = (u8)(mchbar_read32(0x252) >> 13 & 0xf);
+ mchbar_clrsetbits8(0x12d, 0xf << 4, reg8 << 4);
+ reg8 = (u8)(mchbar_read32(0x258) >> 17 & 0xf);
+ mchbar_clrsetbits8(0x12d, 0xf << 0, reg8 << 0);
+ mchbar_write8(0x12f, 0x4c);
reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9);
if (s->spd_type == DDR3) {
- MCHBAR8(0x114) = 0x42;
+ mchbar_write8(0x114, 0x42);
reg16 = (512 - MAX(5, s->selected_timings.tRFC + 10000
/ ddr_to_ps[s->selected_timings.mem_clk]))
/ 2;
reg16 &= 0x1ff;
reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9);
}
- MCHBAR32_AND_OR(0x6c0, ~0xffffff00, reg32);
- MCHBAR8_AND_OR(0x6c4, ~0x7, 0x2);
+ mchbar_clrsetbits32(0x6c0, 0xffffff00, reg32);
+ mchbar_clrsetbits8(0x6c4, 0x7, 0x2);
}
static void program_dll(struct sysinfo *s)
@@ -674,11 +671,11 @@
const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, 0x08, 0x10 };
- MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04);
- MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8);
- MCHBAR16_AND_OR(0x18a, ~0x1f1f, 0x0f0f);
- MCHBAR16_AND_OR(0x1b4, ~0x8020, 0x100);
- MCHBAR8_AND_OR(0x194, ~0x77, 0x33);
+ mchbar_clrsetbits16(0x180, 0x7e06, 0xc04);
+ mchbar_clrsetbits16(0x182, 0x3ff, 0xc8);
+ mchbar_clrsetbits16(0x18a, 0x1f1f, 0x0f0f);
+ mchbar_clrsetbits16(0x1b4, 0x8020, 0x100);
+ mchbar_clrsetbits8(0x194, 0x77, 0x33);
switch (s->selected_timings.mem_clk) {
default:
case MEM_CLOCK_667MHz:
@@ -692,47 +689,47 @@
reg16 = (0x7 << 9) | 0x7;
break;
}
- MCHBAR16_AND_OR(0x19c, ~0x1e0f, reg16);
- MCHBAR16_AND_OR(0x19c, ~0x2030, 0x2010);
+ mchbar_clrsetbits16(0x19c, 0xf << 9 | 0xf, reg16);
+ mchbar_clrsetbits16(0x19c, 0x2030, 0x2010);
udelay(1);
- MCHBAR16_AND(0x198, ~0x100);
+ mchbar_clrbits16(0x198, 1 << 8);
- MCHBAR16_AND_OR(0x1c8, ~0x1f, 0xd);
+ mchbar_clrsetbits16(0x1c8, 0x1f, 0xd);
udelay(1);
- MCHBAR8_AND(0x190, ~1);
+ mchbar_clrbits8(0x190, 1);
udelay(1); /* 533ns */
- MCHBAR32_AND(0x198, ~0x11554000);
+ mchbar_clrbits32(0x198, 0x11554000);
udelay(1);
- MCHBAR32_AND(0x198, ~0x1455);
+ mchbar_clrbits32(0x198, 0x1455);
udelay(1);
- MCHBAR8_AND(0x583, ~0x1c);
- MCHBAR8_AND(0x983, ~0x1c);
+ mchbar_clrbits8(0x583, 0x1c);
+ mchbar_clrbits8(0x983, 0x1c);
udelay(1); /* 533ns */
- MCHBAR8_AND(0x583, ~0x3);
- MCHBAR8_AND(0x983, ~0x3);
+ mchbar_clrbits8(0x583, 0x3);
+ mchbar_clrbits8(0x983, 0x3);
udelay(1); /* 533ns */
/* ME related */
- MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, s->spd_type == DDR2 ? 0x551803 : 0x555801);
+ mchbar_clrsetbits32(0x1a0, 0x7ffffff, s->spd_type == DDR2 ? 0x551803 : 0x555801);
- MCHBAR16_AND(0x1b4, ~0x800);
+ mchbar_clrbits16(0x1b4, 0x800);
if (s->spd_type == DDR2) {
- MCHBAR8_OR(0x1a8, 0xf0);
+ mchbar_setbits8(0x1a8, 0xf0);
} else { /* DDR3 */
reg8 = 0x9; /* 0x9 << 4 ?? */
if (s->dimms[0].ranks == 2)
reg8 &= ~0x80;
if (s->dimms[3].ranks == 2)
reg8 &= ~0x10;
- MCHBAR8_AND_OR(0x1a8, ~0xf0, reg8);
+ mchbar_clrsetbits8(0x1a8, 0xf0, reg8);
}
FOR_EACH_CHANNEL(i) {
reg16 = 0;
if ((s->spd_type == DDR3) && (i == 0))
reg16 = (0x3 << 12);
- MCHBAR16_AND_OR(0x400*i + 0x59c, ~0x3000, reg16);
+ mchbar_clrsetbits16(0x400 * i + 0x59c, 0x3 << 12, reg16);
reg32 = 0;
FOR_EACH_RANK_IN_CHANNEL(r) {
@@ -740,8 +737,8 @@
reg32 |= 0x111 << r;
}
- MCHBAR32_AND_OR(0x400*i + 0x59c, ~0xfff, reg32);
- MCHBAR8_AND(0x400*i + 0x594, ~1);
+ mchbar_clrsetbits32(0x400 * i + 0x59c, 0xfff, reg32);
+ mchbar_clrbits8(0x400 * i + 0x594, 1);
if (s->spd_type == DDR2) {
if (!CHANNEL_IS_POPULATED(s->dimms, i)) {
@@ -759,33 +756,34 @@
} else {
die("Unhandled case\n");
}
- MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, (u32)(reg8 << 24));
+ mchbar_clrsetbits32(0x400 * i + 0x5a0, 0x3f000000, reg8 << 24);
} else { /* DDR3 */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {
- MCHBAR8_AND(0x400 * i + 0x5a0 + 3, ~rank2clken[r + i * 4]);
+ mchbar_clrbits8(0x400 * i + 0x5a0 + 3, rank2clken[r + i * 4]);
}
}
} /* END EACH CHANNEL */
if (s->spd_type == DDR2) {
- MCHBAR8_OR(0x1a8, 1);
- MCHBAR8_AND(0x1a8, ~0x4);
+ mchbar_setbits8(0x1a8, 1 << 0);
+ mchbar_clrbits8(0x1a8, 1 << 2);
} else { /* DDR3 */
- MCHBAR8_AND(0x1a8, ~1);
- MCHBAR8_OR(0x1a8, 0x4);
+ mchbar_clrbits8(0x1a8, 1 << 0);
+ mchbar_setbits8(0x1a8, 1 << 2);
}
/* Update DLL timing */
- MCHBAR8_AND(0x1a4, ~0x80);
- MCHBAR8_OR(0x1a4, 0x40);
- MCHBAR16_AND_OR(0x5f0, ~0x400, 0x400);
+ mchbar_clrbits8(0x1a4, 1 << 7);
+ mchbar_setbits8(0x1a4, 1 << 6);
+ mchbar_setbits16(0x5f0, 1 << 10);
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
- MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc);
- MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc);
- MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, s->spd_type == DDR2 ? 0x70 : 0x60);
- MCHBAR16_AND_OR(0x400*i + 0x590, 0, s->spd_type == DDR2 ? 0x5555 : 0xa955);
+ mchbar_setbits16(0x400 * i + 0x5f0, 0x3fc);
+ mchbar_clrbits32(0x400 * i + 0x5fc, 0xcccccccc);
+ mchbar_clrsetbits8(0x400 * i + 0x5d9, 0xf0, s->spd_type == DDR2 ? 0x70 : 0x60);
+ mchbar_clrsetbits16(0x400 * i + 0x590, ~0,
+ s->spd_type == DDR2 ? 0x5555 : 0xa955);
}
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
@@ -820,15 +818,15 @@
}
/* XXX if not async mode */
- MCHBAR16_AND(0x180, ~0x8200);
- MCHBAR8_OR(0x180, 0x4);
+ mchbar_clrbits16(0x180, 1 << 15 | 1 << 9);
+ mchbar_setbits8(0x180, 1 << 2);
j = 0;
for (i = 0; i < 16; i++) {
- MCHBAR8_AND_OR(0x1c8, ~0x1f, i);
- MCHBAR8_OR(0x180, 0x10);
- while (MCHBAR8(0x180) & 0x10)
+ mchbar_clrsetbits8(0x1c8, 0x1f, i);
+ mchbar_setbits8(0x180, 1 << 4);
+ while (mchbar_read8(0x180) & (1 << 4))
;
- if (MCHBAR32(0x184) == 0xffffffff) {
+ if (mchbar_read32(0x184) == 0xffffffff) {
j++;
if (j >= 2)
break;
@@ -845,21 +843,21 @@
j = 0;
i++;
for (; i < 16; i++) {
- MCHBAR8_AND_OR(0x1c8, ~0x1f, i);
- MCHBAR8_OR(0x180, 0x10);
- while (MCHBAR8(0x180) & 0x10)
+ mchbar_clrsetbits8(0x1c8, 0x1f, i);
+ mchbar_setbits8(0x180, 1 << 4);
+ while (mchbar_read8(0x180) & (1 << 4))
;
- if (MCHBAR32(0x184) == 0) {
+ if (mchbar_read32(0x184) == 0) {
i++;
break;
}
}
for (; i < 16; i++) {
- MCHBAR8_AND_OR(0x1c8, ~0x1f, i);
- MCHBAR8_OR(0x180, 0x10);
- while (MCHBAR8(0x180) & 0x10)
+ mchbar_clrsetbits8(0x1c8, 0x1f, i);
+ mchbar_setbits8(0x180, 1 << 4);
+ while (mchbar_read8(0x180) & (1 << 4))
;
- if (MCHBAR32(0x184) == 0xffffffff) {
+ if (mchbar_read32(0x184) == 0xffffffff) {
j++;
if (j >= 2)
break;
@@ -868,16 +866,16 @@
}
}
if (j < 2) {
- MCHBAR8_AND(0x1c8, ~0x1f);
- MCHBAR8_OR(0x180, 0x10);
- while (MCHBAR8(0x180) & 0x10)
+ mchbar_clrsetbits8(0x1c8, 0x1f, 0);
+ mchbar_setbits8(0x180, 1 << 4);
+ while (mchbar_read8(0x180) & (1 << 4))
;
j = 2;
}
}
if (j < 2) {
- MCHBAR8_AND(0x1c8, ~0x1f);
+ mchbar_clrsetbits8(0x1c8, 0x1f, 0);
async = 1;
printk(BIOS_NOTICE, "HMC failed, using async mode\n");
}
@@ -905,32 +903,32 @@
break;
}
- MCHBAR8_AND(0x180, ~0x80);
+ mchbar_clrbits8(0x180, 1 << 7);
if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)
|| (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz
&& s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {
- i = MCHBAR8(0x1c8) & 0xf;
+ i = mchbar_read8(0x1c8) & 0xf;
if (s->spd_type == DDR2)
i = (i + 10) % 14;
else /* DDR3 */
i = (i + 3) % 12;
- MCHBAR8_AND_OR(0x1c8, ~0x1f, i);
- MCHBAR8_OR(0x180, 0x10);
- while (MCHBAR8(0x180) & 0x10)
+ mchbar_clrsetbits8(0x1c8, 0x1f, i);
+ mchbar_setbits8(0x180, 1 << 4);
+ while (mchbar_read8(0x180) & (1 << 4))
;
}
- reg8 = MCHBAR8(0x188) & ~1;
- MCHBAR8(0x188) = reg8;
+ reg8 = mchbar_read8(0x188) & ~1;
+ mchbar_write8(0x188, reg8);
reg8 &= ~0x3e;
reg8 |= clk;
- MCHBAR8(0x188) = reg8;
+ mchbar_write8(0x188, reg8);
reg8 |= 1;
- MCHBAR8(0x188) = reg8;
+ mchbar_write8(0x188, reg8);
if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz)
- MCHBAR8_OR(0x18c, 1);
+ mchbar_setbits8(0x18c, 1);
}
static void select_default_dq_dqs_settings(struct sysinfo *s)
@@ -1077,52 +1075,52 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
/* RCOMP data group is special, program it separately */
- MCHBAR32_AND_OR(0x400*i + 0x31c, ~0xff000, 0xaa000);
- MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, 0x6666);
+ mchbar_clrsetbits32(0x400 * i + 0x31c, 0xff000, 0xaa000);
+ mchbar_clrsetbits16(0x400 * i + 0x320, 0xffff, 0x6666);
for (k = 0; k < 8; k++) {
- MCHBAR32_AND_OR(0x400*i + 0x32a + (k << 2), ~0x3f3f3f3f, x32a[k]);
- MCHBAR32_AND_OR(0x400*i + 0x34a + (k << 2), ~0x3f3f3f3f, x32a[k]);
+ mchbar_clrsetbits32(0x400 * i + 0x32a + (k << 2), 0x3f3f3f3f, x32a[k]);
+ mchbar_clrsetbits32(0x400 * i + 0x34a + (k << 2), 0x3f3f3f3f, x32a[k]);
}
- MCHBAR8_AND_OR(0x400*i + 0x31c, ~1, 0);
+ mchbar_clrsetbits8(0x400 * i + 0x31c, 1, 0);
/* Now program the other RCOMP groups */
for (j = 0; j < ARRAY_SIZE(addr); j++) {
- MCHBAR16_AND_OR(0x400*i + addr[j] + 0, ~0xf000, 0xa000);
- MCHBAR16_AND_OR(0x400*i + addr[j] + 4, ~0xffff, x378[j]);
+ mchbar_clrsetbits16(0x400 * i + addr[j] + 0, 0xf000, 0xa000);
+ mchbar_clrsetbits16(0x400 * i + addr[j] + 4, 0xffff, x378[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x0e, ~0x3f3f3f3f, x382[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12, ~0x3f3f3f3f, x386[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16, ~0x3f3f3f3f, x38a[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a, ~0x3f3f3f3f, x38e[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e, ~0x3f3f3f3f, x392[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22, ~0x3f3f3f3f, x396[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26, ~0x3f3f3f3f, x39a[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, ~0x3f3f3f3f, x39e[j]);
+ mchbar_clrsetbits32(0x400 * i + addr[j] + 0x0e, 0x3f3f3f3f, x382[j]);
+ mchbar_clrsetbits32(0x400 * i + addr[j] + 0x12, 0x3f3f3f3f, x386[j]);
+ mchbar_clrsetbits32(0x400 * i + addr[j] + 0x16, 0x3f3f3f3f, x38a[j]);
+ mchbar_clrsetbits32(0x400 * i + addr[j] + 0x1a, 0x3f3f3f3f, x38e[j]);
+ mchbar_clrsetbits32(0x400 * i + addr[j] + 0x1e, 0x3f3f3f3f, x392[j]);
+ mchbar_clrsetbits32(0x400 * i + addr[j] + 0x22, 0x3f3f3f3f, x396[j]);
+ mchbar_clrsetbits32(0x400 * i + addr[j] + 0x26, 0x3f3f3f3f, x39a[j]);
+ mchbar_clrsetbits32(0x400 * i + addr[j] + 0x2a, 0x3f3f3f3f, x39e[j]);
/* Override command group strength multiplier */
if (s->spd_type == DDR3 && BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
- MCHBAR16_AND_OR(0x378 + 0x400 * i, ~0xffff, 0xcccc);
+ mchbar_clrsetbits16(0x378 + 0x400 * i, 0xffff, 0xcccc);
}
- MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]);
+ mchbar_clrsetbits8(0x400 * i + addr[j], 1, bit[j]);
}
reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36;
- MCHBAR8_AND_OR(0x400*i + 0x45a, ~0x3f, reg8);
- MCHBAR8_AND_OR(0x400*i + 0x45e, ~0x3f, reg8);
- MCHBAR8_AND_OR(0x400*i + 0x462, ~0x3f, reg8);
- MCHBAR8_AND_OR(0x400*i + 0x466, ~0x3f, reg8);
+ mchbar_clrsetbits8(0x400 * i + 0x45a, 0x3f, reg8);
+ mchbar_clrsetbits8(0x400 * i + 0x45e, 0x3f, reg8);
+ mchbar_clrsetbits8(0x400 * i + 0x462, 0x3f, reg8);
+ mchbar_clrsetbits8(0x400 * i + 0x466, 0x3f, reg8);
} /* END EACH POPULATED CHANNEL */
- MCHBAR32_AND_OR(0x134, ~0x63c00, 0x63c00);
- MCHBAR16_AND_OR(0x174, ~0x63ff, 0x63ff);
- MCHBAR16(0x178) = 0x0135;
- MCHBAR32_AND_OR(0x130, ~0x7bdffe0, 0x7a9ffa0);
+ mchbar_clrsetbits32(0x134, 0x63c00, 0x63c00);
+ mchbar_clrsetbits16(0x174, 0x63ff, 0x63ff);
+ mchbar_write16(0x178, 0x0135);
+ mchbar_clrsetbits32(0x130, 0x7bdffe0, 0x7a9ffa0);
if (!CHANNEL_IS_POPULATED(s->dimms, 0))
- MCHBAR32_AND(0x130, ~(1 << 27));
+ mchbar_clrbits32(0x130, 1 << 27);
if (!CHANNEL_IS_POPULATED(s->dimms, 1))
- MCHBAR32_AND(0x130, ~(1 << 28));
+ mchbar_clrbits32(0x130, 1 << 28);
- MCHBAR8_OR(0x130, 1);
+ mchbar_setbits8(0x130, 1);
}
static void program_odt(struct sysinfo *s)
@@ -1168,17 +1166,17 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
if (s->spd_type == DDR2) {
- MCHBAR16(0x400 * i + 0x298) = ddr2_odt[s->dimm_config[i]][1];
- MCHBAR16(0x400 * i + 0x294) = ddr2_odt[s->dimm_config[i]][0];
+ mchbar_write16(0x400 * i + 0x298, ddr2_odt[s->dimm_config[i]][1]);
+ mchbar_write16(0x400 * i + 0x294, ddr2_odt[s->dimm_config[i]][0]);
} else {
- MCHBAR16(0x400 * i + 0x298) = ddr3_odt[s->dimm_config[i]][1];
- MCHBAR16(0x400 * i + 0x294) = ddr3_odt[s->dimm_config[i]][0];
+ mchbar_write16(0x400 * i + 0x298, ddr3_odt[s->dimm_config[i]][1]);
+ mchbar_write16(0x400 * i + 0x294, ddr3_odt[s->dimm_config[i]][0]);
}
- u16 reg16 = MCHBAR16(0x400*i + 0x29c);
+ u16 reg16 = mchbar_read16(0x400 * i + 0x29c);
reg16 &= ~0xfff;
reg16 |= (s->spd_type == DDR2 ? 0x66b : 0x778);
- MCHBAR16(0x400*i + 0x29c) = reg16;
- MCHBAR32_AND_OR(0x400*i + 0x260, ~0x70e3c00, 0x3063c00);
+ mchbar_write16(0x400 * i + 0x29c, reg16);
+ mchbar_clrsetbits32(0x400 * i + 0x260, 0x70e3c00, 0x3063c00);
}
}
@@ -1211,29 +1209,29 @@
* by the SPD.
*/
/* Set rank 0-3 populated */
- MCHBAR32_AND_OR(C0CKECTRL, ~1, 0xf00000);
- MCHBAR32_AND_OR(C1CKECTRL, ~1, 0xf00000);
+ mchbar_clrsetbits32(C0CKECTRL, 1 << 0, 0xf << 20);
+ mchbar_clrsetbits32(C1CKECTRL, 1 << 0, 0xf << 20);
/* Set size of each rank to 128M */
- MCHBAR16(C0DRA01) = 0x0101;
- MCHBAR16(C0DRA23) = 0x0101;
- MCHBAR16(C1DRA01) = 0x0101;
- MCHBAR16(C1DRA23) = 0x0101;
- MCHBAR16(C0DRB0) = 0x0002;
- MCHBAR16(C0DRB1) = 0x0004;
- MCHBAR16(C0DRB2) = 0x0006;
- MCHBAR16(C0DRB3) = 0x0008;
- MCHBAR16(C1DRB0) = 0x0002;
- MCHBAR16(C1DRB1) = 0x0004;
- MCHBAR16(C1DRB2) = 0x0006;
+ mchbar_write16(C0DRA01, 0x0101);
+ mchbar_write16(C0DRA23, 0x0101);
+ mchbar_write16(C1DRA01, 0x0101);
+ mchbar_write16(C1DRA23, 0x0101);
+ mchbar_write16(C0DRB0, 0x0002);
+ mchbar_write16(C0DRB1, 0x0004);
+ mchbar_write16(C0DRB2, 0x0006);
+ mchbar_write16(C0DRB3, 0x0008);
+ mchbar_write16(C1DRB0, 0x0002);
+ mchbar_write16(C1DRB1, 0x0004);
+ mchbar_write16(C1DRB2, 0x0006);
/* In stacked mode the last present rank on ch1 needs to have its
size doubled in c1drbx */
- MCHBAR16(C1DRB3) = 0x0010;
- MCHBAR8_OR(0x111, STACKED_MEM);
- MCHBAR32(0x104) = 0;
- MCHBAR16(0x102) = 0x400;
- MCHBAR8(0x110) = (2 << 5) | (3 << 3);
- MCHBAR16(0x10e) = 0;
- MCHBAR32(0x108) = 0;
+ mchbar_write16(C1DRB3, 0x0010);
+ mchbar_setbits8(0x111, STACKED_MEM);
+ mchbar_write32(0x104, 0);
+ mchbar_write16(0x102, 0x400);
+ mchbar_write8(0x110, 2 << 5 | 3 << 3);
+ mchbar_write16(0x10e, 0);
+ mchbar_write32(0x108, 0);
pci_write_config16(HOST_BRIDGE, D0F0_TOLUD, 0x4000);
/* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */
pci_write_config16(HOST_BRIDGE, D0F0_TOM, 0x10);
@@ -1274,8 +1272,8 @@
data8 = (u8)mirror_shift_bit(data8, 4);
}
- MCHBAR8_AND_OR(0x271, ~0x3e, data8);
- MCHBAR8_AND_OR(0x671, ~0x3e, data8);
+ mchbar_clrsetbits8(0x271, 0x3e, data8);
+ mchbar_clrsetbits8(0x671, 0x3e, data8);
data32 = val;
if (s->spd_type == DDR3 && (r & 1)
&& s->dimms[ch * 2 + (r >> 1)].mirrored) {
@@ -1287,8 +1285,8 @@
read32((void *)((data32 | addr)));
udelay(10);
- MCHBAR8_AND_OR(0x271, ~0x3e, NORMALOP_CMD);
- MCHBAR8_AND_OR(0x671, ~0x3e, NORMALOP_CMD);
+ mchbar_clrsetbits8(0x271, 0x3e, NORMALOP_CMD);
+ mchbar_clrsetbits8(0x671, 0x3e, NORMALOP_CMD);
}
static void jedec_ddr2(struct sysinfo *s)
@@ -1417,24 +1415,24 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) {
medium = 0;
coarse_offset = 0;
- reg32 = MCHBAR32(0x400 * channel + 0x248);
+ reg32 = mchbar_read32(0x400 * channel + 0x248);
reg32 &= ~0xf0000;
reg32 |= s->rcven_t[channel].min_common_coarse << 16;
- MCHBAR32(0x400 * channel + 0x248) = reg32;
+ mchbar_write32(0x400 * channel + 0x248, reg32);
FOR_EACH_BYTELANE(lane) {
medium |= s->rcven_t[channel].medium[lane] << (lane * 2);
coarse_offset |=
(s->rcven_t[channel].coarse_offset[lane] & 0x3) << (lane * 2);
- pi_tap = MCHBAR8(0x400 * channel + 0x560 + lane * 4);
+ pi_tap = mchbar_read8(0x400 * channel + 0x560 + lane * 4);
pi_tap &= ~0x7f;
pi_tap |= s->rcven_t[channel].tap[lane];
pi_tap |= s->rcven_t[channel].pi[lane] << 4;
- MCHBAR8(0x400 * channel + 0x560 + lane * 4) = pi_tap;
+ mchbar_write8(0x400 * channel + 0x560 + lane * 4, pi_tap);
}
- MCHBAR16(0x400 * channel + 0x58c) = medium;
- MCHBAR16(0x400 * channel + 0x5fa) = coarse_offset;
+ mchbar_write16(0x400 * channel + 0x58c, medium);
+ mchbar_write16(0x400 * channel + 0x5fa, coarse_offset);
}
}
@@ -1509,23 +1507,23 @@
rankpop1 |= 1 << r;
}
}
- MCHBAR32(0x208) = c0dra;
- MCHBAR32(0x608) = c1dra;
+ mchbar_write32(0x208, c0dra);
+ mchbar_write32(0x608, c1dra);
- MCHBAR8_AND_OR(0x262, ~0xf0, (rankpop0 << 4) & 0xf0);
- MCHBAR8_AND_OR(0x662, ~0xf0, (rankpop1 << 4) & 0xf0);
+ mchbar_clrsetbits8(0x262, 0xf0, (rankpop0 << 4) & 0xf0);
+ mchbar_clrsetbits8(0x662, 0xf0, (rankpop1 << 4) & 0xf0);
if (s->spd_type == DDR3) {
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
/* ZQCAL enable */
- MCHBAR32_OR(0x269 + 0x400 * ch, 1 << 26);
+ mchbar_setbits32(0x269 + 0x400 * ch, 1 << 26);
}
}
if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0))
- MCHBAR8_OR(0x260, 1);
+ mchbar_setbits8(0x260, 1);
if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1))
- MCHBAR8_OR(0x660, 1);
+ mchbar_setbits8(0x660, 1);
/* DRB */
lastrank_ch1 = 0;
@@ -1535,14 +1533,14 @@
dra0 = (c0dra >> (8*r)) & 0x7f;
c0drb = (u16)(c0drb + drbtab[dra0]);
}
- MCHBAR16(0x200 + 2*r) = c0drb;
+ mchbar_write16(0x200 + 2 * r, c0drb);
} else {
if (RANK_IS_POPULATED(s->dimms, ch, r)) {
lastrank_ch1 = r;
dra1 = (c1dra >> (8*r)) & 0x7f;
c1drb = (u16)(c1drb + drbtab[dra1]);
}
- MCHBAR16(0x600 + 2*r) = c1drb;
+ mchbar_write16(0x600 + 2 * r, c1drb);
}
}
@@ -1556,7 +1554,7 @@
*/
if (s->stacked_mode) {
for (r = lastrank_ch1; r < 4; r++)
- MCHBAR16(0x600 + 2*r) = 2 * c1drb;
+ mchbar_write16(0x600 + 2 * r, 2 * c1drb);
}
totalmemorymb = s->channel_capacity[0] + s->channel_capacity[1];
@@ -1569,10 +1567,10 @@
size_me = ME_UMA_SIZEMB;
if (s->stacked_mode) {
- MCHBAR8_OR(0x111, STACKED_MEM);
+ mchbar_setbits8(0x111, STACKED_MEM);
} else {
- MCHBAR8_AND(0x111, ~STACKED_MEM);
- MCHBAR8_OR(0x111, 1 << 4);
+ mchbar_clrbits8(0x111, STACKED_MEM);
+ mchbar_setbits8(0x111, 1 << 4);
}
if (s->stacked_mode) {
@@ -1586,16 +1584,16 @@
/* TOTEST: bailout? */
} else {
/* Set ME UMA size in MiB */
- MCHBAR16(0x100) = size_me;
+ mchbar_write16(0x100, size_me);
/* Set ME UMA Present bit */
- MCHBAR32_OR(0x111, 1);
+ mchbar_setbits8(0x111, 1 << 0);
}
dual_channel_size = MIN(size_ch0 - size_me, size_ch1) * 2;
}
- MCHBAR16(0x104) = dual_channel_size;
+ mchbar_write16(0x104, dual_channel_size);
single_channel_size = size_ch0 + size_ch1 - dual_channel_size;
- MCHBAR16(0x102) = single_channel_size;
+ mchbar_write16(0x102, single_channel_size);
map = 0;
if (size_ch0 == 0)
@@ -1619,8 +1617,8 @@
map |= 0x04;
}
- MCHBAR8(0x110) = map;
- MCHBAR16(0x10e) = 0;
+ mchbar_write8(0x110, map);
+ mchbar_write16(0x10e, 0);
/*
* "108h[15:0] Single Channel Offset for Ch0"
@@ -1643,8 +1641,8 @@
single_channel_offset = dual_channel_size / 2 + size_me;
}
- MCHBAR16(0x108) = single_channel_offset;
- MCHBAR16(0x10a) = dual_channel_size / 2;
+ mchbar_write16(0x108, single_channel_offset);
+ mchbar_write16(0x10a, dual_channel_size / 2);
}
static void configure_mmap(struct sysinfo *s)
@@ -1707,34 +1705,34 @@
u8 ch, reg8;
u32 reg32;
- MCHBAR32(0xfb0) = 0x1000d024;
- MCHBAR32(0xfb4) = 0xc842;
- MCHBAR32(0xfbc) = 0xf;
- MCHBAR32(0xfc4) = 0xfe22244;
- MCHBAR8(0x12f) = 0x5c;
- MCHBAR8_OR(0xfb0, 1);
+ mchbar_write32(0xfb0, 0x1000d024);
+ mchbar_write32(0xfb4, 0xc842);
+ mchbar_write32(0xfbc, 0xf);
+ mchbar_write32(0xfc4, 0xfe22244);
+ mchbar_write8(0x12f, 0x5c);
+ mchbar_setbits8(0xfb0, 1 << 0);
if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz)
- MCHBAR8_OR(0x12f, 0x2);
+ mchbar_setbits8(0x12f, 1 << 1);
else
- MCHBAR8_AND(0x12f, ~0x2);
- MCHBAR8_AND_OR(0x6c0, ~0xf0, 0xa0);
- MCHBAR32(0xfa8) = 0x30d400;
+ mchbar_clrbits8(0x12f, 1 << 1);
+ mchbar_clrsetbits8(0x6c0, 0xf0, 0xa0);
+ mchbar_write32(0xfa8, 0x30d400);
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
- MCHBAR8_OR(0x400*ch + 0x26c, 1);
- MCHBAR32(0x400*ch + 0x278) = 0x88141881;
- MCHBAR16(0x400*ch + 0x27c) = 0x0041;
- MCHBAR8(0x400*ch + 0x292) = 0xf2;
- MCHBAR16_OR(0x400*ch + 0x272, 0x100);
- MCHBAR8_AND_OR(0x400*ch + 0x243, ~0x2, 1);
- MCHBAR32(0x400*ch + 0x288) = 0x8040200;
- MCHBAR32(0x400*ch + 0x28c) = 0xff402010;
- MCHBAR32(0x400*ch + 0x290) = 0x4f2091c;
+ mchbar_setbits8(0x400 * ch + 0x26c, 1);
+ mchbar_write32(0x400 * ch + 0x278, 0x88141881);
+ mchbar_write16(0x400 * ch + 0x27c, 0x0041);
+ mchbar_write8(0x400 * ch + 0x292, 0xf2);
+ mchbar_setbits16(0x400 * ch + 0x272, 1 << 8);
+ mchbar_clrsetbits8(0x400 * ch + 0x243, 3, 1);
+ mchbar_write32(0x400 * ch + 0x288, 0x8040200);
+ mchbar_write32(0x400 * ch + 0x28c, 0xff402010);
+ mchbar_write32(0x400 * ch + 0x290, 0x4f2091c);
}
reg8 = pci_read_config8(HOST_BRIDGE, 0xf0);
pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1);
- MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk ==
+ mchbar_clrsetbits32(0xfa0, 0x20002, 0x2 | (s->selected_timings.fsb_clk ==
FSB_CLOCK_1333MHz ? 0x20000 : 0));
reg32 = 0x219100c2;
if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) {
@@ -1744,7 +1742,7 @@
} else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) {
reg32 &= ~0x10000;
}
- MCHBAR32_AND_OR(0xfa4, ~0x219100c3, reg32);
+ mchbar_clrsetbits32(0xfa4, 0x219100c3, reg32);
reg32 = 0x44a00;
switch (s->selected_timings.fsb_clk) {
case FSB_CLOCK_1333MHz:
@@ -1759,22 +1757,22 @@
break;
}
- MCHBAR32(0x2c) = reg32;
- MCHBAR32(0x30) = 0x1f5a86;
- MCHBAR32(0x34) = 0x1902810;
- MCHBAR32(0x38) = 0xf7000000;
+ mchbar_write32(0x2c, reg32);
+ mchbar_write32(0x30, 0x1f5a86);
+ mchbar_write32(0x34, 0x1902810);
+ mchbar_write32(0x38, 0xf7000000);
reg32 = 0x23014410;
if (s->selected_timings.fsb_clk > FSB_CLOCK_800MHz)
reg32 = (reg32 & ~0x2000000) | 0x44000000;
- MCHBAR32(0x3c) = reg32;
+ mchbar_write32(0x3c, reg32);
reg32 = 0x8f038000;
if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz)
reg32 &= ~0x4000000;
- MCHBAR32_AND_OR(0x40, ~0x8f038000, reg32);
+ mchbar_clrsetbits32(0x40, 0x8f038000, reg32);
reg32 = 0x00013001;
if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz)
reg32 |= 0x20000;
- MCHBAR32(0x20) = reg32;
+ mchbar_write32(0x20, reg32);
pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1);
}
@@ -1838,95 +1836,95 @@
}
if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1))
- MCHBAR32(0x14) = 0x0010461f;
+ mchbar_write32(0x14, 0x0010461f);
else
- MCHBAR32(0x14) = 0x0010691f;
- MCHBAR32(0x18) = 0xdf6437f7;
- MCHBAR32(0x1c) = 0x0;
- MCHBAR32_AND_OR(0x24, ~0xe0000000, 0x60000000);
- MCHBAR32_AND_OR(0x44, ~0x1fef0000, 0x6b0000);
- MCHBAR16(0x115) = (u16) reg1;
- MCHBAR32_AND_OR(0x117, ~0xffffff, reg2);
- MCHBAR8(0x124) = 0x7;
+ mchbar_write32(0x14, 0x0010691f);
+ mchbar_write32(0x18, 0xdf6437f7);
+ mchbar_write32(0x1c, 0);
+ mchbar_clrsetbits32(0x24, 0xe0000000, 0x60000000);
+ mchbar_clrsetbits32(0x44, 0x1fef0000, 0x6b0000);
+ mchbar_write16(0x115, reg1);
+ mchbar_clrsetbits32(0x117, 0xffffff, reg2);
+ mchbar_write8(0x124, 0x7);
/* not sure if dummy reads are needed */
- MCHBAR16_AND_OR(0x12a, 0, 0x80);
- MCHBAR8_AND_OR(0x12c, 0, 0xa0);
- MCHBAR16_AND(0x174, ~(1 << 15));
- MCHBAR16_AND_OR(0x188, ~0x1f00, 0x1f00);
- MCHBAR8_AND(0x18c, ~0x8);
- MCHBAR8_OR(0x192, 1);
- MCHBAR8_OR(0x193, 0xf);
- MCHBAR16_AND_OR(0x1b4, ~0x480, 0x80);
- MCHBAR16_AND_OR(0x210, ~0x1fff, 0x3f); /* clockgating iii */
+ mchbar_clrsetbits16(0x12a, ~0, 0x80);
+ mchbar_clrsetbits8(0x12c, ~0, 0xa0);
+ mchbar_clrbits16(0x174, 1 << 15);
+ mchbar_clrsetbits16(0x188, 0x1f00, 0x1f00);
+ mchbar_clrbits8(0x18c, 1 << 3);
+ mchbar_setbits8(0x192, 1);
+ mchbar_setbits8(0x193, 0xf);
+ mchbar_clrsetbits16(0x1b4, 0x480, 0x80);
+ mchbar_clrsetbits16(0x210, 0x1fff, 0x3f); /* clockgating iii */
/* non-aligned access: possible bug? */
- MCHBAR32_AND_OR(0x6d1, ~0xff03ff, 0x100 | clkgate);
- MCHBAR8_AND_OR(0x212, ~0x7f, 0x7f);
- MCHBAR32_AND_OR(0x2c0, ~0xffff0, 0xcc5f0);
- MCHBAR8_AND_OR(0x2c4, ~0x70, 0x70);
+ mchbar_clrsetbits32(0x6d1, 0xff03ff, 0x100 | clkgate);
+ mchbar_clrsetbits8(0x212, 0x7f, 0x7f);
+ mchbar_clrsetbits32(0x2c0, 0xffff0, 0xcc5f0);
+ mchbar_clrsetbits8(0x2c4, 0x70, 0x70);
/* non-aligned access: possible bug? */
- MCHBAR32_AND_OR(0x2d1, ~0xffffff, 0xff2831); /* clockgating i */
- MCHBAR32(0x2d4) = 0x40453600;
- MCHBAR32(0x300) = 0xc0b0a08;
- MCHBAR32(0x304) = 0x6040201;
- MCHBAR32_AND_OR(0x30c, ~0x43c0f, 0x41405);
- MCHBAR16(0x610) = reg3;
- MCHBAR16(0x612) = reg4;
- MCHBAR32_AND_OR(0x62c, ~0xc000000, 0x4000000);
- MCHBAR32(0xae4) = 0;
- MCHBAR32_AND_OR(0xc00, ~0xf0000, 0x10000);
- MCHBAR32(0xf00) = 0x393a3b3c;
- MCHBAR32(0xf04) = 0x3d3e3f40;
- MCHBAR32(0xf08) = 0x393a3b3c;
- MCHBAR32(0xf0c) = 0x3d3e3f40;
- MCHBAR32_AND(0xf18, ~0xfff00001);
- MCHBAR32(0xf48) = 0xfff0ffe0;
- MCHBAR32(0xf4c) = 0xffc0ff00;
- MCHBAR32(0xf50) = 0xfc00f000;
- MCHBAR32(0xf54) = 0xc0008000;
- MCHBAR32_AND_OR(0xf6c, ~0xffff0000, 0xffff0000);
- MCHBAR32_AND(0xfac, ~0x80000000);
- MCHBAR32_AND(0xfb8, ~0xff000000);
- MCHBAR32_AND_OR(0xfbc, ~0x7f800, 0xf000);
- MCHBAR32(0x1104) = 0x3003232;
- MCHBAR32(0x1108) = 0x74;
+ mchbar_clrsetbits32(0x2d1, 0xffffff, 0xff2831); /* clockgating i */
+ mchbar_write32(0x2d4, 0x40453600);
+ mchbar_write32(0x300, 0xc0b0a08);
+ mchbar_write32(0x304, 0x6040201);
+ mchbar_clrsetbits32(0x30c, 0x43c0f, 0x41405);
+ mchbar_write16(0x610, reg3);
+ mchbar_write16(0x612, reg4);
+ mchbar_clrsetbits32(0x62c, 0xc000000, 0x4000000);
+ mchbar_write32(0xae4, 0);
+ mchbar_clrsetbits32(0xc00, 0xf0000, 0x10000);
+ mchbar_write32(0xf00, 0x393a3b3c);
+ mchbar_write32(0xf04, 0x3d3e3f40);
+ mchbar_write32(0xf08, 0x393a3b3c);
+ mchbar_write32(0xf0c, 0x3d3e3f40);
+ mchbar_clrbits32(0xf18, 0xfff00001);
+ mchbar_write32(0xf48, 0xfff0ffe0);
+ mchbar_write32(0xf4c, 0xffc0ff00);
+ mchbar_write32(0xf50, 0xfc00f000);
+ mchbar_write32(0xf54, 0xc0008000);
+ mchbar_clrsetbits32(0xf6c, 0xffff0000, 0xffff0000);
+ mchbar_clrbits32(0xfac, 0x80000000);
+ mchbar_clrbits32(0xfb8, 0xff000000);
+ mchbar_clrsetbits32(0xfbc, 0x7f800, 0xf000);
+ mchbar_write32(0x1104, 0x3003232);
+ mchbar_write32(0x1108, 0x74);
if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz)
- MCHBAR32(0x110c) = 0xaa;
+ mchbar_write32(0x110c, 0xaa);
else
- MCHBAR32(0x110c) = 0x100;
- MCHBAR32(0x1110) = 0x10810350 & ~0x78;
- MCHBAR32(0x1114) = 0;
+ mchbar_write32(0x110c, 0x100);
+ mchbar_write32(0x1110, 0x10810350 & ~0x78);
+ mchbar_write32(0x1114, 0);
x592 = 0xff;
if (pci_read_config8(HOST_BRIDGE, 0x8) < 3)
x592 = ~0x4;
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
- MCHBAR8(0x400*ch + 0x239) = twl + 15;
- MCHBAR16(0x400*ch + 0x23c) = x23c;
- MCHBAR32_AND_OR(0x400*ch + 0x248, ~0x706033, 0x406033);
- MCHBAR32_AND_OR(0x400*ch + 0x260, ~(1 << 16), 1 << 16);
- MCHBAR8(0x400*ch + 0x264) = x264;
- MCHBAR8_AND_OR(0x400*ch + 0x592, ~0x3f, 0x3c & x592);
- MCHBAR8_AND_OR(0x400*ch + 0x593, ~0x1f, 0x1e);
+ mchbar_write8(0x400 * ch + 0x239, twl + 15);
+ mchbar_write16(0x400 * ch + 0x23c, x23c);
+ mchbar_clrsetbits32(0x400 * ch + 0x248, 0x706033, 0x406033);
+ mchbar_clrsetbits32(0x400 * ch + 0x260, 1 << 16, 1 << 16);
+ mchbar_write8(0x400 * ch + 0x264, x264);
+ mchbar_clrsetbits8(0x400 * ch + 0x592, 0x3f, 0x3c & x592);
+ mchbar_clrsetbits8(0x400 * ch + 0x593, 0x1f, 0x1e);
}
for (lane = 0; lane < 8; lane++)
- MCHBAR8_AND(0x561 + (lane << 2), ~(1 << 3));
+ mchbar_clrbits8(0x561 + (lane << 2), 1 << 3);
}
static void software_ddr3_reset(struct sysinfo *s)
{
printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n");
- MCHBAR8_OR(0x1a8, 0x02);
- MCHBAR8_AND(0x5da, ~0x80);
- MCHBAR8_AND(0x1a8, ~0x02);
- MCHBAR8_AND_OR(0x5da, ~0x03, 1);
+ mchbar_setbits8(0x1a8, 1 << 1);
+ mchbar_clrbits8(0x5da, 1 << 7);
+ mchbar_clrbits8(0x1a8, 1 << 1);
+ mchbar_clrsetbits8(0x5da, 3, 1);
udelay(200);
- MCHBAR8_AND(0x1a8, ~0x02);
- MCHBAR8_OR(0x5da, 0x80);
- MCHBAR8_AND(0x5da, ~0x80);
+ mchbar_clrbits8(0x1a8, 1 << 1);
+ mchbar_setbits8(0x5da, 1 << 7);
+ mchbar_clrbits8(0x5da, 1 << 7);
udelay(500);
- MCHBAR8_OR(0x5da, 0x03);
- MCHBAR8_AND(0x5da, ~0x03);
+ mchbar_setbits8(0x5da, 3);
+ mchbar_clrbits8(0x5da, 3);
/* After write leveling the dram needs to be reset and reinitialised */
jedec_ddr3(s);
}
@@ -1939,25 +1937,24 @@
if (s->boot_path != BOOT_PATH_WARM_RESET) {
/* Clear self refresh */
- MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR)
- | PMSTS_BOTH_SELFREFRESH;
+ mchbar_setbits32(PMSTS_MCHBAR, PMSTS_BOTH_SELFREFRESH);
/* Clear host clk gate reg */
- MCHBAR32_OR(0x1c, 0xffffffff);
+ mchbar_setbits32(0x1c, 0xffffffff);
/* Select type */
if (s->spd_type == DDR2)
- MCHBAR8_AND(0x1a8, ~0x4);
+ mchbar_clrbits8(0x1a8, 1 << 2);
else
- MCHBAR8_OR(0x1a8, 0x4);
+ mchbar_setbits8(0x1a8, 1 << 2);
/* Set frequency */
- MCHBAR32_AND_OR(CLKCFG_MCHBAR, ~CLKCFG_MEMCLK_MASK,
+ mchbar_clrsetbits32(CLKCFG_MCHBAR, CLKCFG_MEMCLK_MASK,
(s->selected_timings.mem_clk << CLKCFG_MEMCLK_SHIFT) | CLKCFG_UPDATE);
/* Overwrite value if chipset rejects it */
- s->selected_timings.mem_clk =
- (MCHBAR8(CLKCFG_MCHBAR) & CLKCFG_MEMCLK_MASK) >> CLKCFG_MEMCLK_SHIFT;
+ s->selected_timings.mem_clk = (mchbar_read8(CLKCFG_MCHBAR) &
+ CLKCFG_MEMCLK_MASK) >> CLKCFG_MEMCLK_SHIFT;
if (s->selected_timings.mem_clk > (s->max_fsb + 3))
die("Error: DDR is faster than FSB, halt\n");
}
@@ -1997,7 +1994,7 @@
/* RCOMP update */
if (s->boot_path != BOOT_PATH_WARM_RESET) {
- while (MCHBAR8(0x130) & 1)
+ while (mchbar_read8(0x130) & 1)
;
printk(BIOS_DEBUG, "Done RCOMP update\n");
}
@@ -2006,36 +2003,36 @@
/* IOBUFACT */
if (CHANNEL_IS_POPULATED(s->dimms, 0)) {
- MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f);
- MCHBAR8_OR(0x5d8, 0x7);
+ mchbar_clrsetbits8(0x5dd, 0x3f, 0x3f);
+ mchbar_setbits8(0x5d8, 0x7);
}
if (CHANNEL_IS_POPULATED(s->dimms, 1)) {
if (pci_read_config8(HOST_BRIDGE, 0x8) < 2) {
- MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f);
- MCHBAR8_OR(0x5d8, 1);
+ mchbar_clrsetbits8(0x5dd, 0x3f, 0x3f);
+ mchbar_setbits8(0x5d8, 1);
}
- MCHBAR8_OR(0x9dd, 0x3f);
- MCHBAR8_OR(0x9d8, 0x7);
+ mchbar_setbits8(0x9dd, 0x3f);
+ mchbar_setbits8(0x9d8, 0x7);
}
/* DDR3 reset */
if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) {
printk(BIOS_DEBUG, "DDR3 Reset.\n");
- MCHBAR8_AND(0x1a8, ~0x2);
- MCHBAR8_OR(0x5da, 0x80);
+ mchbar_clrbits8(0x1a8, 1 << 1);
+ mchbar_setbits8(0x5da, 1 << 7);
udelay(500);
- MCHBAR8_AND(0x1a8, ~0x2);
- MCHBAR8_AND(0x5da, ~0x80);
+ mchbar_clrbits8(0x1a8, 1 << 1);
+ mchbar_clrbits8(0x5da, 1 << 7);
udelay(500);
}
/* Pre jedec */
- MCHBAR8_OR(0x40, 0x2);
+ mchbar_setbits8(0x40, 1 << 1);
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
- MCHBAR32_OR(0x400*ch + 0x260, 1 << 27);
+ mchbar_setbits32(0x400 * ch + 0x260, 1 << 27);
}
- MCHBAR16_OR(0x212, 0xf000);
- MCHBAR16_OR(0x212, 0xf00);
+ mchbar_setbits16(0x212, 0xf << 12);
+ mchbar_setbits16(0x212, 0xf << 8);
printk(BIOS_DEBUG, "Done pre-jedec\n");
/* JEDEC reset */
@@ -2056,7 +2053,7 @@
}
/* After JEDEC reset */
- MCHBAR8_AND(0x40, ~0x2);
+ mchbar_clrbits8(0x40, 1 << 1);
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
reg32 = (2 << 18);
reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
@@ -2070,23 +2067,23 @@
reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
[s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] << 8;
}
- MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32);
- MCHBAR8_AND(0x400*ch + 0x274, ~0x80);
- MCHBAR8_OR(0x400*ch + 0x26c, 1);
- MCHBAR32(0x400*ch + 0x278) = 0x88141881;
- MCHBAR16(0x400*ch + 0x27c) = 0x41;
- MCHBAR8(0x400*ch + 0x292) = 0xf2;
- MCHBAR8_OR(0x400*ch + 0x271, 0xe);
+ mchbar_clrsetbits32(0x400 * ch + 0x274, 0xfff00, reg32);
+ mchbar_clrbits8(0x400 * ch + 0x274, 1 << 7);
+ mchbar_setbits8(0x400 * ch + 0x26c, 1 << 0);
+ mchbar_write32(0x400 * ch + 0x278, 0x88141881);
+ mchbar_write16(0x400 * ch + 0x27c, 0x41);
+ mchbar_write8(0x400 * ch + 0x292, 0xf2);
+ mchbar_setbits8(0x400 * ch + 0x271, 0xe);
}
- MCHBAR8_OR(0x2c4, 0x8);
- MCHBAR8_OR(0x2c3, 0x40);
- MCHBAR8_OR(0x2c4, 0x4);
+ mchbar_setbits8(0x2c4, 1 << 3);
+ mchbar_setbits8(0x2c3, 1 << 6);
+ mchbar_setbits8(0x2c4, 1 << 2);
printk(BIOS_DEBUG, "Done post-jedec\n");
/* Set DDR init complete */
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
- MCHBAR32_OR(0x400*ch + 0x268, 0xc0000000);
+ mchbar_setbits32(0x400 * ch + 0x268, 3 << 30);
}
/* Dummy reads */
@@ -2104,14 +2101,14 @@
/* Finish rcven */
FOR_EACH_CHANNEL(ch) {
- MCHBAR8_AND(0x400*ch + 0x5d8, ~0xe);
- MCHBAR8_OR(0x400*ch + 0x5d8, 0x2);
- MCHBAR8_OR(0x400*ch + 0x5d8, 0x4);
- MCHBAR8_OR(0x400*ch + 0x5d8, 0x8);
+ mchbar_clrbits8(0x400 * ch + 0x5d8, 7 << 1);
+ mchbar_setbits8(0x400 * ch + 0x5d8, 1 << 1);
+ mchbar_setbits8(0x400 * ch + 0x5d8, 1 << 2);
+ mchbar_setbits8(0x400 * ch + 0x5d8, 1 << 3);
}
- MCHBAR8_OR(0x5dc, 0x80);
- MCHBAR8_AND(0x5dc, ~0x80);
- MCHBAR8_OR(0x5dc, 0x80);
+ mchbar_setbits8(0x5dc, 1 << 7);
+ mchbar_clrbits8(0x5dc, 1 << 7);
+ mchbar_setbits8(0x5dc, 1 << 7);
/* XXX tRD */
@@ -2137,9 +2134,9 @@
printk(BIOS_DEBUG, "Done enhanced mode\n");
/* Periodic RCOMP */
- MCHBAR16_AND_OR(0x160, ~0xfff, 0x999);
- MCHBAR16_OR(0x1b4, 0x3000);
- MCHBAR8_OR(0x130, 0x82);
+ mchbar_clrsetbits16(0x160, 0xfff, 0x999);
+ mchbar_setbits16(0x1b4, 0x3000);
+ mchbar_setbits8(0x130, 1 << 7 | 1 << 1);
printk(BIOS_DEBUG, "Done PRCOMP\n");
/* Power settings */
@@ -2153,10 +2150,10 @@
*/
if (ME_UMA_SIZEMB != 0) {
if (RANK_IS_POPULATED(s->dimms, 0, 0) || RANK_IS_POPULATED(s->dimms, 1, 0))
- MCHBAR8_OR(0xa2f, 1 << 0);
+ mchbar_setbits8(0xa2f, 1 << 0);
if (RANK_IS_POPULATED(s->dimms, 0, 1) || RANK_IS_POPULATED(s->dimms, 1, 1))
- MCHBAR8_OR(0xa2f, 1 << 1);
- MCHBAR32_OR(0xa30, 1 << 26);
+ mchbar_setbits8(0xa2f, 1 << 1);
+ mchbar_setbits32(0xa30, 1 << 26);
}
printk(BIOS_DEBUG, "Done raminit\n");
diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index c79fdc3..d3b1b31 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -30,16 +30,16 @@
/* Reset the DQS probe, on both channels? */
for (u8 i = 0; i < TOTAL_CHANNELS; i++) {
- MCHBAR8(RESET_CNTL(i)) &= ~0x2;
+ mchbar_clrbits8(RESET_CNTL(i), 1 << 1);
udelay(1);
- MCHBAR8(RESET_CNTL(i)) |= 0x2;
+ mchbar_setbits8(RESET_CNTL(i), 1 << 1);
udelay(1);
}
mfence();
/* Read strobe */
read32((u32 *)addr);
mfence();
- return (MCHBAR8(sample_offset) >> 6) & 1;
+ return mchbar_read8(sample_offset) >> 6 & 1;
}
static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane)
@@ -51,21 +51,21 @@
printk(RAM_SPEW, " Programming timings:Coarse: %d, Medium: %d, TAP: %d, PI: %d\n",
timing->coarse, timing->medium, timing->tap, timing->pi);
- reg32 = MCHBAR32(0x400 * channel + 0x248);
+ reg32 = mchbar_read32(0x400 * channel + 0x248);
reg32 &= ~0xf0000;
reg32 |= timing->coarse << 16;
- MCHBAR32(0x400 * channel + 0x248) = reg32;
+ mchbar_write32(0x400 * channel + 0x248, reg32);
- reg16 = MCHBAR16(0x400 * channel + 0x58c);
+ reg16 = mchbar_read16(0x400 * channel + 0x58c);
reg16 &= ~(3 << (lane * 2));
reg16 |= timing->medium << (lane * 2);
- MCHBAR16(0x400 * channel + 0x58c) = reg16;
+ mchbar_write16(0x400 * channel + 0x58c, reg16);
- reg8 = MCHBAR8(0x400 * channel + 0x560 + lane * 4);
+ reg8 = mchbar_read8(0x400 * channel + 0x560 + lane * 4);
reg8 &= ~0x7f;
reg8 |= timing->tap;
reg8 |= timing->pi << 4;
- MCHBAR8(0x400 * channel + 0x560 + lane * 4) = reg8;
+ mchbar_write8(0x400 * channel + 0x560 + lane * 4, reg8);
}
static int increase_medium(struct rec_timing *timing)
@@ -241,8 +241,7 @@
{
program_timing(timing, channel, lane);
/* Set receive enable bit */
- MCHBAR16(0x400 * channel + 0x588) = (MCHBAR16(0x400 * channel + 0x588)
- & ~(3 << (lane * 2))) | (1 << (lane * 2));
+ mchbar_clrsetbits16(0x400 * channel + 0x588, 3 << (lane * 2), 1 << (lane * 2));
if (find_dqs_low(channel, lane, addr, timing))
return -1;
@@ -275,8 +274,7 @@
program_timing(timing, channel, lane);
/* Unset receive enable bit */
- MCHBAR16(0x400 * channel + 0x588) = MCHBAR16(0x400 * channel + 0x588) &
- ~(3 << (lane * 2));
+ mchbar_clrbits16(0x400 * channel + 0x588, 3 << (lane * 2));
return 0;
}
@@ -294,9 +292,9 @@
printk(BIOS_DEBUG, "Starting DQS receiver enable calibration\n");
- MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc;
- MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0xc;
- MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80;
+ mchbar_clrbits8(0x5d8, 3 << 2);
+ mchbar_clrbits8(0x9d8, 3 << 2);
+ mchbar_clrbits8(0x5dc, 1 << 7);
FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) {
mincoarse = 0xff;
/*
@@ -355,9 +353,8 @@
s->rcven_t[channel].medium[lane] = timing[lane].medium;
s->rcven_t[channel].tap[lane] = timing[lane].tap;
s->rcven_t[channel].pi[lane] = timing[lane].pi;
- MCHBAR16(0x400 * channel + 0x5fa) =
- (MCHBAR16(0x400 * channel + 0x5fa) &
- ~(3 << (lane * 2))) | (reg8 << (lane * 2));
+ mchbar_clrsetbits16(0x400 * channel + 0x5fa, 3 << (lane * 2),
+ reg8 << (lane * 2));
}
/* simply use timing[0] to program mincoarse */
timing[0].coarse = mincoarse;
diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c
index c70c1fb..1695ddd 100644
--- a/src/northbridge/intel/x4x/romstage.c
+++ b/src/northbridge/intel/x4x/romstage.c
@@ -37,7 +37,7 @@
if (s3_resume)
boot_path = BOOT_PATH_RESUME;
- if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
+ if (mchbar_read32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
mb_get_spd_map(spd_addr_map);